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Sheet Three

This document contains information about computer architecture and design basics. It includes examples of 32-bit instruction word formats and discusses the number of operations, registers, and immediate operands that can be addressed given the bit allocations. It also provides details about instruction formats, opcodes, register transfers, and simulating a single-cycle computer through examples and truth tables.

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21 views4 pages

Sheet Three

This document contains information about computer architecture and design basics. It includes examples of 32-bit instruction word formats and discusses the number of operations, registers, and immediate operands that can be addressed given the bit allocations. It also provides details about instruction formats, opcodes, register transfers, and simulating a single-cycle computer through examples and truth tables.

Uploaded by

Rana Badran
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Electrical Engineering Department

Module; [ELEC14I02] Computer Architecture


Sheet 3
Computer Design Basics

Sheet three
Computer Design Basics

1) A computer has a 32-bit instruction word broken into fields as follows:


Opcode, 6 bits; two register fields, 6 bits each; and one immediate
operand/register fields, 14 bits.
(a) What is the maximum number of operations that can be specified?
(b) How many registers can be addressed?
(c) What is the range of unsigned immediate operands that can be
provided?
(d) What is the range of signed immediate operands that can be provided,
assuming that bit 13 is the sign bit?

2) A digital computer has a memory unit with 32-bit instruction and a register
file with 32 registers. The instruction set consists of 110 different operations.
There is only one type of instruction format, with an opcode part, a register
file address, and an immediate operant part. Each instruction is stored in one
word of memory.
(a) How many bits are needed for the opcode part of the instruction?
(b) How many bits are left for the immediate part of the instruction?
(c) If the immediate operand is used as an unsigned address to memory,
what is the maximum number of words that can be addressed in
memory?
(d) What are the largest and the smallest algebraic values of signed 2’s
complement binary numbers that can be accommodated as an
immediate operand?

3) A digital computer has 32-bit instructions. There are a number of different


instruction formats and the number of bits in each format used for opcodes
varies depending on the bits needed for the other fields. If the first bit of the
opcode is 0, then there are 4 opcode bits. If the first bit of the opcode is 1 and
the second bit of the opcode is 0, then there are 6 opcode bits. If the first bit of
the opcode is 1 and the second bit of the opcode is 1, then there are 8 opcode
bits. Haw many distinct opcodes are available for this computer?

Page 1 of 4
4) The single-cycle computer in figure 1 executes the five instructions described
by the register transfers in the table that follows.

(a) Complete the following table, giving the binary instruction decoder
outputs from figure 2 during execution of each of the instructions:

Instruction – DA AA BA MB FS MD RW MW PL JB BC
Register Transfer

R[0] = R [7] R[3]

R[1]  M[R[4]]

R[2]  R[5] +2

R[3]  sl R[6]

If (R[4] = 0)
PC  PC + se PC

(b) Complete the following table, giving the instruction in binary for the
single-cycle computer that executes the register transfer (if any field is
not used, give it the value 0):

Instruction – Register Transfer Opcode DR SA` SB or Operand


R[0] = srR[7]
R[1]  M[R[6]]
R[2]  R[5] +4
R[3]  R[4] R[3]
R[4]  R[2] – R[1]

Page 2 of 4
5) Using the information in the truth table in table 1, verify that the design for the
single-bit outputs in the decoder in figure 2 is correct.

Table 1 - Truth Table for Instruction Decoder

6) Manually simulate the single-cycle computer in figure 1 for the following


sequence of instructions, assuming that each register initially contains contents
equal to its index (i.e. R0 contains 0, R1 contains 1, etc):

ADD R0, R1, R2


SUB R3, R4, R5
SUB R6, R7, R0
SUB R0, R0, R3
SUB R0, R0, R6
ST R7, R0
LD R7, R6
ADI R0, R6, 0
ADI R3, R6, 3

Give:
(a) the binary value of the instruction on the current line of the results
(b) the contents of any register changed by the instruction, or the location
and contents of any memory location changed by the instruction on the
next line of the results.
The results are positioned in this fashion because the new values do not
appear in a register or memory, due to the execution of an instruction, until
after a positive clock edge has occurred.

Page 3 of 4
Figure 1 - Block Diagram for a Single Cycle Computer

Figure 2 - Diagram of Instruction Decoder

Page 4 of 4

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