SCHOOL OF ELECTRONICS ENGINEERING

COURSE CODE: ECE 1003

COURSE NAME: DIGITAL LOGIC DESIGN

LABORATORY MANUAL
 LIST OF EXPERIMENTS

1. Verification of Basic gates in behavioural, structural and gate-level modelling.

2. Verification of Half Adder and Half Subtractor, Full Adder & Full Subtractor.

3. Design and verification of 4-bit Binary Adder and Subtractor.

4. Design and verification of 3×8 Decoder and 8×3 Encoder.

5. Design and verification of 4×1 MUX and 1×4 DeMUX.

6. Design and verification of 4-bit Magnitude Comparator.

7. Verification of Latches and Flip-Flops.

8. Design and verification of 4-bit Shift Registers.

9. Design and verification of 4-bit asynchronous counter.

10. Design and verification of 4-bit Synchronous counter.

11. Design and verification of 4-bit Ring and Johnson counter.

 Lab Experiment-1
Title of the Experiment: Verification of basic gates using behavioural, dataflow and gate-
level modelling.

Objective/Motivation: In this lab, all the basic logic gates are designed based on their truth
tables. The objective will be to test these gate designs on Xilinx simulation tool. The tests will
be performed for all the possible combinations of inputs to verify their functionality. Moreover,
the knowledge gained will be used to design much larger and complex logic designs.

Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
AND gate:
Logic Diagram:

Truth Table:

OR gate:
Logic Diagram:
Truth Table:

NOT gate:
Logic Diagram:

Truth Table:

NAND gate:
Logic Diagram:

Truth Table:
NOR gate:
Logic Diagram:

Truth Table:

XOR gate:
Logic Diagram:

Truth Table:

XNOR gate:
Logic Diagram:
Truth Table:

Verilog Code:
Test Bench: (For all gates)
a=0 ; b=0;
#100
a=0 ; b=1;
#100
a=1 ; b=0;
#100
a=1 ; b=1;
#100

Observation/Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are all the outputs verified according to the truth table?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-2
Title of the Experiment: To design adder and subtractor using Verilog code and compare with
their respective truth tables.
Objective/Motivation: In this lab, a half adder, full adder, half subtractor and full subtractor
are designed. The objective will be to test these designs on Xilinx simulation tool. The tests
will be performed for all the possible combinations of inputs to verify their functionality.
Moreover, the knowledge gained will be used to design much larger and complex logic designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
Half Adder:
Logic Diagram and Truth Table:
Half Subtractor:
Logic Diagram and Truth Table

Full Adder:
Logic Diagram And Truth Table
Full Subtractor:
Logic Diagram and Truth Table

Source codes:
Half Adder:
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor x1(sum,a,b);
and a1(carry,a,b);
endmodule

Half Subtractor:
module halfsub(diff, borrow, a, b);
output diff;
output borrow;
input a;
input b;
wire abar;
xor x1(diff,a,b);
not n1(abar,a);
and a1(borrow,abar,b);
endmodule

Full Adder:
module full_adder(sum, carry, a, b, c);
output sum;
output carry;
input a;
input b;
input c;
wire s1,t1,t2;
xor x1(s1,a,b);
xor x2(sum,s1,c);
and a1(t1,a,b);
and a2(t2,s1,c);
or o1(carry,t1,t2);
endmodule

Full Subtractor:
module fullsub(diff, borrow, a, b, c);
output diff;
output borrow;
input a;
input b;
input c;
wire abar,q,r,s;
xor x1(diff,a,b,c);
not n1(abar,a);
and a1(q,abar,b);
and a2(r,abar,c);
and a3(s,b,c);
or o1(borrow,q,r,s);
endmodule

Test Bench:
For Half Adder and Half Subtractor:
a=0 ; b=0;
#100
a=0 ; b=1;
#100
a=1 ; b=0;
#100
a=1 ; b=1;
#100

For Full Adder and Full Subtractor:

a=0 ; b=0; c=0;
#100
a=0 ; b=0; c=1;
#100
a=0 ; b=1; c=0;
#100
a=0 ; b=1; c=1;
#100
a=1 ; b=0; c=0;
#100
a=1 ; b=0; c=1;
#100
a=01; b=1; c=0;
#100
a=1; b=1; c=1;
#100

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are the adder and subtractor designs giving the correct output for any inputs?
2. What happens if the inputs are negative numbers?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-3
Title of the Experiment: To design adder and subtractor using Verilog code and compare with
their respective truth tables.
Objective/Motivation: In this lab, a half adder, full adder, half subtractor and full subtractor
are designed. The objective will be to test these designs on Xilinx simulation tool. The tests
will be performed for all the possible combinations of inputs to verify their functionality.
Moreover, the knowledge gained will be used to design much larger and complex logic designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
4-bit Binary Adder:

4-bit Binary Subtractor:

Source Code:
4-bit binary Adder:
module singleStage (input a, input b, input cin, output s, output cout );
assign s = a ^ b ^ cin;
assign cout = (a & b) | (a & cin) | (b & cin);
endmodule
Test bench:
a=4’b1001;
b=4’b1100;
cin = 1’b0;
#100
a=4’b0011;
b=4’b1100;
cin = 1’b1;
#100
a=4’b1110;
b=4’b0011;
cin = 1’b0;
#100
a=4’b1011;
b=4’b1001;
cin = 1’b1;
#100

4-bit binary Subtractor:

module singleStage (input a, input b, input cin, output s, output cout );
assign s = a ^ (~b) ^ cin;
assign cout = (a & (~b)) | (a & cin) | ((~b) & cin);
endmodule
Test bench:
a=4’b1001;
b=4’b1100;
cin = 1’b0;
#100
a=4’b0011;
b=4’b1100;
cin = 1’b1;
#100
a=4’b1110;
b=4’b0011;
cin = 1’b0;
#100
a=4’b1011;
b=4’b1001;
cin = 1’b1;
#100

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Do the binary adder and subtractor designs give the correct output for any inputs?
2. What happens if the inputs are negative numbers?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-4
Title of the Experiment: To design Encoder and Decoder using Verilog code and compare
with their respective truth tables.
Objective/Motivation: In this lab, a 8x3 encoder and 3x8 decoder are designed. The objective
will be to test these designs on Xilinx simulation tool. The tests will be performed for all the
possible combinations of inputs to verify their functionality. Moreover, the knowledge gained
will be used to design complex designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
Encoder:
Logic Diagram

Truth Table
Decoder:
Logic Diagram

Truth Table

Source code(s):
Encoder:
module Encoder(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
or(a,d4,d5,d6,d7);
or(b,d2,d3,d6,d7);
or(c,d1,d3,d5,d7);
endmodule

Decoder:
module Decoder(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
input a,b,c;
output d0,d1,d2,d3,d4,d5,d6,d7;
 assign d0=(~a&~b&~c),
d1=(~a&~b&c),
d2=(~a&b&~c),
d3=(~a&b&c),
d4=(a&~b&~c),
d5=(a&~b&c),
d6=(a&b&~c),
d7=(a&b&c);
endmodule

Test Bench:
Encoder:
module TestModule;
// Inputs
reg d0;
reg d1;
reg d2;
reg d3;
reg d4;
reg d5;
reg d6;
reg d7;
// Outputs
wire a;
wire b;
wire c;
// Instantiate the Unit Under Test (UUT)
Encoder uut (
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
 .d6(d6),
.d7(d7),
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
d0 = 0;
d1 = 0;
d2 = 0;
d3 = 0;
d4 = 0;
d5 = 0;
d6 = 0;
d7 = 0;
// Wait 100 ns for global reset to finish
#100;
d0 = 0;
d1 = 0;
d2 = 0;
d3 = 1;
d4 = 0;
d5 = 0;
d6 = 0;
d7 = 0;
// Wait 100 ns for global reset to finish
#100
end
endmodule
Decoder:
module TestModule;
// Inputs
reg a;
reg b;
reg c;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;
// Instantiate the Unit Under Test (UUT)
Decoder uut (
.a(a),
.b(b),
.c(c),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
a = 0;
b = 0;
c = 0;
 // Wait 100 ns for global reset to finish
#100;
a = 1;
b = 0;
c = 1;
// Wait 100 ns for global reset to finish
#100;
end
endmodule

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
3. Is the encoder and decoder design giving the correct output for any inputs?
4. What happens if the inputs are negative numbers?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-5
Title of the Experiment: To design 4:1 mux and 1:4 demux using Verilog code and compare
with their respective truth tables.
Objective/Motivation: In this lab, a 4:1 mux and 1:4 demux are designed. The objective will
be to test these designs on Xilinx simulation tool. The tests will be performed for all the possible
combinations of inputs to verify their functionality. Moreover, the knowledge gained will be
used to design complex designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
4:1 Multiplexer:
Truth Table and Logic Diagram
1:4 De-Multiplexer:

Source Code:
4:1 Multiplexer:
module 4*1mux(i,s,y);
inputs [3:0] i;
inputs [1:0] s;
output y;
reg y;
always@(i or s)
begin
y=0;
case(s)
2’b00 : y=i[0];
2’b01 : y=i[1];
2’b10 : y=i[2];
2’b11 : y=i[3];
default: y=0;
endcase
end
endmodule

1:4 De-Multiplexer:
module 1*4demux(d,s,e);
input e;
inputs [1:0] s;
output [3:0] d;
reg [3:0] d;
always@(e or s)
begin
case(s)
2’b00 : d[0]=e;
2’b01 : d[1]=e;
2’b10 : d[2]=e;
2’b11 : d[3]=e;
Default: d[0]=0;
endcase
endmodule

Test Bench:
4:1 Mux:
i[0] = 1 ; i[1] = 0; i[2] = 0; i[3] = 0; s[0]=0; s[1]=0
#100
i[0] = 0 ; i[1] = 1; i[2] = 0; i[3] = 0 ;s[0]=1; s[1]=0
#100
i[0] = 0 ; i[1] = 0; i[2] = 1; i[3] = 0 ;s[0]=0; s[1]=1
#100
i[0] = 0 ; i[1] = 0; i[2] = 0; i[3] = 1 ;s[0]=1; s[1]=1
#100
1:4 Demux:
s[0]=0; s[1]=0; e=1
#100
s[0]=1; s[1]=0; e=1
#100
s[0]=0; s[1]=1; e=1
#100
s[0]=1; s[1]=1; e=1
#100

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are the 4:1 MUX and 1:4 DEMUX designs giving the correct output for any inputs?
2. What happens if the inputs are negative numbers?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-6
Title of the Experiment: To design 4-bit magnitude comparator using Verilog code and
compare with their respective truth tables.
Objective/Motivation: In this lab, a 4-bit magnitude comparator is designed. The objective
will be to test this design on Xilinx simulation tool. The tests will be performed for all the
possible combinations of inputs to verify its functionality. Moreover, the knowledge gained
will be used to design multiple bit comparators.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
4-bit Comparator
Truth Table

Source Code:
module comparator(
Data_in_A, //input A
Data_in_B, //input B
less, //high when A is less than B
equal, //high when A is equal to B
greater //high when A is greater than B
);
//what are the input ports.
input [3:0] Data_in_A;
input [3:0] Data_in_B;
//What are the output ports.
output less;
output equal;
output greater;
//Internal variables
reg less;
reg equal;
reg greater;
 //When the inputs and A or B are changed execute this block
always @(Data_in_A or Data_in_B)
begin
if(Data_in_A > Data_in_B) begin //check if A is bigger than B.
less = 0;
equal = 0;
greater = 1; end
else if(Data_in_A == Data_in_B) begin //Check if A is equal to B
less = 0;
equal = 1;
greater = 0; end
else begin //Otherwise - check for A less than B.
less = 1;
equal = 0;
greater =0;
end
end
endmodule

Test Bench:
module tb_tm;
// Inputs
reg [3:0] Data_in_A;
reg [3:0] Data_in_B;
// Outputs
wire less;
wire equal;
wire greater;
// Instantiate the Unit Under Test (UUT)
comparator uut (
.Data_in_A(Data_in_A),
.Data_in_B(Data_in_B),
 .less(less),
.equal(equal),
.greater(greater)
);
initial begin
//Apply inputs
Data_in_A = 10;
Data_in_B = 12;
#100;
Data_in_A = 15;
Data_in_B = 11;
#100;
Data_in_A = 10;
Data_in_B = 10;
#100;
end
endmodule

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Is the comparator design giving the correct output for any inputs?
2. What happens if the inputs are negative numbers?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-7
Title of the Experiment: To design synchronous and asynchronous flipflops using verilog
code in Xilinx.
Objective/Motivation: In this lab, synchronous and asynchronous flipflops are designed. The
objective will be to test these designs on Xilinx simulation tool. The tests will be performed
for all the possible combinations of inputs to verify their functionality. Moreover, the
knowledge gained will be used to design complex designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
SR Flip Flip

JK Flip Flop

D Flip Flop with Synchronous Reset:

D Flip Flop with Asynchronous Reset:

Source Code(s):
D Flip Flop with Synchronous Reset:
module d_flipflop_synrst(data_in,data_out,clock,reset);
input data_in;
input clock,reset;
output reg data_out;
always@(posedge clock)
begin
if(reset)
data_out<=1'd0;
else
data_out<=data_in;v end
endmodule

Test Bench:
module Tb_dflipflop_synrst();
reg data_in;
reg clock,reset;
wire data_out;
d_flipflop_synrst UUT(.data_in(data_in),
.data_out(data_out),
.clock(clock),
.reset(reset));
initial begin
// Initiliase Input Stimulus
data_in = 0;
clock = 0;
reset=0;
end
always #100 clock=~clock;
//Stimulus
Initial
Begin
#200 data_in = 1'b1;
reset = 1'b1;
#200 data_in = 1'b1;
reset = 1'b1;
#300 data_in = 1'b1;
reset=1'b0;
#600 data_in = 1'b0;
#500 data_in = 1'b1;
#200 data_in = 1'b0;
#400 $stop;
end
endmodule

D Flip Flop with Asynchronous Reset:

module async_set_reset_dff (clk, d, set, q);
input clk, d, set, reset;
output q;
reg q;
always @ (posedge clk or posedge set or posedge reset)
begin
if (set)
q <= 1′ b1;
else if (reset)
q <= 1′ b0;
else
q <= d;
end
endmodule (OR)
module d_ff (
input clk,d,rst_n,
output reg q);
//Here is reset is Asynchronous, You have include in sensitivity list
always@(posedge clk ,negedge rst_n)
begin
if(!rst_n)
q <= 1'b0;
else
q <= d;
end
endmodule

Test Bench:
module tb_dff;
reg RST_n, CLK,D;
wire Q;
d_ff DFF (.clk(CLK) ,.rst_n(RST_n) ,.q(Q),.d(D));
initial begin
RST_n = 1'b0;
CLK =1'b0;
D =1'b0;
#5 RST_n = 1'b1;
#13 RST_n = 1'b0;
#7 RST_n = 1'b1;
#45 $finish;
end
always #3 CLK = ~CLK;
always #6 D = ~D;
always @(posedge CLK ,negedge RST_n)
$strobe("time =%0t \t INPUD VALUES \t D =%b RST_n =%b \t OUDPUD VALUES Q
=%d",$time,D,RST_n,Q);
endmodule

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are the flips flop designs giving the correct output for any inputs?
2. What happens if the clock frequency is increased to very high values?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-8
Title of the Experiment: To implement shift-right and shift-left register using Verilog code in
Xilinx.
Objective/Motivation: In this lab, a 4-bit shift-right and shift-left register is designed. The
objective will be to test these designs on Xilinx simulation tool. The tests will be performed
for all the possible combinations of inputs to verify their functionality. Moreover, the
knowledge gained will be used to design complex designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):

Source Code:
module slsr(sl, sr, din, clk, reset,Q);
input sl, sr, din, clk, reset;
output [7:0] Q;
reg [7:0] Q;
always @ (posedge clk) begin
if (~reset) begin
if (sl) begin
Q <= #2 {Q[6:0],din};
end
else if (sr) begin
Q <= #2 {din, Q[7:1]};
end
end
end
always @ (posedge reset) begin
Q<= 8'b00000000;
end
endmodule

Test Bench:
module main;
reg clk, reset, din, sl, sr;
wire [7:0] q;
slsr slsr1(sl, sr, din, clk,
reset, q);
initial begin
forever begin
clk <= 0;
#5
clk <= 1;
#5
clk <= 0;
end
end
initial begin
reset = 1;
#12
reset = 0;
#90
reset = 1;
#12
reset = 0;
end
initial begin
sl = 1;
sr = 0;
#50
sl = 0;
#12
sr = 1;
end
initial begin
forever begin
din = 0;
#7
din = 1;
#8
din = 0;
end
end
endmodule

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are the shift register designs giving the correct output for any inputs?
2. What happens if the clock frequency is increased to very high values?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-9
Title of the Experiment: To design asynchronous counter using Verilog code in Xilinx.
Objective/Motivation: In this lab, a 4-bit asynchronous counter is designed. The objective
will be to test these designs on Xilinx simulation tool. The tests will be performed for all the
possible combinations of inputs to verify their functionality. Moreover, the knowledge gained
will be used to design complex designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
Asynchronous counter:

Source Code:
module counter( clk, count );
input clk;
output[3:0] count;
reg[3:0] count;
wire clk;
initial
count = 4'b0;
always @( negedge clk )
count[0] <= ~count[0];
always @( negedge count[0] )
count[1] <= ~count[1];
always @( negedge count[1] )
count[2] <= ~count[2];
always @( negedge count[2] )
count[3] <= ~count[3];
endmodule

Test Bench:
initial begin
clk=1; end
always #20clk=~clk;
endmodule

Result:
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are the counter designs giving the correct output for any inputs?
2. What happens if the clock frequency is increased to very high values?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-10
Title of the Experiment: To design synchronous counter using Verilog code in Xilinx.
Objective/Motivation: In this lab, a 4-bit synchronous counter is designed. The objective will
be to test these designs on Xilinx simulation tool. The tests will be performed for all the possible
combinations of inputs to verify their functionality. Moreover, the knowledge gained will be
used to design complex designs.
Equipment required:
1. Zybo board - Zynq XC7Z010
2. Xilinx Vivado Design Suite 2016

Logic diagram(s):
Synchronous Counter:

Source Code:
module first_counter (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
input clock ;
input reset ;
input enable ;
output [3:0] counter_out ;
// By rule all the input ports should be wires
wire clock ;
wire reset ;
wire enable ;
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;
always @ (posedge clock)
begin : COUNTER // Block Name
if (reset == 1'b1) begin
counter_out <= #1 4'b0000;
end
else if (enable == 1'b1) begin
counter_out <= #1 counter_out + 1;
end
end // End of Block COUNTER
endmodule

Test Bench:
module first_counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] counter_out;
// Initialize all variables
initial begin
$display ("time\t clk reset enable counter");
$monitor ("%g\t %b %b %b %b",
$time, clock, reset, enable, counter_out);
clock = 1; // initial value of clock
reset = 0; // initial value of reset
enable = 0; // initial value of enable
#5 reset = 1; // Assert the reset
#10 reset = 0; // De-assert the reset
#10 enable = 1; // Assert enable
#100 enable = 0; // De-assert enable
#5 $finish; // Terminate simulation
End
// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end
// Connect DUT to test bench
first_counter U_counter (clock,reset,enable,counter_out);
endmodule

Result :
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
1. Are the counter designs giving the correct output for any inputs?
2. What happens if the clock frequency is increased to very high values?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.
 Lab Experiment-11
Title of the Experiment: To design Ring and Johnson counter using Verilog code in Xilinx.
Objective/Motivation: In this lab, a 4-bit Ring and Johnson counters are designed. The
objective will be to test these designs on Xilinx simulation tool. The tests will be performed
for all the possible combinations of inputs to verify their functionality. Moreover, the
knowledge gained will be used to design complex designs.
Equipment required:
3. Zybo board - Zynq XC7Z010
4. Xilinx Vivado Design Suite 2016

Logic diagram(s):
Ring Counter:

Johnson Counter:
Source Code:
Ring Counter:
module ring_count(q,clk,clr);
input clk,clr;
output [3:0]q;
reg [3:0]q;
always @(posedge clk)
if(clr==1)
q<=4′b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

Test Bench:
module ring_count_test();
reg clk_tb,clr_tb;
wire [3:0]q_tb;
ring_count dut1(q_tb,clk_tb,clr_tb);
initial
begin
$display(“time,\t clk_tb,\t clr_tb,\t q_tb”);
$monitor(“%g,\t %b,\t %b,\t %b”,$time,clk_tb,clr_tb,q_tb);
clr_tb=1′b0;
#50 clr_tb=1′b1;
#100 clr_tb=1′b0;
end
always
begin
#50 clk_tb=1′b1;
 #50 clk_tb=1′b0;
end
endmodule

Johnson Counter:
module johnson(Reset, Clock, Q);
input Reset, Clock;
output[3:0] Q;
reg [3:0] Q;
always @(negedge Reset or posedge Clock)
if(!Reset)
Q <= 0;
else
Q <= {{Q[2:0]},{~Q[3]}};
endmodule

Test Bench:
module johnsontstbnch;
reg rst,clk;
wire [7:0]q;
johnson jon (rst,clk,q);
initial
begin
clk=0;
rst = 0;
$monitor($time, ,”c=%b”,clk, , ,”r=%b”,rst, , ,”q=%b”,q);
#6 rst =1;
end
always #2 clk = ~clk;
initial #68 $finish;
endmodule
Result :
The simulation waveforms are obtained and verified with the expected waveforms.
Post-experiment questions to be answered:
3. Are the counter designs giving the correct output for any inputs?
4. What happens if the clock frequency is increased to very high values?
References
[1] M.Morris Mano, Michael D Ciletti, Digital Design , 5th edition , Pearson Publishers.