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Verilog Exp 1

The document describes an experiment to implement digital logic gates using Verilog. It discusses the hardware and software requirements. It then explains the theory of logic gates and lists different types of logic gates and their boolean expressions. The Verilog code for a top module with inputs a and b and outputs for AND, OR, NOT, NAND, NOR, XOR and XNOR gates is provided. The output shows the simulation waveform and RTL design matches the expected results.

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14 views3 pages

Verilog Exp 1

The document describes an experiment to implement digital logic gates using Verilog. It discusses the hardware and software requirements. It then explains the theory of logic gates and lists different types of logic gates and their boolean expressions. The Verilog code for a top module with inputs a and b and outputs for AND, OR, NOT, NAND, NOR, XOR and XNOR gates is provided. The output shows the simulation waveform and RTL design matches the expected results.

Uploaded by

usutkarsh0705
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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EXPERIMENT – 1

Obiective: Implementation of Digital Logic Gates using Verilog.


Resources Required:
Hardware requirements: Computer System.
Software requirements: XILINX VIVÄDO Software.
Theory:
A logic gate is a device that acts as a building block for digital circuits.
They perform basic logical functions that are fundamental to digital
circuits. Most electronic devices we use today will have some form of
logic gates in them. We can implement different digital circuits with the
combination of various logic gates.
Types of different digital logic gates and their Boolean expression is given
below in Table 1 (Inputs: a and “b”, and Output is “f”)

Table 1: Logic Gates and Boolean Expressions


S.No. Logic Gate Boolean Expression
1. OR f=(a+b)
2. AND f=(a.b)
3. NOT f=(a)’
4. NAND f=(a.b)’
5. NOR f=(a+b)’
6. XOR f=(a ⊕b)=(a’b+ab’)
7. XNOR f=(a⊙b)=(a’b’+ab)

Verilog Code:
• Top Module
timescale 1ns / 1ps
module Gates (a, b, out_and, out_or, out_not, out_nand, out_nor,
out_xor, out_xnor);
input [3:0] a, b;
output[3:0] out_and, out_or, out_not, out_nand, out_nor, out_xor,
out_xnor;
assign out_and=a&b;
assign out_or=a|b;
assign out_not=~a;
assign out_nand=~(a&b);
assign out_nor=~(a|b);
assign out_xor=a^b;
assign out_xnor=~(a^b);
endmodule

OUTPUT:
Figure l and Figure 2 shows the Simulation Waveform and RTL Design of
the above Verilog code respectively.

Figure 1: Simulation Waveform


Figure 2: RTL Design

Results :
Verilog code of Digital Logic Gates was simulated, and correct results were
obtained for all the Boolean operations, RTL schematic for the code was
generated.

Name- UTKARSH SRIVASTAVA


Roll No.- 323108110

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