COMSATS UNIVERSITY ISLAMABAD

Department of Electrical & Computer Engineering

Course name: Digital Logic Design

Lab report #: 03

Lab title: Introduction to Verilog and Simulation using XILINX ISE

Submitted by:

Student Name Registration #

Nayyab Kanwal FA23-BCE-088

Saman Kalsoom FA23-BCE-099

Zufishan Abbasi FA23-BCE-116

Submitted to: Dr.Irfan Ullah

Submission date: 27/09/2024
Remarks (if any):

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Objectives :

 In this lab, Verilog (Hardware Description Language) is introduced with

Xilinx ISE. Verilog is used to model d i g i t a l systems. It is most
commonly used in the design and verification of digital circuits.
 Xilinx ISE is a verification and simulation tool for Verilog, VHDL, System
Verilog, and mixed- language designs.

In-Lab Task 1:

Verify all the basic logic gates using the Xilinx ISE simulation tool and verify
your waveform with logic gates truth table.

i. Task 01: Write a Verilog code (Gate-Level) for NOT, OR, NOR,
NAND, XOR and XNOR.
ii. Task 02: Write a stimulus/test bench for Task 01 and show the
simulation results.

 AND Gate:

Verilog code of AND gate Test Bench of AND Gate:

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 a) Timing Diagram

 AND Gate:

 Verilog code of OR gate: Test Bench of OR Gate:

a) Timing Diagram:

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 NAND Gate:

 Verilog code of NAND gate:

b) Timing Diagram:

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 NOT Gate:

 Verilog code of NOT gate:

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 NOR Gate:

 Verilog code of NOR gate:

 Test Bench of NOR gate:

Timing Diagram:

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 XOR Gate:

 Verilog code of XOR gate:

 Test Bench Of XOR Gate:

Timing Diagram:

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 XNOR Gate:

 Verilog code of XNOR Gate:

 Test Bench Of XNOR Gate:

c) Timing Diagram:

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Truth Table:

A B A A OR A A A A A XNOR
NOT B NOR B NAND B XOR B AND B B
0 0 1 0 1 1 0 0 1
0 1 1 1 0 1 1 0 0
1 0 0 1 0 1 1 0 0
1 1 0 1 0 0 0 1 1

Explanation:

Task 01: Verilog Code for Basic Logic Gates

In Task 01, the objective is to write Verilog code using gate-level modeling to
represent six basic logic gates: NOT, OR, NOR, NAND, XOR, and XNOR.
Each gate is implemented as a separate module, which accepts one or two
input signals and produces a single output corresponding to the operation of
each gate. Gate-level modeling directly reflects the underlying hardware
design, allowing us to simulate the behavior of digital circuits in Verilog.

Task 02: Test Bench for Logic Gates

In Task 02, a test bench is written to validate the functionality of the logic
gates developed in Task 01. The test bench provides a set of input
combinations and monitors the outputs to verify correct behavior. The test
bench cycles through various input pairs for the two-input gates and a single
input for the NOT gate, displaying the results for each case. This test bench is
executed within a simulation tool, such as Xilinx ISE, which generates
waveforms to visualize the output for each gate. The waveforms are then
compared to the expected truth tables to confirm the gates’ accuracy.

Post-Lab:

Task 01: Write a Verilog code for the given Boolean function (e.g. 𝐹 = 𝑥 + 𝑥̅𝑦
+ 𝑦𝑧̅ ):

a) Using Gate-Level model (Provide Gate Level diagram and Truth Table)

b) Using Dataflow model

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Task 02: Write a stimulus/test bench for Task 01 and show the simulation
results.

 Verilog Code of Boolean function :

 Test Bench Of Boolean Function:

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Timing Diagram:

Truth Table:

x y z x’ Z’ (xy)’ yz’ F

0 0 0 1 1 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 1 1 1 1
0 1 1 1 0 1 0 1
1 0 0 0 1 0 0 1
1 0 1 0 0 0 0 1
1 1 0 0 1 0 1 1
1 1 1 0 0 0 0 1

Explanation:

Task 01: Verilog Code for Boolean Function

In Task 01, we need to write Verilog code to implement a Boolean function (𝐹

= 𝑥 + (xy)’ + 𝑦z’) using two methods: the Gate-Level model and the
Dataflow model. In the Gate-Level model, we directly use basic gates like
NOT, AND, and OR to create the function. The NOT gates invert values (x’ and
𝑧z’), the AND gates combine them with other inputs, and the OR gate adds the
terms together. On the other hand, the Dataflow model uses simpler code with
logical operations like OR (|), AND (&), and NOT (~) to describe the
behavior of the function without focusing on specific gates.

Task 02: Test bench and Simulation

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In Task 02, we write a test bench to check if both models (Gate-Level and
Dataflow) work correctly. The test bench gives different combinations of inputs
x, y and z and compares the output (F) from both models. We use the
$display command to show the results and $finish to stop the simulation.
It shows the results match the truth table of the Boolean function, proving the
code works as expected.

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