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EEE 306 Post LAB 6

This post lab report describes a module hierarchy in Verilog for a 4-bit adder/subtractor circuit. The report includes: 1) Code for a 1-bit full adder module and a 4-bit adder/subtractor module using the 1-bit module. 2) Text for a test bench to simulate the 4-bit circuit under different input conditions. 3) The report was submitted by a student for their Embedded Systems course lab assignment on FPGA programming using Verilog modules.

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Abu Saleh Bin Aftab
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11 views7 pages

EEE 306 Post LAB 6

This post lab report describes a module hierarchy in Verilog for a 4-bit adder/subtractor circuit. The report includes: 1) Code for a 1-bit full adder module and a 4-bit adder/subtractor module using the 1-bit module. 2) Text for a test bench to simulate the 4-bit circuit under different input conditions. 3) The report was submitted by a student for their Embedded Systems course lab assignment on FPGA programming using Verilog modules.

Uploaded by

Abu Saleh Bin Aftab
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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East West University

EEE Department
Post LAB Report

Course Code: EEE 306


Course Title: Embedded Systems
Section:01
Experiment No: 06
Experiment Title: Module Hierarchy in Verilog for FPGA Programming.
Name: Abu Saleh Bin Aftab Sakib
ID: 2020-2-80-019

Date of Submission:18/11/23

Course Instructor: Muhammed Mazharul Islam, Assistant Professor.


b)
ⅰ. Code:
module onebit_full_adder (
input A,
input B,
input carry_in,
output x,
output carry_out
);

assign x = A ^ B ^ carry_in;
assign carry_out = (A & B) | (B & carry_in) | (carry_in & A);

endmodule

module fourbit_adder_subtractor(
input [3:0] A,
input [3:0] B,
input carry_in,
input K,
output carry_out,
output [3:0] x
);

wire [3:0] f;
wire [4:0] y;
assign f = K ? ~B : B;

onebit_full_adder addersubt_0 (A[0], f[0], carry_in, x[0], y[0]);


onebit_full_adder addersubt_1 (A[1], f[1], y[0], x[1], y[1]);
onebit_full_adder addersubt_2 (A[2], f[2], y[1], x[2], y[2]);
onebit_full_adder addersubt_3 (A[3], f[3], y[2], x[3], y[3]);

assign carry_out = K ? y[4] : addersubt_3.carry_out;

endmodule

ⅱ. Gate level Schematic:


ⅲ. Technology Schematic:

RTL Schematic:
ⅳ. Text Bench Code:
module fadder_sub_t;

// Inputs
reg [3:0] A;
reg [3:0] B;
reg carry_in;
reg K;

// Outputs
wire carry_out;
wire [3:0] x;

// Instantiate the Unit Under Test (UUT)


fourbit_adder_subtractor uut (
.A(A),
.B(B),
.carry_in(carry_in),
.K(K),
.carry_out(carry_out),
.x(x)
);

initial begin
// Initialize Inputs
A = 0;
B = 0;
carry_in = 0;
K = 0;

// Wait 100 ns for global reset to finish


#100;
A=0; B=0; carry_in=0; K=1;
#50;
A=0; B=0; carry_in=1; K=0;
#50;
A=0; B=0; carry_in=1; K=1;
#50;
A=0; B=1; carry_in=0; K=0;
#50;
A=0; B=1; carry_in=0; K=1;
#50;
A=0; B=1; carry_in=1; K=0;
#50;
A=0; B=1; carry_in=1; K=1;
#50;
A=1; B=0; carry_in=0; K=0;
#50;
A=1; B=0; carry_in=0; K=1;
#50;
A=1; B=0; carry_in=1; K=0;
#50;
A=1; B=0; carry_in=1; K=1;
#50;
A=1; B=1; carry_in=0; K=0;
#50;
A=1; B=1; carry_in=0; K=1;
#50;
A=1; B=1; carry_in=1; K=0;
#50;
A=1; B=1; carry_in=1; K=1;

// Add stimulus here

end

endmodule

ⅴ. Timing Diagram:

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