Scribd
Upload
16 views6 pages

Lab1 2

The document describes several Verilog modules that implement logic gates and basic logic functions. It defines modules for a full adder, 8-bit adder, error detection, AND/OR gates, and XOR gates with timing delays.

Uploaded by

karnikrathva200
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
16 views6 pages

Lab1 2

The document describes several Verilog modules that implement logic gates and basic logic functions. It defines modules for a full adder, 8-bit adder, error detection, AND/OR gates, and XOR gates with timing delays.

Uploaded by

karnikrathva200
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
You are on page 1/ 6

--> Lab2__1 : -

full adder :-
module fulladd(
input a,
input b,
input cin,
output sum,

output cout
);
assign sum=(a^b^cin);

assign cout=((a&b)|(b&cin)|(a&cin));

endmodule

8 bit adder with flag set :-

module lab2_152_153(
input [7:0] a,
input [7:0] b,
input cin,
output [7:0] sum,
output cout,
output [4:0] flag
);
wire [6:0] c;
fulladd a1(a[0],b[0],cin,sum[0],c[0]);

fulladd a2(a[1],b[1],c[0],sum[1],c[1]);

fulladd a3(a[2],b[2],c[1],sum[2],c[2]);

fulladd a4(a[3],b[3],c[2],sum[3],c[3]);

fulladd a5(a[4],b[4],c[3],sum[4],c[4]);

fulladd a6(a[5],b[5],c[4],sum[5],c[5]);

fulladd a7(a[6],b[6],c[5],sum[6],c[6]);

fulladd a8(a[7],b[7],c[6],sum[7],cout);

assign flag[0]= ~(sum[0] | sum[1] | sum[2] | sum[3] | sum[4] | sum[5] | sum[6] |


sum[7]);
assign flag[1]= sum[0] ^sum[1] ^sum[2] ^sum[3] ^sum[5] ^sum[6] ^sum[7];
assign flag[2]=c[3];
assign flag[3] = ~sum[0];
assign flag[4] = cout;

endmodule

test bench :-
module lab2_152_153_test;

// Inputs
reg [7:0] a;
reg [7:0] b;

reg cin;

wire [7:0] sum;

wire cout;

wire [4:0] flag;

lab2_152_153 uut (.a(a),.b(b),.cin(cin),.sum(sum),.cout(cout),.flag(flag) );

initial begin

#10 a=8'b00000001;b=8'b00000001;cin=1'b0;

#10 a=8'b00000001;b=8'b00000001;cin=1'b1;

#10 a=8'b00000010;b=8'b00000011;cin=1'b0;

#10 a=8'b10000001;b=8'b10000001;cin=1'b0;

#10 a=8'b00011001;b=8'b00110001;cin=1'b0;

#10 a=8'b00000011;b=8'b00000011;cin=1'b1;

#10 a=8'b11111111;b=8'b00000001;cin=1'b0;

#10 a=8'b11111111;b=8'b00000000;cin=1'b1;

#10 a=8'b11111111;b=8'b11111111;cin=1'b0;

#10 $stop;

// Add stimulus here

end

endmodule

--> Lab2__2 : -

Question 2(1) :-

encoded output :-

module Q2(
input [7:0] a,
output [8:0] cout
);
assign cout[1]=a[0];
assign cout[2]=a[1];
assign cout[3]=a[2];
assign cout[4]=a[3];
assign cout[5]=a[4];
assign cout[6]=a[5];
assign cout[7]=a[6];
assign cout[8]=a[7];
assign cout[0]=a[0]^a[1]^a[2]^a[3]^a[4]^a[5]^a[6]^a[7];

endmodule

test bench :-

module Q2_test;

// Inputs
reg [7:0] a;

// Outputs
wire [8:0] cout;

// Instantiate the Unit Under Test (UUT)


Q2 uut (
.a(a),
.cout(cout)
);

initial begin
// Initialize Inputs
a = 8'b11111111;

// Wait 100 ns for global reset to finish


#10;
a = 8'b11111000;
#10 $stop;
// Add stimulus her

end

endmodule

Graph :-
18

Questio :- 2(2)

Error code :-

module Q2_2(
input [8:0] a,
output error
);

assign error = a[0]^a[1]^a[2]^a[3]^a[4]^a[5]^a[6]^a[7]^a[8];

endmodule

test bench :-

module Q2_2_test;
// Inputs
reg [8:0] a;

// Outputs
wire error;

// Instantiate the Unit Under Test (UUT)


Q2_2 uut (
.a(a),
.error(error)
);

initial begin
// Initialize Inputs
a = 9'b111111111;

// Wait 100 ns for global reset to finish


#10;
a = 9'b101111000;
#10 $stop;
// Add stimulus here

end

endmodule

--> Lab1: -

module lab6_1(
input [0:0] v1,
input [0:0] v2,
input [0:0] v3,
input [0:0] v4,
input [0:0] v5,
input [0:0] v6,
output [0:0] out
);
wire w1,w2,w3;
and g1(w1,v1,v2),g2(w2,v3,v4),g3(w3,v5,v6);
or g4(out,w1,w2,w3);

endmodule
`timescale 1ns / 1ps

module LAB6_1_2(
input [0:0] v1,
input [0:0] v2,
input [0:0] v3,
output [0:0] out
);
assign out=(v1&v2)|(v2&v3)|(v1&v3);

endmodule
module Lab6_1_3(
input [0:0] v1,
input [0:0] v2,
input [0:0] v3,
input [0:0] v4,
input [0:0] v5,
input [0:0] v6,
output reg out
);

always@(v1,v2,v3,v4,v5,v6)
if ((v1&&v2)||(v3&&v4)||(v5&&v6))
out=1;
else
out=0;

endmodule
module lab6_2_1_S(
input v1,
input v2,
input v3,
output out
);
wire x;
wire y=1'b1;
LAB6_1_2 g1(v1,v2,v3,x);
nand n1(out,x,y);

endmodule
module lab6_que3(
input [0:0] a,
input [0:0] b,
output [0:0] out
);
wire a1,a2,a3,a4;
assign #0.03 a1=~a;
assign #0.03 a2=~b;
assign #1 a3=a&a2;
assign #1 a4=b&a1;
assign #1.5 out=a3|a4;

endmodule
module Lab6_que4(
input a,
input b,
input c,
input d,
output out
);
assign out = (~(a & b) | (c & d)) ^ ((a & b) | ~(c & d));

endmodule
module lab6_qu4s(
input a,
input b,
input c,
input d,
output y
);
wire x1,x2,x3,x4,x5,x6;
and a1(x1,a,b),a2(x2,c,d);
not n1(x3,x1),n2(x4,x2);
or o1(x5,x4,x1),o(x6,x3,x2);
xor y1(y,x5,x6);

endmodule

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy