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Structural Counter 8

This document describes a module called Counter8_tp that contains a counter, multiplexers, and other logic to display a changing decimal number on a 7-segment display. It instantiates submodules for clock division, incrementing/decrementing, comparing values, and multiplexing signals to control the display.

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16 views11 pages

Structural Counter 8

This document describes a module called Counter8_tp that contains a counter, multiplexers, and other logic to display a changing decimal number on a 7-segment display. It instantiates submodules for clock division, incrementing/decrementing, comparing values, and multiplexing signals to control the display.

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arturorexz851
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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`timescale 1ns / 1ps

module Counter8_tp(
input CLK100MHZ, BTNR, BTNL, BTND, [15:0] SW,
output CA, CB, CC, CD, CE, CF, CG, DP, [7:0] AN );

wire SegA, SegB, SegC, SegD, SegE, SegF, SegG;


wire Clock, ClkOut;
wire [7:0]Count;
wire [3:0]Mux;
wire [1:0]Print;

assign LED = SW;

ClkDiv1Hz Clocking( CLK100MHZ, BTND, Clock );


ClkDivDisp Lighting_Mcqueen( CLK100MHZ, BTND, ClkOut );

Counter8 Counter( Clock, BTNR, BTNL, SW[0], Count );

Mux8 Muxing( Count[7:0], ClkOut,


Mux );

Printf CoutOut( ClkOut,


Print );

SSD HDD( Mux[3], Mux[2], Mux[1], Mux[0],


SegA, SegB, SegC, SegD, SegE, SegF, SegG );

Invert8 InvSeg( SegA, SegB, SegC, SegD, SegE, SegF, SegG, 0,


CA, CB, CC, CD, CE, CF, CG, DP );

Invert8 InvAN( 0, 0, 0, 0, 0, 0, Print[1], Print[0],


AN[ 7], AN[ 6], AN[ 5], AN[ 4], AN[ 3], AN[ 2], AN[ 1], AN[ 0] );

endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
//
// Create Date: 23:23:54 04/21/2012
// Author: Roman Lysecky
//
// modified by SJKranock 2019/12/25
// parameter DivVal = xxxxxxxxxxxxxxxxxxxxxxxx
//
//////////////////////////////////////////////////////////////////////////////////

module ClkDiv1Hz( ClkIn, Reset, Clock );

input ClkIn, Reset;


output reg Clock;

parameter DivVal = 10_000_000; // xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx


reg [31:0] DivCnt;

always @ ( posedge ClkIn ) begin


if ( Reset ) begin
Clock = 0;
DivCnt = 0;
end
else begin
if ( DivCnt == DivVal ) begin
Clock = ~Clock;
DivCnt = 0;
end
else begin
DivCnt = DivCnt + 1;
end
end
end
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
//
// Create Date: 23:23:54 04/21/2012
// Author: Roman Lysecky
//
// modified by SJKranock 2019/12/25
// parameter DivVal = xxxxxxxxxxxxxxxxxxxxxxxx
//
//////////////////////////////////////////////////////////////////////////////////

module ClkDivDisp( ClkIn, Reset, Clock );

input ClkIn, Reset;


output reg Clock;

parameter DivVal = 1_000_000; // xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx


reg [31:0] DivCnt;

always @ ( posedge ClkIn ) begin


if ( Reset ) begin
Clock = 0;
DivCnt = 0;
end
else begin
if ( DivCnt == DivVal ) begin
Clock = ~Clock;
DivCnt = 0;
end
else begin
DivCnt = DivCnt + 1;
end
end
end
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
// Engineer: Kranock
// Create Date: 2017/10/07
// Description: Inverts 8 discrete inputs
//////////////////////////////////////////////////////////////////////////////////
module Invert8( input In0, In1, In2, In3, In4, In5, In6, In7,
output reg Out0, Out1, Out2, Out3, Out4, Out5, Out6, Out7 );

always @ ( In0, In1, In2, In3, In4, In5, In6, In7 ) begin
Out0 = ~In0;
Out1 = ~In1;
Out2 = ~In2;
Out3 = ~In3;
Out4 = ~In4;
Out5 = ~In5;
Out6 = ~In6;
Out7 = ~In7;
end
endmodule

`timescale 1ns / 1ps

module Mux8( input [7:0]Count, ClkOut,


output reg [3:0] Mux );

always @ (Count, ClkOut) begin

if ( ClkOut ) begin
Mux[0] = Count[4];
Mux[1] = Count[5];
Mux[2] = Count[6];
Mux[3] = Count[7];
end

else begin
Mux[0] = Count[0];
Mux[1] = Count[1];
Mux[2] = Count[2];
Mux[3] = Count[3];
end

end
endmodule

`timescale 1ns / 1ps

module Printf( input ClkOut,


output reg [1:0] Print );

always @ (ClkOut) begin


if (ClkOut) begin
Print[1] = 1;
Print[0] = 0;
end
else begin
Print[1] = 0;
Print[0] = 1;
end
end
endmodule

`timescale 1ns / 1ps


//////////////////////////////////////////////////////////////////////////////////
//
// Comments go here
//
//////////////////////////////////////////////////////////////////////////////////

module SSD(
input In3, In2, In1, In0,
output reg SegA, SegB, SegC, SegD, SegE, SegF, SegG );

always @ ( In3, In2, In1, In0 ) begin

SegA = (~In3&~In2&~In1&~In0)|(~In3&~In2&In1&~In0)|(~In3&~In2&In1&In0)|
(~In3&In2&~In1&In0)|(~In3&In2&In1&~In0)|(~In3&In2&In1&In0)|(In3&~In2&~In1&~In0)|
(In3&~In2&~In1&In0)|(In3&~In2&In1&~In0)|(In3&In2&~In1&~In0)|(In3&In2&In1&~In0)|
(In3&In2&In1&In0);
SegB = (~In3&~In2&~In1&~In0)|(~In3&~In2&~In1&In0)|(~In3&~In2&In1&~In0)|
(~In3&~In2&In1&In0)|(~In3&In2&~In1&~In0)|(~In3&In2&In1&In0)|(In3&~In2&~In1&~In0)|
(In3&~In2&~In1&In0)|(In3&~In2&In1&~In0)|(In3&In2&~In1&In0);
SegC = (~In3&~In2&~In1&~In0)|(~In3&~In2&~In1&In0)|(~In3&~In2&In1&In0)|
(~In3&In2&~In1&~In0)|(~In3&In2&~In1&In0)|(~In3&In2&In1&~In0)|(~In3&In2&In1&In0)|
(In3&~In2&~In1&~In0)|(In3&~In2&~In1&In0)|(In3&~In2&In1&~In0)|(In3&~In2&In1&In0)|
(In3&In2&~In1&In0);
SegD = (~In3&~In2&~In1&~In0)|(~In3&~In2&In1&~In0)|(~In3&~In2&In1&In0)|
(~In3&In2&~In1&In0)|(~In3&In2&In1&~In0)|(In3&~In2&~In1&~In0)|(In3&~In2&In1&In0)|
(In3&In2&~In1&In0)|(In3&In2&In1&~In0)|(In3&In2&~In1&~In0);
SegE = (~In3&~In2&~In1&~In0)|(~In3&~In2&In1&~In0)|(~In3&In2&In1&~In0)|
(In3&~In2&~In1&~In0)|(In3&~In2&In1&~In0)|(In3&~In2&In1&In0)|(In3&In2&~In1&~In0)|
(In3&In2&~In1&In0)|(In3&In2&In1&~In0)|(In3&In2&In1&In0);
SegF = (~In3&~In2&~In1&~In0)|(~In3&In2&~In1&~In0)|(~In3&In2&~In1&In0)|
(~In3&In2&In1&~In0)|(In3&~In2&~In1&~In0)|(In3&~In2&~In1&In0)|(In3&~In2&In1&~In0)|
(In3&~In2&In1&In0)|(In3&In2&~In1&~In0)|(In3&In2&In1&~In0)|(In3&In2&In1&In0);
SegG = (~In3&~In2&In1&~In0)|(~In3&~In2&In1&In0)|(~In3&In2&~In1&~In0)|
(~In3&In2&~In1&In0)|(~In3&In2&In1&~In0)|(In3&~In2&~In1&~In0)|(In3&~In2&~In1&In0)|
(In3&~In2&In1&~In0)|(In3&~In2&In1&In0)|(In3&In2&~In1&In0)|(In3&In2&In1&~In0)|
(In3&In2&In1&In0);

end

endmodule

`timescale 1ns / 1ps

module Counter8(
input Clock,
input Reset,
input Pause,
input Up,
output reg [7:0] Count);

wire [7:0]CountNext;
wire [7:0]Answer;
wire [7:0]CountPlus;
wire [7:0]CountMinus;
wire eq_27;
wire eq_0;
wire [7:0]Increasing;
wire [7:0]Decreasing;

//Incrementer-Decrementer
Incrementer Audi(Count, 1, CountPlus);
Decrementer Subaru( Count, 1, 1, CountMinus);

//Comparators
Comparator_8 NissanMaxima(Count, 39, eq_27, lt_27, gt_27);
Comparator_8 MiniCooper(Count, 0, eq_0, lt_0, gt_0);

//Muxes
Mux_16x8 Lamborghini(eq_27, CountPlus, 0, Increasing);
Mux_16x8 Ferrari(eq_0, CountMinus, 39, Decreasing);
Mux_16x8 Dealership(Up, Decreasing, Increasing , Answer);

// Register
Register Registration(Clock, Reset, ~Pause, Answer, CountNext);

always @( Count ) begin


Count = CountNext;
end

endmodule

`timescale 1ns / 1ps

module Incrementer(
input [7:0]A, B,
output reg [7:0]S);

wire c0, c1, c2, c3, c4, c5, c6, c7, s0, s1, s2, s3, s4, s5, s6, s7;

Half_Adder (A[0], B, c0, s0);


Half_Adder (A[1], c0, c1, s1);
Half_Adder (A[2], c1, c2, s2);
Half_Adder (A[3], c2, c3, s3);
Half_Adder (A[4], c3, c4, s4);
Half_Adder (A[5], c4, c5, s5);
Half_Adder (A[6], c5, c6, s6);
Half_Adder (A[7], c6, c7, s7);

always @(s0, s1, s2, s3, s4, s5, s6, s7) begin
S[0] = s0;
S[1] = s1;
S[2] = s2;
S[3] = s3;
S[4] = s4;
S[5] = s5;
S[6] = s6;
S[7] = s7;
end

endmodule

`timescale 1ns / 1ps

module Decrementer(
input [7:0]A, [7:0]B, C,
output reg [7:0]D);

wire c0, c1, c2, c3, c4, c5, c6, c7, s0, s1, s2, s3, s4, s5, s6, s7, y0, y1,
y2, y3, y4, y5, y6, y7, x0, x1, x2, x3, x4, x5, x6, x7;

Half_Adder (~B[0], C, c0, s0);


Half_Adder (~B[1], c0, c1, s1);
Half_Adder (~B[2], c1, c2, s2);
Half_Adder (~B[3], c2, c3, s3);
Half_Adder (~B[4], c3, c4, s4);
Half_Adder (~B[5], c4, c5, s5);
Half_Adder (~B[6], c5, c6, s6);
Half_Adder (~B[7], c6, c7, s7);

Full_Adder (A[0], s0, 0, y0, x0);


Full_Adder (A[1], s1, y0, y1, x1);
Full_Adder (A[2], s2, y1, y2, x2);
Full_Adder (A[3], s3, y2, y3, x3);
Full_Adder (A[4], s4, y3, y4, x4);
Full_Adder (A[5], s5, y4, y5, x5);
Full_Adder (A[6], s6, y5, y6, x6);
Full_Adder (A[7], s7, y6, y7, x7);

always @(x0, x1, x2, x3, x4, x5, x6, x7) begin
D[0] = x0;
D[1] = x1;
D[2] = x2;
D[3] = x3;
D[4] = x4;
D[5] = x5;
D[6] = x6;
D[7] = x7;
end

endmodule

`timescale 1ns / 1ps

module Full_Adder(
input A, B, cin,
output reg co, reg S);

wire F, G, H, W, X, Y, Z, M, N;

AND_2x1(A, B, F);
AND_2x1(A, cin, G);
AND_2x1(B, cin, H);
OR_3x1(F, G, H, M);

AND_3x1(~A, ~B, cin, W);


AND_3x1(~A, B, ~cin, X);
AND_3x1(A, ~B, ~cin, Y);
AND_3x1(A, B, cin, Z);
OR_4x1(W, X, Y, Z, N);

always @(M, N) begin


co = M;
S = N;
end

endmodule

`timescale 1ns / 1ps

module Half_Adder(
input A, B,
output reg co, reg S);

wire W, X, Y, Z;

AND_2x1(A, B, W);
AND_2x1(A, ~B, X);
AND_2x1(~A, B, Y);
OR_2x1(X, Y, Z);

always @(W, Z) begin


co = W;
S = Z;
end

endmodule

`timescale 1ns / 1ps

module Comparator_8(
input [7:0]A, [7:0]B,
output reg eqo, reg lto, reg gto);

wire eq0, eq1, eq2, eq3, eq4, eq5, eq6, eq7, lt0, lt1, lt2, lt3, lt4, lt5, lt6,
lt7, gt0, gt1, gt2, gt3, gt4, gt5, gt6, gt7;

Comparator(A[7], B[7], 1, 0, 0, eq0, lt0, gt0);


Comparator(A[6], B[6], eq0, lt0, gt0, eq1, lt1, gt1);
Comparator(A[5], B[5], eq1, lt1, gt1, eq2, lt2, gt2);
Comparator(A[4], B[4], eq2, lt2, gt2, eq3, lt3, gt3);
Comparator(A[3], B[3], eq3, lt3, gt3, eq4, lt4, gt4);
Comparator(A[2], B[2], eq4, lt4, gt4, eq5, lt5, gt5);
Comparator(A[1], B[1], eq5, lt5, gt5, eq6, lt6, gt6);
Comparator(A[0], B[0], eq6, lt6, gt6, eq7, lt7, gt7);

always @(eq7, lt7, gt7) begin


eqo = eq7;
lto = lt7;
gto = gt7;
end

endmodule

`timescale 1ns / 1ps

module Comparator(
input A, B, eqi, lti, gti,
output reg eq, reg lt, reg gt);

wire W, X, Y, Z, F, L, E, G;

AND_3x1(eqi, A, ~B, W);


OR_2x1(gti, W, G);

AND_3x1(eqi, ~A, B, X);


OR_2x1(lti, X, L);

AND_2x1(A, B, Y);
AND_2x1(~A, ~B, Z);
OR_2x1(Y, Z, F);
AND_2x1(eqi, F, E);

always @(E, L, G) begin


gt = G;
lt = L;
eq = E;
end

endmodule

`timescale 1ns / 1ps

module Mux_16x8(
input S, [7:0]A, [7:0]B,
output reg [7:0]Y);

Mux_2x1(S, A[7], B[7], y7);


Mux_2x1(S, A[6], B[6], y6);
Mux_2x1(S, A[5], B[5], y5);
Mux_2x1(S, A[4], B[4], y4);
Mux_2x1(S, A[3], B[3], y3);
Mux_2x1(S, A[2], B[2], y2);
Mux_2x1(S, A[1], B[1], y1);
Mux_2x1(S, A[0], B[0], y0);

always @(y0, y1, y2, y3, y4, y5, y6, y7) begin
Y[7] = y7;
Y[6] = y6;
Y[5] = y5;
Y[4] = y4;
Y[3] = y3;
Y[2] = y2;
Y[1] = y1;
Y[0] = y0;
end

endmodule

`timescale 1ns / 1ps

module Mux_2x1(
input S, A, B,
output reg Z);

wire X, Y;

AND_2x1(S, B, W);
AND_2x1(~S, B, X);
OR_2x1(W, X, Y);

always @(Y) begin


Z = Y;
end

endmodule

`timescale 1ns / 1ps

module Register(
input clk, clr, id, [7:0]D,
output reg [7:0]Q);

wire y7, y6, y5, y4, y3, y2, y1, y0, x0, x1, x2, x3, x4, x5, x6, x7;

Mux_4x1(clr, id, q7, 0, D[7], q7, y7);


Mux_4x1(clr, id, q6, 0, D[6], q6, y6);
Mux_4x1(clr, id, q5, 0, D[5], q5, y5);
Mux_4x1(clr, id, q4, 0, D[4], q4, y4);
Mux_4x1(clr, id, q3, 0, D[3], q3, y3);
Mux_4x1(clr, id, q2, 0, D[2], q2, y2);
Mux_4x1(clr, id, q1, 0, D[1], q1, y1);
Mux_4x1(clr, id, q0, 0, D[0], q0, y0);

DFlipFlop(clk, y7, x7);


DFlipFlop(clk, y6, x6);
DFlipFlop(clk, y5, x5);
DFlipFlop(clk, y4, x4);
DFlipFlop(clk, y3, x3);
DFlipFlop(clk, y2, x2);
DFlipFlop(clk, y1, x1);
DFlipFlop(clk, y0, x0);

always @(x0, x1, x2, x3, x4, x5, x6, x7) begin
Q[7] = x7;
Q[6] = x6;
Q[5] = x5;
Q[4] = x4;
Q[3] = x3;
Q[2] = x2;
Q[1] = x1;
Q[0] = x0;
end

endmodule

`timescale 1ns / 1ps

module Mux_4x1(
input s1, s0, i3, i2, i1, i0,
output reg Y);

wire A, B, C, D;

AND_3x1(~s1, ~s0, i0, A);


AND_3x1(~s1, s0, i1, B);
AND_3x1(s1, ~s0, i2, C);
AND_3x1(s1, s0, i3, D);
OR_4x1(A, B, C, D, E);

always @(E) begin


Y = E;
end

endmodule

`timescale 1ns / 1ps

module DFlipFlop(
input clk, d,
output reg q);

wire q1, q0;

DLatch(~clk, d, q1);
DLatch(clk, q1, q0);

always @(q0) begin


q = q0;
end

endmodule

`timescale 1ns / 1ps

module DLatch(
input e, d,
output reg q);

always @(e, d) begin


if (e == 1)
q = d;
end

endmodule

`timescale 1ns / 1ps

module AND_2x1( input A, B,


output reg S);

always @(A, B) begin


S = A & B;
end

endmodule

`timescale 1ns / 1ps

module AND_3x1( input A, B, C,


output reg S);

always @(A, B, C) begin


S = A & B & C;
end

endmodule
`timescale 1ns / 1ps

module NOR_2x1( input A, B,


output reg S);

always @(A, B) begin


S = ~(A | B);
end

endmodule

`timescale 1ns / 1ps

module OR_2x1( input A, B,


output reg S);
always @(A, B) begin
S = A | B;
end

endmodule

`timescale 1ns / 1ps

module OR_3x1( input A, B, C,


output reg S);
always @(A, B, C) begin
S = A | B | C;
end

endmodule

`timescale 1ns / 1ps

module OR_4x1( input A, B, C, D,


output reg S);
always @(A, B, C, D) begin
S = A | B | C | D;
end

endmodule

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