REx: reset code(4.

5)

`timescale 1ns/10 ps module reg_reset_testbench; localparam T=10, D=4*T;

reg clk,reset, d; wire q; reg_reset uut(clk, reset, d, q); initial
begin clk=1'b1; reset=1'b1; #(T/2); end always #(T/2)
clk=~clk;
initial begin
$dumpfile ("reg_reset.vcd"); $dumpvars; d=1'b1;
#D; d=1'b0;
#D; d=1'b1;
#D; d=1'b1;
#D; d=1'b0;
#D; d=1'b1;
#D; d=1'b1; #D; d=1'b0;
#D; $finish; end endmodule
Module:
`timescale 1ns/10 ps module reg_reset
(
input wire clk, reset, input wire [7:0] d, output reg [7:0] q
);
always@(posedge clk, posedge reset)
if(reset) q<=0; else q<=d; endmodule

REG FILE CODE: ARRAY+ ADDR(4.6)

`timescale 1 ns/10 ps
module reg_file
#
(
parameter B = 8,
W = 2
)
(
input wire clk,
input wire wr_en,
input wire [W-1:0] w_addr , r_addr ,
input wire [B-1:0] w_data,
output wire [B-1:0] r_data
);

reg [B-1:0] array_reg [2**W-1:0] ;

always @(posedge clk)
if (wr_en)
array_reg [w_addr] <= w_data;

assign r_data = array_reg [r_addr] ;

endmodule

`timescale 1 ns/10 ps
module reg_file_testbench;
localparam T=10,
D=4*T;
reg clk, en;
reg [1:0] wr_adress, re_adress;
reg [7:0] wr_data;
wire [7:0] re_data;

reg_file uut (clk, en, wr_adress, re_adress, wr_data, re_data);

 initial
begin
clk = 1'b1;
wr_adress = 2'b10;
re_adress = 2'b10;
end
always #(T/2)
clk = ~clk;
initial
begin
$dumpfile("reg_file_testbench.vcd");
$dumpvars;
en = 1'b0; wr_data = 8'b01101101;
#D;
en = 1'b1; wr_data = 8'b11001001;
#D;
en = 1'b0; wr_data = 8'b11100110;
#D;
en = 1'b1; wr_data = 8'b01001001;
#D;
en = 1'b0; wr_data=8'b11101100;
#D;
$finish;
end
endmodule

FREE RUN REG (4.7)

`timescale 1 ns/10 ps
module free_run_shift_reg
#(parameter N=8)
(
input wire clk, reset,
input wire s_in,
output wire s_out
);
//signal declaration
reg [N-1:0] r_reg;
wire [N-1 : 0] r_next ;
// body
// register
always @(posedge clk, posedge reset)
if (reset)
r_reg <= 0;
else
r_reg <= r_next;
// next-state logic
assign r_next = {s_in , r_reg [N-1: 1] };
// olrtput logic
assign s_out = r_reg[0];

endmodule

`timescale 1 ns/10 ps
module free_run_shift_reg_testbench;
localparam T=10,
D=4*T;

reg clock, res;

reg test_in;
 wire test_out;

free_run_shift_reg uut (clock, res, test_in, test_out);

initial
begin
clock = 1'b1;
res = 1'b1;
#(T/2);
res = 1'b0;
end

always #(T/2)
clock = ~clock;

initial
begin
$dumpfile("free_run_shift_reg_testbench.vcd");
$dumpvars;

test_in = 8'b1;
#D;
test_in = 8'b0;
#D;
$finish;
end
endmodule

Ex:Create a Verilog module for 8-bit universal shift register. Write a testbench
code with the input 00110001. Apply different control signals and observe the
outputs.

Code:

`timescale 1 ns/10 ps module univ_shift_reg_testbench; localparam T=10,

D=4*T; reg clock, res; reg [1:0] control; reg [7:0] in;
wire[7:0] out;

univ_shift_reg uut (clock, res, control, in, out); initial begin

clock = 1'b1; res = 1'b1;
#(T/2);
res = 1'b0;
end
always #(T/2) clock = ~clock;
initial begin
$dumpfile("univ_shift_reg_testbench.vcd");
$dumpvars;
in = 8'b00110001; control = 2'b00;
#D;
control = 2'b01;
#D;
control = 2'b10;
#D;

control = 2'b11;
 #D; $finish; end
endmodule

Module:
`timescale 1 ns/10 ps module univ_shift_reg
#(parameter N=8)
(
input wire clk, reset, input wire [1:0] ctrl, input wire [N-1:0] d, output
wire [N-1:0] q
) ;

reg [N-1:0] r_reg, r_next;

always @(posedge clk, posedge reset) if (reset) r_reg <= 0; else r_reg <= r_next;

always @*
case (ctrl)
2'b00: r_next = r_reg;
2'b01: r_next = {r_reg[N-2:0], d[0]}; 2'b10: r_next = {d[N-1], r_reg[N-1:1]};
default: r_next = d; endcase
assign q = r_reg; endmodule

lab 5:
d flip flop.
TESTBENCH
`timescale 1ns/10 ps module d_ff_testbench; localparam T=10, D=4*T;
reg clk, d; wire q; d_ff uut(clk, d, q); initial begin
clk=1'b1; #(T/2); end always #(T/2) clk=~clk;
initial begin
$dumpfile ("d_ff.vcd"); $dumpvars; d=1'b1;
#D; d=1'b0;
#D; d=1'b1;
#D; d=1'b1;
#D; d=1'b0;
#D; d=1'b1;
#D; d=1'b1;
#D; d=1'b0;
#D; $finish; end endmodule
MODULE:
`timescale 1ns/10 ps module d_ff
(
input wire clk, input wire d, output reg q
);
always @(posedge clk) q<=d;
endmodule

d ff reset: code
`timescale 1ns/10 ps module d_ff_reset_testbench; localparam T=10, D=4*T;
reg clk,reset, d; wire q; d_ff_reset uut(clk,reset, d, q); initial
begin clk=1'b1; reset=1'b1; #(T/2); reset=1'b0;
end always #(T/2) clk=~clk;
initial begin
$dumpfile ("d_ff.vcd"); $dumpvars; d=1'b1;
#D; d=1'b0;
#D; d=1'b1;
#D; d=1'b1;
#D; d=1'b0;
 #D; d=1'b1;
#D; d=1'b1; #D; d=1'b0;
#D;
$finish;
end
end module
MODULE:
timescale 1ns/10 ps
module d_ff_reset
( input wire clk,reset,input wire d,output reg q);
always @(posedge clk,posedge reset)
if(reset)
q<=1'b0;
else
q<=d;
endmodule

1 SEGMENT
MODULE
`timescale 1ns/10 ps
module d_ff_en_1seg
(
input wire clk, reset,
input wire en,
input wire d,
output reg q
);

always @(posedge clk, posedge reset)

if(reset)
q<=1'b0;
else if(en)
q<=d;

endmodule

`timescale 1ns/10 ps
module d_ff_en_1seg_testbench;
localparam T=10,
D=4*T;

reg clk,reset,en, d;
wire q;
d_ff_en_1seg uut(clk,reset,en, d, q);
initial
begin
clk=1'b1;
reset=1'b1;
#(T/2);
reset=1'b0;
end
always #(T/2) clk=~clk;
initial
begin
$dumpfile ("d_ff.vcd"); $dumpvars;
en=1'b0; d=1'b1;
#D; en=1'b0; d=1'b0;
#D; en=1'b1; d=1'b1;
 #D; en=1'b1; d=1'b1;
#D; en=1'b1; d=1'b0;
#D; en=1'b1; d=1'b1;
#D; en=1'b0; d=1'b1;
#D; en=1'b1; d=1'b0;
#D;
$finish;
end
endmodule

2 SEGEMENT
`timescale 1ns/10 ps
module d_ff_en_2seg
(
input wire clk, reset,
input wire en,
input wire d,
output reg q
);
reg r_reg, r_next;

always @(posedge clk, posedge reset)

if(reset)
r_reg<=1'b0;
else
r_reg <= r_next;

always@
if(en)
r_next=d;
else
r_next=r_reg;

always@
q=r_reg;

endmodule

`timescale 1ns/10 ps
module d_ff_en_2seg_testbench;
localparam T=10,
D=4*T;

reg clk,reset,en, d;
wire r_reg, r_next, q;
d_ff_en_2seg uut(clk,reset,en, d, q);
initial
begin
clk=1'b1;
reset=1'b1;
#(T/2);
reset=1'b0;
end
always #(T/2) clk=~clk;
initial
begin
$dumpfile ("d_ff.vcd"); $dumpvars;
en=1'b0; d=1'b1;
#D; en=1'b0; d=1'b0;
 #D; en=1'b1; d=1'b1;
#D; en=1'b1; d=1'b1;
#D; en=1'b1; d=1'b0;
#D; en=1'b1; d=1'b1;
#D; en=1'b0; d=1'b1;
#D; en=1'b1; d=1'b0;
#D;
$finish;
end
endmodule

Exercise:
Amend duty-cycle of the clock (25% or 75%) in the sample testbench code. Run the
listing 4.3 with the amended testbench code and observe the outputs.

For 25% DUTY CYCLE:

`timescale 1ns/10 ps module d_ff_en_1seg_testbench; localparam T=10, D=4*T;

reg clk,reset,en, d; wire q; d_ff_en_1seg uut(clk,reset,en, d, q);
initial begin clk=1'b1; reset=1'b1; #(T/4);
reset=1'b0; end always #(T/4) clk=~clk;
initial begin
$dumpfile ("d_ff.vcd"); $dumpvars; en=1'b0; d=1'b1;
#D; en=1'b0; d=1'b0;
#D; en=1'b1; d=1'b1;
#D; en=1'b1; d=1'b1;

#D; en=1'b1; d=1'b0;

#D; en=1'b1; d=1'b1;
#D; en=1'b0; d=1'b1; #D; en=1'b1; d=1'b0;
#D; $finish; end endmodule
MODULE:

`timescale 1ns/10 ps module d_ff_en_1seg

(
input wire clk, reset, input wire en, input wire d, output reg q
);
always @(posedge clk, posedge reset)
if(reset) q<=1'b0; else if(en) q<=d;
endmodule

For 75% DUTY CYCLE:

`timescale 1ns/10 ps module d_ff_en_1seg_testbench; localparam T=10, D=4*T;

reg clk,reset,en, d; wire q; d_ff_en_1seg uut(clk,reset,en, d, q);
initial begin clk=1'b1; reset=1'b1; #(3*T/4);
reset=1'b0; end always #(3*T/4) clk=~clk;
initial begin
$dumpfile ("d_ff.vcd"); $dumpvars;
en=1'b0; d=1'b1;
#D; en=1'b0; d=1'b0;
#D; en=1'b1; d=1'b1;
#D; en=1'b1; d=1'b1;
#D; en=1'b1; d=1'b0;
#D; en=1'b1; d=1'b1;
#D; en=1'b0; d=1'b1; #D; en=1'b1; d=1'b0;
#D; $finish; end endmodule
MODULE:

`timescale 1ns/10 ps module d_ff_en_1seg

(
input wire clk, reset, input wire en, input wire d, output reg q
);
always @(posedge clk, posedge reset)
if(reset) q<=1'b0; else if(en)

LAB 4:
ADDR CARRY HARD
`timescale 1ns/10 ps
module adder_carry_hard_lit
(
input wire [3:0] a,b, output wire [3:0] sum,
output wire cout
);
wire [4:0] sum_ext;

assign sum_ext = {1'b0, a} + {1'b0, b};

assign sum = sum_ext [3:0]; assign cout = sum_ext[4];
endmodule

`timescale 1ns/ 10 ps
module adder_carry_hard_lit_testbench; reg [3:0] a, b; wire [3:0] sum; wire
cout;
adder_carry_hard_lit uff(a, b, sum, cout);
initial begin
$dumpfile("adder_carry_hard_lit_testbench.vcd"); $dumpvars;

a = 4'b0001; b =4'b1001;
#20;
$display("the sum of a and b = %b", sum);
$display("the carry = %b", cout);

$finish; end
endmodule

2. A parameter is declared with a constant value inside a module. Is it possible

to modify the default value when the module is instantiated? Please explain with a
programming example.
module MyModule #(parameter PARAM_VALUE = 4) ( input wire clk, input wire rst,
output wire [3:0] out
);
// Use PARAM_VALUE in the module logic
always @(posedge clk or posedge rst) begin if (rst) begin out <=
4'b0000;
end else begin out <= PARAM_VALUE;
end
end endmodule module TestModule (
input wire clk, input wire rst, output wire [3:0] out
);
MyModule #(8) my_inst (
.clk(clk),
.rst(rst),
.out(out)
);
endmodule

LAB 3 : MUX 2x1 MUX: Two single-bit inputs with one selectivity switch.
`timescale 1ns/ 10ps module m21
(
input wire d0, d1, s, output reg y
);

always @*
if (s==0) y = d0; else if (s==1)
y = d1;

endmodule

`timescale 1ns/ 10ps

module m21_testbench;
reg test_d0, test_d1, test_s; wire test_y;

m21 uut
( .d0(test_d0), .d1(test_d1), .s(test_s), .y(test_y));

initial begin test_d0 = 1; test_d1 = 1; test_s = 0;

# 20
$display ("the output of mux 2to1 when d0=1, d1=1 and the sel= 0 is %d",
test_y); test_d0 = 1; test_d1 = 0; test_s = 1;
# 20
$display ("the output of mux 2to1 when d0=1, d1=0 and the sel= 1 is %d",
test_y);

$finish; end
endmodule

2. 4-bit wide 4x1 MUX: Four inputs (4-bits wide each) with two selectivity
switches.

`timescale 1ns/ 10ps module m41

(
input wire [3:0] d0, d1, d2, d3, s0, s1, output reg [3:0] y
);

always @*
if (s0==0 && s1==0)
y = d0;
else if (s0==0 && s1==1) y = d1;
else if (s0==1 && s1==0) y = d2;
else if (s0==1 && s1==1) y = d3 ;

endmodule

`timescale 1ns/ 10ps module m41_testbench;

reg [3:0] test_d0, test_d1, test_d2, test_d3, test_s0, test_s1; wire [3:0]
test_y; m41 uut

( .d0(test_d0), .d1(test_d1), .d2(test_d2), .d3(test_d3), .s0(test_s0), .s1(test_s1

),
.y(test_y)); initial begin test_d0 = 4'b0000; test_d1 = 4'b0001;
test_d2 = 4'b0010; test_d3 = 4'b0011; test_s0 = 4'b0000; test_s1
= 4'b0000; # 20;
$display ("the output of mux 4to1 when sel0= 0, sel1=0 is %b", test_y);
test_d0 = 4'b0000; test_d1 = 4'b0001; test_d2 = 4'b0010; test_d3
= 4'b0011; test_s0 = 4'b0000;
test_s1 = 4'b0001; # 20;
$display ("the output of mux 4to1 when sel0= 1,sel1=0 is %b", test_y);

$finish; end
endmodule

To explain the working of the four shift operators in Verilog HDL (Hardware
Description Language), let's create a simple Verilog design that demonstrates the
behavior of these operators using two bits for shifting. We will use the four shift
operators: left shift (<<), right shift (>>), logical right shift (>>>), and
arithmetic right shift (>>>) to manipulate a 4-bit binary number.
module shift_operations_tb;

// Inputs reg [3:0] data_in;

// Outputs wire [3:0] left_shift_result; wire [3:0] right_shift_result;

wire [3:0] logical_left_shift_result; wire [3:0] logical_right_shift_result;

// Instantiate the shift modules left_shift ls

(.data_in(data_in), .result(left_shift_result)); right_shift rs
(.data_in(data_in), .result(right_shift_result)); logical_left_shift lls
(.data_in(data_in), .result(logical_left_shift_result)); logical_right_shift lrs
(.data_in(data_in), .result(logical_right_shift_result)); initial begin

$dumpfile("dump.vcd");
$dumpvars;

data_in = 4'b1100; // Input data: 1100

#10;
data_in = 4'b0011; // Input data: 0011
#10;
// Add more test cases if needed
$finish;
end

endmodule

module left_shift( input [3:0] data_in, output reg [3:0] result

);

always @(*) begin result = data_in << 2;

end endmodule
module right_shift( input [3:0] data_in, output reg [3:0] result
);

always @(*) begin

result = data_in >> 2; end
endmodule
module logical_left_shift( input [3:0] data_in, output reg [3:0] result
);

always @(*) begin

result = data_in <<< 2; end

endmodule
module logical_right_shift( input [3:0] data_in, output reg [3:0] result
);

always @(*) begin

result = data_in >>> 2; end

endmodule

. Make a 2-bits max comparator HDL design using �?� operator. You may take three 2-
bit inputs (a, b, c), and a 2-bit output should be a max number of all the three
inputs.
Note: You also need to write a testbench code for the above exercises. Please
provide your explanation with supporting waveforms obtained from your design.

module max_comparator_tb;

// Inputs reg [1:0] a; reg [1:0] b;

reg [1:0] c;

// Outputs
wire [1:0] max_result;

// Instantiate the max comparator module max_comparator uut (

.a(a),
.b(b),
.c(c),
.max_result(max_result)
);
// Stimulus generation
initial begin
$dumpfile("dump.vcd");
$dumpvars;

// Test case 1: a > b > c a = 2'b11; b = 2'b10; c = 2'b01;

#10;

// Test case 2: c > a > b a = 2'b01; b = 2'b00; c = 2'b11;

#10;

// Test case 3: b > c > a a = 2'b00; b = 2'b11; c = 2'b10;

#10;

$finish;
end

endmodule
module max_comparator(
input [1:0] a, input [1:0] b, input [1:0] c,
output [1:0] max_result
);

assign max_result = (a > b) ? ((a > c) ? a : c) : ((b > c) ? b : c);

endmodule
LAB 1 FULL ADDER:
TEST BENCH CODE:
module tb_full_adder;

reg a, b, c_in; wire sum, c_out;

full_adder dut (
.a(a),
.b(b),
.c_in(c_in),
.sum(sum),
.c_out(c_out)
);

initial begin
$dumpfile("dump.vcd");

$dumpvars(0, tb_full_adder);

$display("a b c_in | sum c_out");

$monitor("%b %b %b | %b %b", a, b, c_in, sum, c_out);

// Test case 1 a = 1'b0; b = 1'b0; c_in = 1'b1;

#10;

// Test case 2 a = 1'b1; b = 1'b1; c_in = 1'b0;

#10;

// Test case 3 a = 1'b1; b = 1'b0; c_in = 1'b1;

#10;

// Test case 4 a = 1'b1; b = 1'b1; c_in = 1'b1;

#10;

$finish; end

endmodule
MODULE DESIGN CODE:
module full_adder ( input a, input b, input c_in, output sum,
output c_out
);
assign sum = a ^ b ^ c_in; assign c_out = (a & b) | (b & c_in) | (a &
c_in); endmodule