combinational Logic Circuits 2.59 dynamic inverter starts to conduct when the input signal exceeds the threshold voltage (Vp of the NMOS pull-down transistor, Therefore, it is reasonable to set the switching threshold (V,,) a8 well as V,,,and V,, of the gate equal to V,,, This translates to a low value for the NM, . 2.17.2 Domino Logic Domino logic is a CMOS-based evolution of the dynamic logic techniques based oneitherPMOS or NMOS transistors. It allows a rail-to-rail logic swing, It was developed to speed up circuits. . Logic Features ¥ — Theyhave smaller areas than conventional CMOS logic (as does all Dynamic Logic). ¥ Parasitic capacitances are smaller so that higher operating speeds are possible. Y — Operation is free of glitches as each gate can make only one transition. v Only non-inverting structures are possible because of the presence of inverting buffer. ¥ — Charge distribution may bea problem. Hit Static Inverter 4— PON — PON with level Restorer Figure 2.53 The block of Domino logic rcON Vl 2.60 LSI and Ch; hip esi 2.17.3 Dual-Rail Domino Logic i -rail ino gates acc, Itencodes each Signal with a pair of wires. Dual-rail domino g ©Pt bot, itary out and. complementary Inputs and compute both true and complement ‘ary Outputs Dy, d ; Maj ‘ i ng and noniny, Sminois complete ogc fanilin that itcan computa ‘averting and nonin logic fa etn F + « nctions. However, itrequires morearea, wiring, and Power Dual-rail doming Si Tot only the result ofa computation butalso indicates when the com; al putation ig Aone Before Computation Completes, both rails are precharged. When the SOMPUtaton completes, one. Tail will be asserted, Yh =AxorB| EE eee reer eee inational Lo i combina gic Circuits 261 Keepers aan ven the delay and noise margin problems, If a dynamic node is prosharged igh and left floating, then the Voltage of dynamic node will drift over time guoto gate, subthreshold junction leakages It avoids charge sharing. a Week keeper dik x H a 2 2 Figure 2.55 Conventional Keeper 2.17.4 Multiple output Domino Logic (MODL) Hwang and Fisher formally introduced MODL in 1989, and it has been shown to provide considerable hardware savings. In domino CMOS logic, as well as other non complementary MOS logic styles, there is only one output available from a given logic gate. However, itis a fact that multiple functions are often implemented in the logic tree with one beinga sub-function of another. Therefore, if one or more of these sub-functions areneeded as separate output signals, they have to be implemented in several additional gates, resulting in a replication of circuitry. Basically speaking, the main concept behind MODL is the utilization of sub-functions available in the logic tree of domino gates, thus saving replication of circuitry. The additional ouputs are obtained by adding precharge devices and static inverters at the corresponding intermediate nodes of the logic tree. It is apparently area-efficient if we build the several outputs on only one tree; also it will not affect the speed of implementing all the functions. Figure below the block of MODL for the following functions:@=B(C+D) QI=A.B(C#D) Qi FABKCpy a = (C+D) Figure 2.56 Block diagram of MODL 2.17.5 NP Domino Logic ‘The Hl-skew inverting static gates ae replaced wih predischarged dynamic gates using pMOS logic. The design styles called NP Domino or NORA Domino (NO RAce) NORA has two major drawbacks. The logical effort of footed p-logic gates is gener-ally worse than that of HI-skew gates, Secondly, NORA is extremely susceptible to noise.combinational Logic Circuits 264 4 4 3 tne | toxic nelogic ad Bq Dating f t . ike] | La | Other p Blocks J, Othern Blocks (a) (b) Other m Blocks Other p Blacks A A ap at te Inputs logic ; stble—} [ f mlogic During f t cik=1 | ' 1 Other p Blocks J Mthern Blocks (©) Figure 2.57 NP Domino 2.17.6 Speed and Power Dissipation of Dynamic Logic The main advantages of dynamic logic are v v v Increased speed Reduced implementation area. Less number of transistors to implement a given logic function implies that the overall load capacitance is much smaller. After the precharge phase, the output is high. For alow input signal, no additional switching occurs. Asa result, t, 0! ‘The high-to-low transition, on the other hand, requires the discharging of the output capacitance through the pull-down network. Therefore twis proportional to C, and the current-sinking capabilities of the pull-down network,VLSI and Chip Design 2.64 ii ewhat, as it presents The presence of the evaluation transistor slows the gate som: F . i i in static power an extra series resistance. Omitting this transistormay result pe dissipation and potentially a performance loss. Y The precharge time is determined by the time it takes to charge CL through the PMOS precharge transistor. During this time, the logic in the gate cannot be utilized, However, very often, the overall digital system can be designed in such a way that the precharge time coincides with other system functions, ” — The precharge of the arithmetic unit ina microprocessor can coincide with the instruction decode, ~ — The designer has to be aware of this “dead zone” in the use of dynamic logic, and should carefully consider the Pros and cons of its usage, taking the overall system requirements into account, 2.18 PASS TRANSISTOR LOGIC Pass transistor logic is a popular and widely used alternative of complementary CMOS. It reduces the number of transi Primary inputs to drive gate terminals ors required to implement logic by allowing the 5 Well as source/drain terminals, The above diagram shows the implementation ofan AND function using NMOS transisitors only, Here, if input Bis high, The {op transistor is tuned on and copies the innnr A 0 the output F. When B is low, the bottam ann +. p ino