Digital IC Design

Lec 4-3:
Combinational Circuits –– Dynamic Logic
黃柏蒼 Po-Tsang (Bug) Huang
bughuang@nycu.edu.tw

International College of Semiconductor Technology

National Chiao Tung Yang Ming University
Dynamic and Static CMOS
n In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
u fan-in of n requires 2n (n N-type + n P-type) devices

n Dynamic circuits rely on the temporary storage

of signal values on the capacitance of high
impedance nodes.
u requires on n + 2 (n+1 N-type + 1 P-type) transistors
u takes a sequence of precharge and conditional
evaluation phases to realize logic functions

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Dynamic Gate

off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)

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Problems of Dynamic Logic
n Cascading dynamic logic
u Domino logic
Ø Non-inverting logic
n Signal integrity problems
u Charge leakage
Ø Add keeper
u Charge sharing
Ø Precharge internal node
u Capacitive coupling
u Clock feedthrough

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Cascade Dynamic Gates: Monotonicity
n Dynamic gates require monotonically rising
inputs during evaluation
u 0 -> 0 f
u 0 -> 1 A
u 1 -> 1
u But not 1 -> 0 violates monotonicity
during evaluation
A

f Precharge Evaluate Precharge

Output should rise but does not

Only 0 ® 1 transitions allowed at inputs!

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 Monotonicity Problem
n But dynamic gates produce monotonically
falling outputs during evaluation
n Illegal for one dynamic gate to drive another!

A=1

f f Precharge Evaluate Precharge

Y
X
A
X
X monotonically falls during evaluation
Y
Y should rise but cannot

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Conditions on Output
n Once the output of a dynamic gate is
discharged, it cannot be charged again until the
next precharge operation.
u Inputs to the gate can make at most one transition
during evaluation.
u This could be a problem when you cascade the
dynamic logic
Ø Extra transition will destroy the logic

n Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL
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np-CMOS (Zipper)

CLK Mp CLK Me
1®1
Out1
1®0
In1 In4 PUN
In2 PDN In5
0®0
In3 Out2
0®1
(to PDN)
CLK Me CLK Mp

to other to other
PDN’s PUN’s

Only 0 ® 1 transitions allowed at inputs of PDN

Only 1 ® 0 transitions allowed at inputs of PUN
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np-CMOS Adder Circuit

CLK CLK 1®x

0®x Sum1
A1 B1 B1 C1
1®x A1
A1 A1 B1 C1
0 ® xC2
B1
CLK
CLK

CLK
CLK 1 ® x C1 B0
0®x
A0 A0 B0 C0 A0
A0 B0 B0 1®x C0
Sum0
C0 0®x
CLK CLK

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Solution: Domino Logic

Clk Mp Clk Mp Mkp

1®1
Out1 Out2
1®0
0®0
In1 0®1
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

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Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

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Properties of Domino Logic
n Only non-inverting logic can be implemented
for dymaic circuits, fixes include
u can reorganize the logic using Boolean
transformations
u use differential logic (dual rail)
u use np-CMOS (zipper)
n Very high speed
u tpHL = 0
u static inverter can be optimized to match fan-out
(separation of fan-in and fan-out capacitances)

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Domino Gates
n Follow dynamic stage with inverting static gate
u Dynamic / static pair is called domino gate
u Produces monotonic outputs

f Precharge Evaluate Precharge

domino AND
W

W X Y Z X
A
Y
B C
f
Z

dynamic static
f f
NAND inverter f f
A W X A X
H Y =
B H Z B Z
C C

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 Domino Optimizations
n Each domino gate triggers next one, like a
string of dominos toppling over
n Gates evaluate sequentially but precharge in
parallel
n Thus evaluation is more critical than precharge
n HI-skewed static stages can perform logic
f

S0 S1 S2 S3
D0 D1 D2 D3
Y
H
f

S4 S5 S6 S7
D4 D5 D6 D7
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Domino Zero Detector
n Large Fan-in circuits

In7 In6 In5 In4 In3 In2 In1 In0

not zero

CLK

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Domino Comparator

A3 A2 A1 A0
CLK

Out

B3 B2 B1 B0

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Properties of Domino Logic
n Only non-inverting logic can be implemented,
fixes include
u can reorganize the logic using Boolean
transformations
u use differential logic (dual rail)
u use np-CMOS (zipper)

n Very high speed

u tpHL = 0
u static inverter can be optimized to match fan-out
(separation of fan-in and fan-out capacitances)

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Dual-Rail Domino
n Domino only performs noninverting functions:
u AND, OR but not NAND, NOR, or XOR
n Dual-rail domino solves this problem
u Takes true and complementary inputs
u Produces true and complementary outputs

sig_h sig_l Meaning

Y_l Y_h
0 0 Precharged f
inputs
0 1 ‘0’ f f

1 0 ‘1’ f

1 1 invalid

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 Example: AND/NAND
n Given A_h, A_l, B_h, B_l
n Compute Y_h = AB, Y_l = AB
n Pulldown networks are conduction
complements

Y_l f Y_h
= A*B A_h = A*B
A_l B_l B_h

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Example: XOR/XNOR
n Sometimes possible to share transistors

Y_l f Y_h
= A xnor B A_h A_l A_l A_h = A xor B
B_l B_h

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 Differential (Dual Rail) Domino

off on
CLK Mp Mkp Mkp Mp CLK

Out = AB 1 0 1 0 !Out = !(AB)

A
!A !B
B

CLK Me

Due to its high-performance, differential domino is

very popular and is used in several commercial
microprocessors!
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Other Domino Variations
n Multiple output domino logic – exploits the fact that
certain outputs are subsets of other outputs to
generate a number of logic functions in a single gate.
n Compound domino
CLK Mp CLK Mp Mp

A D

B E G

C F H

CLK Me CLK Me Me

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 Domino Summary
n Domino logic is attractive for high-speed
circuits
u 1.3 – 2x faster than static CMOS
u But many challenges:
Ø Monotonicity, leakage, charge sharing, noise
n Widely used in high-performance
microprocessors in 1990s when speed was king
n Largely displaced by static CMOS now that
power is the limiter
n Still used in memories for area efficiency

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Impact of Charge Leakage
n Output settles to an intermediate voltage determined
by a resistive divider of the pull-up and pull-down
networks
u Once the output drops below the switching threshold of the
fan-out logic gate, the output is interpreted as a low voltage.
CLK
4
CLK Mp
3

Out
1

A=0 CL
2
VOut Evaluate
CLK Me
Precharge

Leakage sources

Minimum clock rate!!! 24

A Solution to Charge Leakage
q Keeper compensates for the charge lost
due to the pull-down leakage paths.
Keeper

CLK Mp Mkp

!Out
A
CL
B

Must be weak enough not to fight

CLK Me
evaluation

Same approach as level restorer for pass

transistor logic
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Charge Sharing
n Dynamic gates suffer from charge sharing

f
f
Y A
A x CY
Y
B=0 Cx Charge sharing noise

CY
Vx = VY = VDD
C x + CY

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Malfunction of Charge sharing

Charge stored originally on

CLK Mp
Out CL is redistributed (shared)
A over CL and CA leading to
CL
static power consumption by
B=0 Ca downstream gates and
possible circuit malfunction.
CLK Me Cb

When DVout = - VDD (Ca / (Ca + CL )) the drop in Vout is

large enough to be below the switching threshold of
the gate it drives causing a malfunction.

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Solution to Charge Redistribution
n Solution: add secondary precharge transistors
u Typically need to precharge every other node
n Big load capacitance CY helps as well

secondary
f precharge
Y transistor
A x
B
Precharge internal nodes using a
clock-driven transistor (at the cost
of increased area and power)
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Backgate Coupling
n Susceptible to crosstalk due to 1) high impedance of
the output node and 2) backgate capacitive coupling
u Out2 capacitively couples with Out1 through the gate-source
and gate-drain capacitances of M4

CLK Mp M6 M5
Out1 =1
Out2 =0
A=0 M1 M4
CL1 CL2

B=0 M2 M3 In

CLK Me

Dynamic NAND Static NAND

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Backgate Coupling Effect
n Capacitive coupling means Out1 drops
significantly so Out2 doesn’t go all the way to
ground
3

2
Out1
Voltage

1 CLK

0 In Out2

-1
0 2 4 6
Time 30
Clock Feedthrough
n A special case of backgate capacitive coupling
between the clock input of the precharge
transistor and the dynamic output node

CLK Coupling between Out and

Mp
Out CLK input of the precharge
A CL
device due to the gate-
drain capacitance. So
B voltage of Out can rise
above VDD. The fast rising
CLK Me
(and falling edges) of the
clock couple to Out.

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Clock Feedthrough

CLK Clock feedthrough

Out
In1 2.5

In2
1.5
In3
Voltage

Out
In4 0.5 In &
CLK
CLK
-0.5
0 0.5 1
Time, ns
Clock feedthrough

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Power Consumption of Dynamic Gate

CLK Mp
Out
In1 CL
In2 PDN
In3

CLK Me

Power only dissipated when previous Out = 0

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Dynamic Power Consumption is Data Dependent

Dynamic 2-input NOR Gate

Assume signal probabilities
A B Out
PA=1 = 1/2
0 0 1 PB=1 = 1/2
0 1 0

1 0 0
Then transition probability
P0®1 = Pout=0 x Pout=1
1 1 0

= 3/4 x 1 = 3/4

Switching activity can be higher in dynamic gates!

P0®1 = Pout=0

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Power
n Domino gates have high activity factors
u Output evaluates and precharges
Ø If output probability = 0.5, a = 0.5
• Output rises and falls on half the cycles
u Clocked transistors have a = 1
n Leads to very high power consumption

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Noise Sensitivity
n Dynamic gates are very sensitive to noise
u Inputs: VIH » Vtn
u Outputs: floating output susceptible noise
n Noise sources
u Capacitive crosstalk
u Charge sharing
u Power supply noise
u Feedthrough noise
u And more!

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 Properties of Dynamic Gates
n Logic function is implemented by the PDN only
u number of transistors is N + 2 (versus 2N for static
complementary CMOS)
n Full swing outputs (VOL = GND and VOH = VDD)
n Non-ratioed - sizing of the devices does not affect
the logic levels
n Faster switching speeds
u reduced load capacitance due to lower input capacitance (Cin)
u reduced load capacitance due to smaller output loading (Cout)
u no Isc, so all the current provided by PDN goes into discharging CL
u Ignoring the influence of precharge time on the switching speed
of the gate, tpLH = 0 but the presence of the evaluation transistor
slows down the tpHL
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 Properties of Dynamic Gates
n Power dissipation should be better
u consumes only dynamic power – no short circuit power
consumption since the pull-up path is not on when evaluating
u lower CL- both Cint (since there are fewer transistors connected to
the drain output) and Cext (since there the output load is one per
connected gate, not two)
u by construction can have at most one transition per cycle – no
glitching
n But power dissipation can be significantly higher due to
u higher transition probabilities
u extra load on CLK
n PDN starts to work as soon as the input signals exceed
VTn, so set VM, VIH and VIL all equal to VTn
u low noise margin (NML)
n Needs a precharge clock 38
How to Choose a Logic Style
n Depends on your area, speed, power and ease of
design
n Static CMOS is the most robust to noise
u Best general purpose logic style
u Complementary CMOS with large fan-in and complex gates
Ø high area cost, and lower performance
Ø Pseudo NMOS
Ø Pass-transistors for MUX and adders
n Dynamic logic is the fastest
u Noise sensitive
u A lot of design problems
u Lower bound on freq. due to charge leakage

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How to Choose a Logic Style
n Must consider ease of design, robustness
(noise immunity), area, speed, power, system
clocking requirements, fan-out, functionality,
ease of testing
q Current trend is towards an increased use of complementary
static CMOS: design support through DA tools, robust, more
amenable to voltage scaling.

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