UNIT-3/LECTURE-5

Relative Address Mode

 In this mode the content of the program counter is added to the address part of the
instruction in order to obtain the effective address.

 The address part of the instruction is usually a signed number (in 2' s complement
representation) which can be either positive or negative. When this number is added
to the content of the program counter, the result produces an effective address whose
position in memory is relative to the address of the next instruction.

 To clarify with an example, assume that the program counter contains the number
825 and the address part of the instruction contains the number 24.

 The instruction at location 825 is read from memory during the fetch phase and the
program counter is then incremented by one to 826. The effective address
computation for the relative address mode is 826 + 24 = 850.

 This is 24 memory locations forward from the address of the next instruction.
Relative addressing is often used with branch-type instructions when the branch
address is in the area surrounding the instruction word itself.

 It results in a shorter address field in the instruction format since the relative address
can be specified with a smaller number of bits compared to the number of bits
required to designate the entire memory address.

Indexed Addressing Mode

 In this mode the content of an index register is added to the address part of the
instruction to obtain the effective address.

 The index register is a special CPU register that contains an index value.

 The address field of the instruction defines the beginning address of a data array in
memory.

 Each operand in the array is stored in memory relative to the beginning address.
The distance between the beginning address and the address of the operand is the
 index value stored in the index register.

 Any operand in the array can be accessed with the same instruction provided that
the index register contains the correct index value.

 The index register can be incremented to facilitate access to consecutive operands.

 Some computers dedicate one CPU register to function solely as an index register.

 This register is involved implicitly when the index-mode instruction is used.

 In computers with many processor registers, any one of the CPU registers can
contain the index number.

 In such a case the register must be specified explicitly in a register field within the
instruction format.

Base Register Addressing Mode

 In this mode the content of a base register is added to the address part of the
instruction to obtain the effective address.

 This is similar to the indexed addressing mode except that the register is now called
a base register instead of an index register.

 The difference between the two modes is in the way they are used rather than in the
way that they are computed. An index register is assumed to hold an index number
that is relative to the address part of the instruction.

 A base register is assumed to hold a base address and the address field of the
instruction gives a displacement relative to this base address. The base register
addressing mode is used in computers to facilitate the relocation of programs in
memory.

 When programs and data are moved from one segment of memory to another, as
required in multiprogramming systems, the address values of instructions must reflect
this change of position.

 With a base register, the displacement values of instructions do not have to change.
Only the value of the base register requires updating to reflect the beginning of a new
 memory segment.

Numerical Example

 To show the differences between the various modes, we will show the effect of the
addressing modes on the instruction defined in Fig. 7.

 The two-word instruction at address 200 and 201 is a "load to AC" instruction with
an address field equal to 500.

 The first word of the instruction specifies the operation code and mode, and the
second word specifies the address part.

 PC has the value 200 for fetching this instruction. The content of processor register
R1 is 400, and the content of an index register XR is 100.

 AC receives the operand after the instruction is executed. The figure lists a few
pertinent addresses and shows the memory content at each of these addresses.


 The mode field of the instruction can specify any one of a number of modes. For
each possible mode we calculate the effective address and the operand that must be
loaded into AC.

 In the direct address mode the effective address is the address part of the instruction
500 and the operand to be loaded into AC is 800. In the immediate mode the second
word of the instruction is taken as the operand rather than an address, so 500 is loaded
into AC. (The effective address in this case is 201 .)

 In the indirect mode the effective address is stored in memory at address 500.
Therefore, the effective address is 800 and the operand is 300. In the relative mode
the effective address is 500 + 202 = 702 and the operand is 325.

 (Note that the value in PC after the fetch phase and during the execute phase is
202.) In the index mode the effective address is XR + 500 = 100 + 500 = 600 and the
operand is 900. In the register mode the operand is in R1 and 400 is loaded into AC.
 (There is no effective address in this case.) In the register indirect mode the
effective address is 400, equal to the content of R1 and the operand loaded into AC is
700.

 The autoincrement mode is the same as the register indirect mode except that R1 is
incremented to 401 after the execution of the instruction. The autodecrement mode
decrements R1 to 399 prior to the execution of the instruction.

 The operand loaded into AC is now 450. Table 4 lists the values of the effective
address and the operand loaded into AC for the nine addressing modes.