Unit-2

Machine Instructions and Programs (Contd...) and Basic Processing Unit:

2.1 ADDRESSING MODES
The different ways in which the location of an operand is specified in an instruction are referred to as
Addressing Modes (Table 2.1).
Table 2.1 Generic addressing modes

2.1.1. IMPLEMENTATION OF VARIABLE AND CONSTANTS

Variables and constants are the simplest data types and are found in almost every computer program. In assembly
language, a variable is represented by allocating a register or memory location to hold its value.
Variable is represented by allocating a memory-location to hold its value. Thus, the value can be changed as needed
using appropriate instructions.There are 2 accessing modes to access the variables:
1) Register Mode
2) Absolute Mode
Register Mode
• The operand is the contents of a register. The name (or address) of the register is given in the instruction.
• Registers are used as temporary storage locations where the data in a register are accessed. For example, the
instruction
Move R1, R2; Copy content of register R1 into register R2.
Absolute (Direct) Mode
• The operand is in a memory-location.The address of memory-location is given explicitly in the instruction.
• The absolute mode can represent global variables in the program.
• For example, the instruction
Move LOC, R2 ; Copy content of memory-location LOC into register R2
Immediate Mode
• The operand is given explicitly in the instruction.
• For example, the instruction
Move #200, R0 ; Place the value 200 in register R0.
• Clearly, the immediate mode is only used to specify the value of a source-operand.

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2.1.2. INDIRECTION AND POINTERS
Instruction does not give the operand or its address explicitly. Instead, the instruction provides information from which
the new address of the operand can be determined. This address is called Effective Address (EA) of the operand.
Indirect Mode
• The EA of the operand is the contents of a register (or memory-location).The register (or memory-location) that
contains the address of an operand is called a Pointer.
• We denote the indirection by name of the register or new address given in the instruction.
E.g: Add (R1), R0; the operand is in memory. Register R1 gives the effective-address (B) of the operand. The data is
read from location B and added to contents of register R0.
To execute the Add instruction in fig 2.1 (a), the processor uses the value which is in register R1, as the EA of the
operand. It requests a read operation from the memory to read the contents of location B. The value read is
the desired operand, which the processor adds to the contents of register R0.Indirect addressing through a memory-
location is also possible as shown in fig 2.1 (b). In this case, the processor first reads the contents of memory-location
A, then requests a second read operation using the value B as an address to obtain the operand. The register or memory
location that contains the address of an operand is called a pointer.
Indirection and the use of pointers are important and powerful concepts in programming.

Fig.2.1 indirect addressing

Example: Adding N numbers using indirect addressing

Program Explanation
• In above program, Register R2 is used as a pointer to the numbers in the list, and the operands are accessed
indirectly through R2.The initialization-section of the program loads the counter-value n from memory-location N into
R1 and uses the immediate addressing-mode to place the address value NUM1, which is the address of the first number
in the list, into R2. Then it clears R0 to 0.
• The first two instructions in the loop implement the unspecified instruction block starting at LOOP.
• The first time through the loop, the instruction Add (R2), R0 fetches the operand at location NUM1 and adds it to R0.

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• The second Add instruction adds 4 to the contents of the pointer R2, so that it will contain the address value
NUM2 when the above instruction is executed in the second pass through the loop.
2.1.3. Indexing and arrays
A different kind of flexibility for accessing operands is useful in dealing with lists and arrays.
Index mode
• The operation is indicated as X (Ri)
where X=the constant value which defines an offset(also called a displacement).
Ri=the name of the index register which contains address of a new location.
• The effective-address of the operand is given by EA=X+ [Ri]
• The contents of the index-register are not changed in the process of generating the effective address.
• The constant X may be given either as an explicit number or as a symbolic-name representing a numerical value.

Figure 2.2.Indexed addressing

Fig2.2 illustrates two ways of using the Index mode. In fig(a), the index register, R1, contains the address of a memory-
location, and the value X defines an offset(also called a displacement) from this address to the location where the
operand is found.
• To find EA of operand:
Eg: Add 20(R1), R2
EA=>1000+20=1020
• An alternative use is illustrated in fig(b). Here, the constant X corresponds to a memory address, and the contents of
the index register define the offset to the operand. In either case, the effective-address is the sum of two values; one is
given explicitly in the instruction, and the other is stored in a register.
Ex: List of test scores for students taking a given course.

Figure.2.3 A List of Student Marks Figure 2.4 index addressing used in accessing the test score
Two dimensional array having n rows and four Colum’s. Each row contains entries for one student and Colum’s gives
ID and test score. To compute the sum of all scores obtained on each of the tests and store these three sums in memory
location Sum1,Sum2 and Sum3.Register R0 is used as the index register. Before entering loop Ro is set to point to the
ID location of the first student record. It contains the address list.

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First pass T1,T2,T3 add to the R1,R2.R3 which is initially cleared to zero. These scores accessed using index addressing
mode4(R0),8(R0)and 12(R0).
Base with Index Mode
• Another version of the Index mode uses 2 registers which can be denoted as (Ri, Rj), Here, a second register may be
used to contain the offset X.The second register is usually called the base register.
• The effective-address of the operand is given by EA=[Ri]+[Rj]
• This form of indexed addressing provides more flexibility in accessing operands because both components of the
effective-address can be changed.
Base with Index & Offset Mode
• Another version of the Index mode uses 2 registers plus a constant, which can be denoted as X(Ri, Rj)
• The effective-address of the operand is given by EA=X+[Ri]+[Rj]
• This added flexibility is useful in accessing multiple components inside each item in a record, where the beginning of
an item is specified by the (Ri, Rj) part of the addressing-mode. In other words, this mode implements a 3-dimensional
array.
RELATIVE MODE
• This is similar to index-mode with one difference:
The effective-address is determined using the PC in place of the general purpose register Ri.
• The operation is indicated as X(PC).
• X(PC) denotes an effective-address of the operand which is X locations above or below the current contents of PC.
• Since the addressed-location is identified "relative" to the PC, the name Relative mode is associated with this type of
addressing.This mode is used commonly in conditional branch instructions.
• An instruction such as
Branch > 0 LOOP ;Causes program execution to go to the branch target location identified by name LOOP if branch
condition is satisfied.
ADDITIONAL ADDRESSING MODES
1) Auto Increment Mode
Effective-address of operand is contents of a register specified in the instruction (Fig: 2.5).After accessing the operand,
the contents of this register are automatically incremented to point to the next item in a list. Implicitly, the increment
amount is 1.This mode is denoted as (Ri)+ ;where Ri=pointer-register.
2) Auto Decrement Mode
The contents of a register specified in the instruction are first automatically decremented and are then used as the
effective-address of the operand. This mode is denoted as -(Ri) ;where Ri=pointer-register.
These 2 modes can be used together to implement an important data structure called a stack.

Figure 2.6 Auto increment addressing used for adding N numbers

2.2 STACKS AND QUEUES
A computer program often needs to perform a particular subtask using the familiar subroutine structure. To organize the
control and information linkage between the main program and the subroutine, a data structure called a stack is used.
A stack is a special type of data structure where elements are inserted from one end and elements are deleted from the
same end. This end is called the top of the stack (Figure: 2.7).
• The various operations performed on stack:
1) Insert: An element is inserted from top end. Insertion operation is called push operation.
2) Delete: An element is deleted from top end. Deletion operation is called pop operation.
• A processor-register is used to keep track of the address of the element of the stack that is at the top at any given time.
This register is called the Stack Pointer (SP).
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 Figure 2.7 A stack of word in the memory

• If we assume a byte-addressable memory with a 32-bit word length,

1) The push operation can be implemented as
Subtract #4, SP
Move NEWITEM, (SP)
Where the subtract instruction subtract the source operand 4 from destination operand contained in SP and places result
in SP. These two instructions move the word from location NEWITEM to top of the stack, decrementing stack pointer
by 4 before the move.
2) The pop operation can be implemented as
Move (SP), ITEM
Add #4, SP
These two instructions move the top value from the stack into location ITEM and then increment stack pointer by 4 so it
points to the new top element. Figure 2.8 shows the effect of these two operations.
If the processor uses Autoincrement and Autodecrement addressing modes then the push operation is
Move NEWITEM,-(SP)
The pop operation
Move (SP)+,ITEM

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 a. After Push from NEWITEM b.After into ITEM
Figure 2.8 Effect stack operation Push and Pop

• Routine for a safe pop and push operation as follows:

Figure2.9 Checking for empty and full error in pop and push operation

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QUEUE
• Data are stored in and retrieved from a queue on a FIFO basis.
• Difference between stack and queue?
1) One end of the stack is fixed while the other end rises and falls as data are pushed and popped.
2) In stack, a single pointer is needed to keep track of top of the stack at any given time.In queue, two pointers are
needed to keep track of both the front and end for removal and insertion respectively.
3) Without further control, a queue would continuously move through the memory of a computer in the direction of
higher addresses. One way to limit the queue to a fixed region in memory is to use a circular buffer.
SUBROUTINES
• A subtask consisting of a set of instructions which is executed many times is called a Subroutine.
• A Call instruction causes a branch to the subroutine (Figure: 2.10). At the end of the subroutine, a return instruction is
executed
• Program resumes execution at the instruction immediately following the subroutine call
• The way in which a computer makes it possible to call and return from subroutines is referred to as its Subroutine
Linkage method.
• The simplest subroutine linkage method is to save the return-address in a specific location, which may be a register
dedicated to this function. Such a register is called the Link Register.
• When the subroutine completes its task, the Return instruction returns to the calling-program by branching indirectly
through the link-register.
• The Call Instruction is a special branch instruction that performs the following operations:
→ Store the contents of PC into link-register.
→ Branch to the target-address specified by the instruction.
• The Return Instruction is a special branch instruction that performs the operation:
→ Branch to the address contained in the link-register.

Figure 2.10 subroutine linkage using a link register

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SUBROUTINE NESTING AND THE PROCESSOR STACK
• Subroutine Nesting means one subroutine calls another subroutine. In this case, the return-address of the second call is
also stored in the link-register, destroying its previous contents. Hence, it is essential to save the contents of the link-
register in some other location before calling another subroutine. Otherwise, the return-address of the first subroutine
will be lost. Subroutine nesting can be carried out to any depth. Eventually, the last subroutine called completes its
computations and returns to the subroutine that called it.
• The return-address needed for this first return is the last one generated in the nested call sequence.That is, return-
addresses are generated and used in a LIFO order.
• This suggests that the return-addresses associated with subroutine calls should be pushed onto a stack. A particular
register is designated as the SP (Stack Pointer) to be used in this operation.
• SP is used to point to the processor-stack. Call instruction pushes the contents of the PC onto the processor-stack.
Return instruction pops the return-address from the processor-stack into the PC.
PARAMETER PASSING
• The exchange of information between a calling-program and a subroutine is referred to as Parameter Passing (Figure:
2.11).The parameters may be placed in registers or in memory-location, where they can be accessed by the subroutine.
• Alternatively, parameters may be placed on the processor-stack used for saving the return-address.
• Following is a program for adding a list of numbers using subroutine with the parameters passed through registers.

Figure 2.11 Adding a list of numbers using subroutine with the parameters passed through registers.

STACK FRAME
• Stack Frame refers to locations that constitute a private work-space for the subroutine. The work-space is created at
the time the subroutine is entered & freed up when the subroutine returns control to the calling-program (Figure: 2.12).
Frame Pointer (FP) is used to access the parameters passed to the subroutine & to the local memory-variables.
• The contents of FP remains fixed throughout the execution of the subroutine, unlike stack-pointer SP, which must
always point to the current top element in the stack.

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Figure 2.12 Program for adding a list of numbers using subroutine with the parameters passed to stack.
Operation on Stack Frame
• Initially SP is pointing to the address of old TOS. The calling-program saves 4 parameters on the stack (Figure 2.13).
• The Call instruction is now executed, pushing the return-address onto the stack. Now, SP points to this return-address,
and the first instruction of the subroutine is executed. Now, FP is to be initialized and its old contents have to be stored.
Hence, the first 2 instructions in the subroutine are:
Move FP,-(SP)
Move SP,FP
• The FP is initialized to the value of SP i.e. both FP and SP point to the saved FP address. The 3 local variables may
now be pushed onto the stack. Space for local variables is allocated by executing the instruction
Subtract #12,SP
• Finally, the contents of processor-registers R0 and R1 are saved in the stack. At this point, the stackframe
has been set up as shown in the fig 2.13.The subroutine now executes its task. When the task is completed, the
subroutine pops the saved values of R1 and R0 back into those registers, removes the local variables from the stack
frame by executing the instruction.
Add #12, SP
• And subroutine pops saved old value of FP back into FP. At this point, SP points to return-address, so the Return
instruction can be executed, transferring control back to the calling-program.

Figure 2.13 A subroutine stack frame example

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Problem: Register R5 is used in a program to point to the top of a stack. Write a sequence of instructions using
the Index, Autoincrement, and Autodecrement addressing modes to perform each of the following tasks:
(a) Pop the top two items off the stack, and them, and then push the result onto the stack.
(b) Copy the fifth item from the top into register R3.
(c) Remove the top ten items from the stack.
Solution:
(a) Move (R5)+,R0
Add (R5)+,R0
Move R0,-(R5)
(b) Move 16(R5),R3
(c) Add #40,R5

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 Basic Processing unit
Some Fundamental Concepts
A typical computing task consists of a series of operations specified by a sequence of machine-language instructions
that constitute a program. The processor fetches one instruction at a time and performs the operation specified.
The processor uses the program counter, PC, to keep track of the address of the next instruction to be fetched and
executed.
After fetching an instruction, the contents of the PC are updated to point to the next instruction in sequence.
When an instruction is fetched, it is placed in the instruction register, IR, from where it is interpreted, or decoded, by the
processor’s control circuitry. The IR holds the instruction until its execution is completed.
Consider a 32-bit computer in which each instruction is contained in one word in the memory. To execute an
instruction, the processor has to perform the following steps:
Fetch contents of memory-location pointed to by PC. Content of this location is an instruction to be executed. The
instructions are loaded into IR, Symbolically, this operation is written as: IR←[[PC]].
Increment the PC to point to the next instruction. Assuming that the memory is byte addressable, the PC is incremented
by 4; that is PC←[PC] + 4.
Carry out the operation specified by the instruction in the IR.
The first 2 steps are referred to as Fetch Phase. Step 3 is referred to as Execution Phase.
Single bus organization
To study these operations in detail, let us examine the internal organization of the processor. The main building blocks
of a processor are interconnected in a variety of ways. A very simple organization is shown in Figure 2.14.

Fig.2.14. Single bus organization of the datapath inside a processor

• ALU and all the registers are interconnected via a Single Common Bus .
• Data & address lines of the external memory-bus is connected to the internal processor-bus via MDR & MAR
respectively.
(MDR→ Memory Data Register, MAR → Memory Address Register). MDR has 2 inputs and 2 outputs.
Data may be loaded into MDR either from memory-bus (external) or from processor-bus (internal). MAR‟s input is
connected to internal-bus;MAR‟s output is connected to external bus. Instruction Decoder & Control Unit is
responsible for
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→ issuing the control-signals to all the units inside the processor.
→ implementing the actions specified by the instruction (loaded in the IR).
• Register R0 through R(n-1) are the Processor Registers.The programmer can access these registers for general-purpose
use.
• Only processor can access 3 registers Y, Z & Temp for temporary storage during program-execution.The programmer
cannot access these 3 registers.
• In ALU, “A” input gets the operand from the output of the multiplexer (MUX). “B” input gets the operand directly
from the processor-bus.
• There are 2 options provided for “A” input of the ALU.
• MUX is used to select one of the 2 inputs. MUX selects either output of Y or constant-value 4( which is used to
increment PC content).
• An instruction is executed by performing one or more of the following operations:
1) Transfer a word of data from one register to another or to the ALU.
2) Perform arithmetic or a logic operation and store the result in a register.
3) Fetch the contents of a given memory-location and load them into a register.
4) Store a word of data from a register into a given memory-location.
• Disadvantage: Only one data-word can be transferred over the bus in a clock cycle.
Solution: Provide multiple internal-paths. Multiple paths allow several data-transfers to take place in
Register transfers
• Instruction execution involves a sequence of steps in which data are transferred from one register to another.
• For each register, two control-signals are used: Riin & Riout. These are called Gating Signals.
• Riin=1 → data on bus is loaded into Ri. Riout=1 → content of Ri is placed on bus.
Riout=0, → bus can be used for transferring data from other registers.
• For example, Move R1, R2; This transfers the contents of register R1 to register R2. This can be accomplished as
follows:
1) Enable the output of registers R1 by setting R1out to 1 (Figure 2.15).This places the contents of R1 on processor-bus.
2) Enable the input of register R2 by setting R2out to 1.This loads data from processor-bus into register R4.
• All operations and data transfers within the processor take place within time-periods defined by the processor-clock.
• The control-signals that govern a particular transfer are asserted at the start of the clock cycle.
Internal processor
bus
Riin

Ri

Riout
Yin

Y
Constant 4
Select MUX

A B
AL

Zin
Z

Z out

Figure 2.15 Input and output gating for the registers

Input & Output Gating for one Register Bit

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• A 2-input multiplexer is used to select the data applied to the input of an edge-triggered D flip-flop. Riin=1 → mux
selects data on bus. This data will be loaded into flip-flop at rising-edge of clock. Riin=0 → mux feeds back the value
currently stored in flip-flop (Figure 2.16). Q output of flip-flop is connected to bus via a tri-state gate.Riout=0 → gate's
output is in the high-impedance state.
Riout=1 → the gate drives the bus to 0 or 1, depending on the value of Q.

Bus

Fig.2.15. Input and output gating for the registers bit

Performing an arithmetic or logic operation
• The ALU performs arithmetic operations on the 2 operands applied to its A and B inputs. One of the operands is
output of MUX;
And, the other operand is obtained directly from processor-bus.The result (produced by the ALU) is stored temporarily
in register Z.
• The sequence of operations for [R3] → [R1]+[R2] is as follows:
1) R1out, Yin
2) R2out, SelectY, Add, Zin
3) Zout, R3in
• Instruction execution proceeds as follows:
Step 1 --> Contents from register R1 are loaded into register Y.
Step2 --> Contents from Y and from register R2 are applied to the A and B inputs of ALU;Addition is performed &
Result is stored in the Z register.
Step 3 --> The contents of Z register is stored in the R3 register.
• The signals are activated for the duration of the clock cycle corresponding to that step. All other signals are inactive.
Control-signals of MDR
• The MDR register has 4 control-signals (Figure 2.16):
1) MDRin & MDRout control the connection to the internal processor data bus &
2) MDRinE & MDRoutE control the connection to the memory Data bus.
• MAR register has 2 control-signals.
1) MARin controls the connection to the internal processor address bus &
2) MARout controls the connection to the memory address bus.

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 Figure 2.16 Connection and control signal for register MDR
Fetching a word from memory
To fetch instruction/data from memory, processor transfers required address to MAR. At the same time, processor
issues Read signal on control-lines of memory-bus.
• When requested-data are received from memory, they are stored in MDR. From MDR, they are transferred to other
registers.
• The response time of each memory access varies (based on cache miss, memory-mapped I/O). To accommodate this,
MFC is used. (MFC → Memory Function Completed).
• MFC is a signal sent from addressed-device to the processor. MFC informs the processor that the requested operation
has been completed by addressed-device.
• Consider the instruction Move (R1),R2. The sequence of steps is (Figure 2.17):
1) R1out, MARin, Read ;desired address is loaded into MAR & Read command is issued.
2) MDRinE, WMFC ;load MDR from memory-bus & Wait for MFC response from memory.
3) MDRout, R2in ;load R2 from MDR.
where WMFC=control-signal that causes processor's control.circuitry to wait for arrival of MFC signal.

Figure 2.17 Timing of a memory read operation

Storing a Word in Memory
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• Consider the instruction Move R2,(R1). This requires the following sequence:
1) R1out, MARin ;desired address is loaded into MAR.
2) R2out, MDRin, Write ;data to be written are loaded into MDR & Write command is issued.
3) MDRoutE, WMFC ;load data into memory-location pointed by R1 from MDR.
Execution of a complete instruction
• Consider the instruction Add (R3),R1 which adds the contents of a memory-location pointed by R3 to register R1.
Executing this instruction requires the following actions:
1) Fetch the instruction.
2) Fetch the first operand.
3) Perform the addition &
4) Load the result into R1.
• Instruction execution proceeds as follows:
Step1--> The instruction-fetch operation is initiated by loading contents of PC into MAR & sending a Read request to
memory.
The Select signal is set to Select4, which causes the Mux to select constant 4. This value is added to operand at input B
(PC‟s content), and the result is stored in Z.
Step2--> Updated value in Z is moved to PC. This completes the PC increment operation and PC will now point to next
instruction.
Step3--> Fetched instruction is moved into MDR and then to IR.
The step 1 through 3 constitutes the Fetch Phase.
At the beginning of step 4, the instruction decoder interprets the contents of the IR. This enables the control circuitry to
activate the control-signals for steps 4 through 7.
The step 4 through 7 constitutes the Execution Phase.
Step4--> Contents of R3 are loaded into MAR & a memory read signal is issued.
Step5--> Contents of R1 are transferred to Y to prepare for addition.
Step6--> When Read operation is completed, memory-operand is available in MDR, and the addition is performed.
Step7--> Sum is stored in Z, then transferred to R1.The End signal causes a new instruction fetch cycle to begin by
returning to step1.

Figure 2.18control sequence for execution of the instruction Add (R3),R1

Branching instructions
A branch instruction replaces the contents of the PC with the branch target address. This address is usually obtained by
adding anoffset X, which is given in the branch instruction, to the updated value of the PC.
The offset X is usually the difference between the branch target address and the address immediately following the
branch instruction.Control sequence for an unconditional branch instruction is as follows:

Fig.2.18 Control sequence for an unconditional branch instruction

Instruction execution proceeds as follows:

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Step 1-3--> The processing starts & the fetch phase ends in step3.
Step 4--> The offset-value is extracted from IR by instruction-decoding circuit. Since the updated value of PC is already
available in register Y, the offset X is gated onto the bus, and an addition operation is performed.
Step 5--> the result, which is the branch-address, is loaded into the PC.
• The branch instruction loads the branch target address in PC so that PC will fetch the next instruction from the branch
target address.
• The branch target address is usually obtained by adding the offset in the contents of PC.
Multiple bus organization
• Disadvantage of Single-bus organization: Only one data-word can be transferred over the bus in a clock cycle. This
increases the steps required to complete the execution of the instruction
Solution: To reduce the number of steps, most processors provide multiple internal-paths. Multiple paths enable several
transfers to take place in parallel.
• As shown in fig 2.19, three buses can be used to connect registers and the ALU of the processor.
• All general-purpose registers are grouped into a single block called the Register File.
• Register-file has 3 ports:
1) Two output-ports allow the contents of 2 different registers to be simultaneously placed on buses A & B.
2) Third input-port allows data on bus C to be loaded into a third register during the same clock-cycle.
• Buses A and B are used to transfer source-operands to A & B inputs of ALU.
• The result is transferred to destination over bus C.
• Incrementer Unit is used to increment PC by 4.

Fig.2.19 Three bus organization of the datapath

Fig.2.20 Control sequence for the instruction Add R4,R5,R6 for three bus organization

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 The control sequence for executing this instruction is given in Figure 2.20. In step 1, the contents of the PC are
passed through the ALU, using the R=B control signal, and loaded into the MAR to start a memory read operation. At
the same time the PC is incremented by 4. Note that the value loaded into MAR is the original contents of the PC. The
incremented value is loaded into the PC at the end of the clock cycle and will not affect the contents of MAR. In step 2,
the processor waits for MFC and loads the data received into MDR, then transfers them to IR in step 3. Finally, the
execution phase of the instruction requires only one control step to complete, step 4. By providing more paths for data
transfer a significant reduction in the number of clock cycles needed to execute an instruction is achieved.
COMPLETE PROCESSOR
• This has separate processing-units to deal with integer data and floating-point data.
Integer Unit → To process integer data. (Figure 2.21). Floating Unit → To process floating –point data.
• Data-Cache is inserted between these processing-units & main-memory. The integer and floating unit gets data from data
cache.
• Instruction-Unit fetches instructions → from an instruction-cache or → from main-memory when desired instructions are
not already in cache. • Processor is connected to system-bus & hence to the rest of the computer by means of a Bus Interface.
• Using separate caches for instructions & data is common practice in many processors today.
• A processor may include several units of each type to increase the potential for concurrent operations.
• The 80486 processor has 8-kbytes single cache for both instruction and data. Whereas the Pentium processor has two
separate 8 kbytes caches for instruction and data.

Figure 2.21 Block diagram of complete processor

To execute instructions, the processor must have some means of generating the control-signals. There are two approaches for
this purpose:
1) Hardwired control and 2) Microprogrammed control.

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Hardwired control
• Hardwired control is a method of control unit design (Figure 2.22).
• The control-signals are generated by using logic circuits such as gates, flip-flops, decoders etc.
• Decoder/Encoder Block is a combinational-circuit that generates required control-outputs depending on state of all its inputs.
Instruction Decoder
It decodes the instruction loaded in the IR.
If IR is an 8 bit register, then instruction decoder generates 28(256 lines); one for each instruction.
It consists of a separate output-lines INS1 through INSm for each machine instruction.
According to code in the IR, one of the output-lines INS1 through INSm is set to 1, and all other lines are set to 0.
• Step-Decoder provides a separate signal line for each step in the control sequence.
Encoder
It gets the input from instruction decoder, step decoder, external inputs and condition codes.
It uses all these inputs to generate individual control-signals: Yin, PCout, Add, End and so on.
For example (Figure 2.23), Zin=T1+T6.ADD+T4.BR ;This signal is asserted during time-slot T1 for all instructions. during
T6 for an Add instruction. During T4 for unconditional branch instruction
• When RUN=1, counter is incremented by 1 at the end of every clock cycle.
When RUN=0, counter stops counting.
• After execution of each instruction, end signal is generated. End signal resets step counter.
• Sequence of operations carried out by this machine is determined by wiring of logic circuits, hence
the name “hardwired”.
• Advantage: Can operate at high speed.
• Disadvantages:
1) Since no. of instructions/control-lines is often in hundreds, the complexity of control unit is
very high.
2) It is costly and difficult to design.
3) The control unit is inflexible because it is difficult to change the design.

Fig.2.22 separation of the decoding and encoding function Fig.2.23 Generation of the Zin control signal for the processor
Microprogrammed control
• Microprogramming is a method of control unit design (Figure 2.24).

Fig.2.24 Basic organization of a microprogrammed control unit

• Control-signals are generated by a program similar to machine language programs.
• Control Word(CW) is a word whose individual bits represent various control-signals (like Add, PCin).
• Each of the control-steps in control sequence of an instruction defines a unique combination of 1s & 0s in CW.
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• Individual control-words in microroutine are referred to as microinstructions (Figure 2.25).
• A sequence of CWs corresponding to control-sequence of a machine instruction constitutes the microroutine.
• The microroutines for all instructions in the instruction-set of a computer are stored in a special memory called the Control Store
(CS).
• Control-unit generates control-signals for any instruction by sequentially reading CWs of corresponding microroutine from CS.
• μPC is used to read CWs sequentially from CS. (μPC Microprogram Counter).
• Every time new instruction is loaded into IR, o/p of Starting Address Generator is loaded into μPC.
• Then, μPC is automatically incremented by clock; causing successive microinstructions to be read from CS.
Hence, control-signals are delivered to various parts of processor in correct sequence.

Fig.2.25 An example of micro instruction

Organization of microprogrammed control unit to support conditional Branching
• Drawback of previous Microprogram control:
It cannot handle the situation when the control unit is required to check the status of the condition codes or external inputs to
choose between alternative courses of action.
Solution:
Use conditional branch microinstruction Fig.2.26

.
Fig2.26 Microroutine for the instruction Branch<0

• In case of conditional branching, microinstructions specify which of the external inputs, condition codes should be checked as a
condition for branching to take place.
• Starting and Branch Address Generator Block loads a new address into μPC when a microinstruction instructs it to do so (Figure
2.27).
• To allow implementation of a conditional branch, inputs to this block consist of
→ external inputs and condition-codes &
→ contents of IR.
• μPC is incremented every time a new microinstruction is fetched from microprogram memory except in following situations:
1) When a new instruction is loaded into IR, μPC is loaded with starting-address of microroutine for that instruction.
2) When a Branch microinstruction is encountered and branch condition is satisfied, μPC is loaded with branch-address.
3) When an End microinstruction is encountered, μPC is loaded with address of first CW in microroutine for instruction fetch cycle.

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 Fig.2.27 Organization of the control unit to allow conditional branching in the microprogram

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Problem
1:Why is the Wait-for-memory-function-completed step needed for reading from or writing to the main memory?
Sol: The WMFC step is needed to synchronize the operation of the processor and the main memory.
2:For the single bus organization, write the complete control sequence for the instruction: Move (R1), R1
Sol:
1. PCout, MARin, Read, Select4, Add, Zin
2) Zout, PCin, Yin, WMFC
3) MDRout, IRin
4) R1out, MARin, Read
5) MDRinE, WMFC
6) MDRout, R2in, End

3.Write the sequence of control steps required for the single bus organization in each of the following
instructions:
a) Add the immediate number NUM to register R1.
b) Add the contents of memory-location NUM to register R1.
c) Add the contents of the memory-location whose address is at memory-location NUM to register R1.Assume that each instruction
consists of two words. The first word specifies the operation and N the addressing mode, and the second word contains the number
NUM
Sol:

4. Show the control steps for the Branch on Negative instruction for a processor with three-bus organization of the data path

Sol:

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