1 Digital Logic BIT

Unit-4
Combinational Logic

For more notes visit:

https://collegenote.pythonanywhere.com/

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

2 Digital Logic BIT

Unit-4
Combinational Logic
Combinational circuit is a circuit which consist of logic gates whose outputs at any instant of
time are determined directly from the present combination of inputs without regard to
previous input. The combinational circuit do not use any memory.
- There will be 2𝑛 combination of input variable for 𝑛 inputs.
- A combinational circuit can have 𝑛 number of inputs and 𝑚 number of outputs.
- For e.g. adders, subtractors, decoders, encoders etc.

Fig: Block diagram of combinational circuit

Combinational logic circuit design procedure:
1. The problem is stated.
2. The number of available input variables and required output variables is determined.
3. The input and output variables are assigned letter symbols.
4. The truth table that defines the required relationships between inputs and outputs is
derived.
5. The simplified Boolean function for each output is obtained.
6. The logic diagram is drawn.

Adders
Adders are the combinational circuits which is used to add two or more than two bits at a
time.
Types of adders:
- Half Adder
- Full Adder

1. Half Adder:
A combinational circuit that performs the addition of bits is called half adder. This circuit
needs two binary inputs and two binary outputs. The input variables designate the
augend(𝐴) and addend(𝐵) bits; the output variables produce the sum(𝑆) and carry(𝐶).

Fig: Block diagram

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

3 Digital Logic BIT

Truth table to identify the function of half adder:

K-map:

From k-map the logical expression for sum and carry is:
𝐶 = 𝐴𝐵
𝑆 = 𝐴̅𝐵 + 𝐴𝐵̅ = 𝐴⨁𝐵
Logic diagram:

Q. Design a half adder using only NAND gates.

Soln:
Input variables: A & B, Output variables: sum(𝑆) and carry(𝐶)
𝑆 = 𝐴̅𝐵 + 𝐴𝐵̅
𝐶 = 𝐴𝐵
Logic diagram of half adder using NAND gates only:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

4 Digital Logic BIT

Q. Design a half adder logic circuit using NOR gates only.

Soln:
Input variables: A & B, Output variables: sum(𝑆) and carry(𝐶)
̅
𝑆 = 𝐴𝐵 + 𝐴𝐵 ̅
𝐶 = 𝐴𝐵
Logic diagram of half adder using NOR gates only:

2. Full Adder:
A combinational circuit that performs the addition of three bits at a time is called full
adder. It consists of three inputs and two outputs, two inputs are the bits to be added, the
third input represents the carry from the previous position.

Fig: Block diagram

Truth table for full adder:

- The sum(S) output is equal to 1 when

only one input is equal to 1 or when all
three inputs are equal to 1.
- The carry output (𝐶𝑜𝑢𝑡 ) has a carry 1 if
two or three inputs are equal to 1.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

5 Digital Logic BIT

Simplified expression using k-map in SOP can be obtained as;

𝑆𝑢𝑚(𝑆) = 𝐴̅𝐵̅𝐶𝑖𝑛 + 𝐴̅𝐵𝐶𝑖𝑛

̅ + 𝐴𝐵̅𝐶𝑖𝑛
̅ + 𝐴𝐵𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶𝑖𝑛 + 𝐵𝐶𝑖𝑛
Logic Diagram:

For carry For sum

Fig: SOP implementation of full-adder
Note: It can also be implemented in POS form. (Try yourself)

Implementation of a full-adder with two half-adders and an OR gate:

Logic expression for sum:

̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴⨁𝐵)⨁𝐶𝑖𝑛 = (𝐴̅𝐵 + 𝐴𝐵̅)⨁𝐶𝑖𝑛 = (𝐴 ̅𝐵 + 𝐴𝐵̅)𝐶𝑖𝑛 + (𝐴̅𝐵 + 𝐴𝐵̅)𝐶𝑖𝑛
̅
= (𝐴 + 𝐵̅)(𝐴̅ + 𝐵)𝐶𝑖𝑛 + 𝐴̅𝐵𝐶𝑖𝑛̅ + 𝐴𝐵̅𝐶𝑖𝑛
̅
̅ ̅ ̅ ̅
= 𝐴𝐵 𝐶𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛 + 𝐴𝐵𝐶𝑖𝑛̅ ̅

Logic expression for carry:

(𝐴⨁𝐵)𝐶𝑖𝑛 + 𝐴𝐵 = (𝐴̅𝐵 + 𝐴𝐵̅)𝐶𝑖𝑛 + 𝐴𝐵 = 𝐴̅𝐵𝐶𝑖𝑛 + 𝐴𝐵̅𝐶𝑖𝑛 + 𝐴𝐵

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

6 Digital Logic BIT

Simplification of carry:

∴ 𝐶𝑜𝑢𝑡 = 𝐴𝐵 + 𝐴𝐶𝑖𝑛 + 𝐵𝐶𝑖𝑛

Subtractors
Subtractor is a combinational logic circuit which is used to subtract two or more than two bits
at a time, and provides difference and borrow as an output.
Types of Subtractors:
- Half subtractor
- Full subtractor

1. Half Subtractor:
A half-subtractor is a combinational logic circuit that subtract two bits at a time and
produces their difference.
It has two inputs minuend (A) & subtrahend (B) and two outputs difference and borrow.
The difference is a result of subtraction and borrow is used to indicate borrow from next
most significant bit. The borrow bit is present only when 𝐴 < 𝐵.

Truth table:

K-map:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

7 Digital Logic BIT

Logic Diagram:

Fig: Implementation of half-subtractor

2. Full Subtractor:
A combinational logic circuit used to subtract three binary digits at a time is called full
subtractor.
This circuit has three input and two outputs. The three inputs are 𝐴, 𝐵 𝑎𝑛𝑑 𝐵𝑖𝑛 , denote the
minuend, subtrahend and previous borrow respectively. The two outputs, 𝐷 𝑎𝑛𝑑 𝐵𝑜𝑢𝑡
represent the difference and output borrow, respectively.
Truth table for full subtractor:

Simplified expression of D and Bout using k-map in SOP can be obtained as;

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

8 Digital Logic BIT

Logic circuit for full subtractor:

For D For Bout

Fig: SOP implementation of full-subtractor

Note: It can also be implemented in POS form. (Try yourself)

Implementation of full subtractor using two half subtractor and one OR gate:

̅̅̅̅̅̅̅̅̅̅̅̅
𝐷 = (𝐴⨁𝐵)⨁𝐵𝑖𝑛 = (𝐴̅𝐵 + 𝐴𝐵̅)⨁𝐵𝑖𝑛 = (𝐴 ̅ 𝐵 + 𝐴𝐵̅ )𝐵𝑖𝑛 + (𝐴̅𝐵 + 𝐴𝐵̅)𝐵̅𝑖𝑛
= {(𝐴 + 𝐵̅)(𝐴̅ + 𝐵)}𝐵𝑖𝑛 + 𝐴̅𝐵𝐵̅𝑖𝑛 + 𝐴𝐵̅𝐵̅𝑖𝑛
= 𝐴̅𝐵̅𝐵𝑖𝑛 + 𝐴𝐵𝐵𝑖𝑛 + 𝐴̅𝐵𝐵̅𝑖𝑛 + 𝐴𝐵̅𝐵̅𝑖𝑛

𝐵𝑜𝑢𝑡 = (̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅̅̅

𝐴⨁𝐵)𝐵𝑖𝑛 + 𝐴̅𝐵 = (𝐴 ̅𝐵 + 𝐴𝐵̅)𝐵𝑖𝑛 + 𝐴̅𝐵 = {(𝐴 + 𝐵̅)(𝐴̅ + 𝐵)}𝐵𝑖𝑛 + 𝐴̅𝐵
= 𝐴̅𝐵̅𝐵𝑖𝑛 + 𝐴𝐵𝐵𝑖𝑛 + 𝐴̅𝐵
Using k-map:

∴ 𝐵𝑜𝑢𝑡 = 𝐴̅𝐵𝑖𝑛 + 𝐴̅𝐵 + 𝐵𝐵𝑖𝑛

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

9 Digital Logic BIT

Code Conversion
- The availability of large variety of codes for the same discrete elements of information
results in the use of different codes by the different system.
- A conversion circuit must be inserted between the two systems if each use different codes
for same information.
- Thus a code converter is a circuit that makes the two systems compatible even though
each uses a different binary information.
BCD to excess-3 Code Conversion:
BCD Excess-3 circuit will convert numbers from their binary representation to their excess-3
representation. Since each code uses four bits to represent a decimal digit, there must be four
input variables and four outputs variables. Let the input four binary variables are 𝐴, 𝐵, 𝐶 & 𝐷
and the four output variables are 𝑊, 𝑋, 𝑌 & 𝑍.
Truth table:

Note: Four binary variables may

have 16 bit combinations, and
only 10 of which are listed in
truth table i.e. from 0 to 9. The
rest six bit combinations not
listed for input variables are
don’t care combinations.

K-maps for BCD to excess-3 code converter:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

10 Digital Logic BIT

The Boolean functions for the outputs lines of the circuit are derived from k-maps
which are:
𝑊 = 𝐴 + 𝐵𝐶 + 𝐵𝐷 = 𝐴 + 𝐵(𝐶 + 𝐷)
𝑋 = 𝐵′ 𝐶 + 𝐵′ 𝐷 + 𝐵𝐶 ′ 𝐷′ = 𝐵′ (𝐶 + 𝐷) + 𝐵(𝐶 + 𝐷)′
𝑌 = 𝐶𝐷 + 𝐶 ′ 𝐷′ = 𝐶𝐷 + (𝐶 + 𝐷)′
𝑍 = 𝐷′
Logic diagram for BCD to excess-3 converter:

BCD to Seven-segment Decoder

A BCD to seven-segment decoder is a combinational circuit that accepts a decimal digit in

BCD and generates the appropriate outputs for the selection of segments in a display
indicator used for displaying the decimal digit. The seven output of the decoder (a,b,c,d,e,f,g)
select the corresponding segments in the display as shown in figure a. The numeric
designation chosen to represent the decimal digit is shown in figure b.

Fig(a):Segment designation Fig(b):Numerical designation for display

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

11 Digital Logic BIT

Truth table:

K-map:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

12 Digital Logic BIT

Logic Diagram:

Analysis Procedure
To obtain the Boolean expressions and truth tables from the combinational logic circuit, we
need to analyse the circuit. First ensure that the circuit is combinational - that is there is no
feedback of an output to an input that the output depends on.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

13 Digital Logic BIT

1st step: make sure that circuit is combinational.

2nd step: obtain the output Boolean functions or the truth table.
 Obtaining Boolean functions from logic diagram:
Steps:
1. Label all gate outputs that are a function only of input variables or their complements
with arbitrary symbols. Determine the Boolean functions for each gate output.
2. Label the gates that are a function of input variables and previously labeled gates with
other arbitrary symbols. Find the Boolean functions for the outputs of these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained.
4. By repeated substitution of previously defined functions, obtain the output Boolean
functions in terms of input variables only.
A straight-forward procedure:

Step 1: Step 2 & 3:

𝐹2 = 𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 𝑇3 = 𝐹2′ 𝑇1
𝑇1 = 𝐴 + 𝐵 + 𝐶 𝐹1 = 𝑇3 + 𝑇2
𝑇2 = 𝐴𝐵𝐶
Step 4:
𝐹1 = 𝑇3 + 𝑇1 = 𝐹2′ 𝑇1 + 𝐴𝐵𝐶 = (𝐴𝐵 + 𝐴𝐶 + 𝐵𝐶 )′ (𝐴 + 𝐵 + 𝐶 ) + 𝐴𝐵𝐶
= (𝐴′ + 𝐵′ )(𝐴′ + 𝐶 ′ )(𝐵′ + 𝐶 ′ )(𝐴 + 𝐵 + 𝐶 ) + 𝐴𝐵𝐶
= (𝐴′ + 𝐵′ 𝐶 ′ )(𝐴𝐵′ + 𝐴𝐶 ′ + 𝐵𝐶 ′ + 𝐵′ 𝐶 ) + 𝐴𝐵𝐶
= 𝐴′ 𝐵𝐶 ′ + 𝐴′ 𝐵′ 𝐶 + 𝐴𝐵′ 𝐶 ′ + 𝐴𝐵𝐶

 Obtaining truth table from logic diagram:

Steps:
1. Determine the number of input variables in the circuit. For 𝑛 inputs, list the binary
numbers from 0 to 2𝑛 − 1 in a table.
2. Label the output of selected gates.
3. Obtain the truth table for the output of those gates that are a function of the input
variables only.
4. Obtain the truth table for those gates that are a function of previously defined
variables at step 3, until all outputs are determined.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

14 Digital Logic BIT

Truth table for the above logic diagram:

Multi-level NAND Circuit

To implement a Boolean function with NAND gates we need to obtain the simplified
Boolean function in terms of Boolean operators and then convert the function to NAND
logic. The conversion of an algebraic expression from AND, OR, and complement to NAND
can be done by simple circuit-manipulation techniques that change AND-OR diagrams to
NAND diagrams.
To obtain a multilevel NAND diagram from a Boolean expression, proceed as follows:
1. From the given Boolean expression, draw the logic diagram with AND, OR, and inverter
gates. Assume that both the normal and complement inputs are available.
2. Convert all AND gates to NAND gates with AND-invert graphic symbols.
3. Convert all OR gates to NAND gates with invert-OR graphic symbols.
4. Check all small circles in the diagram. For every small circle that is not compensated by
another small circle along the same line, insert an inverter (one-input NAND gate) or
complement the input variable.
E.g.
Multilevel Boolean expression: 𝐹 = (𝐶𝐷 + 𝐸)(𝐴 + 𝐵′ )

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

15 Digital Logic BIT

→ NAND diagram using two graphic symbols:

→ NAND diagram using one graphic symbol:

Multi-level NOR Circuit

The NOR function is the dual of the NAND function. For this reason, all procedures and rules
for NOR logic form a dual of the corresponding procedures and rules developed for NAND
logic.
Boolean function implementation using NOR gate:
1. Draw the AND-OR logic diagram from the given algebraic expression. Assume that both
the normal and complement inputs are available.
2. Convert all OR gates to NOR gates with OR-invert graphic symbols.
3. Convert all AND gates to NOR gates with invert-AND graphic symbols.
4. Any small circle that is not compensated by another small circle along the same line
needs an inverter or the complementation of the input variable.
E.g.
𝐹 = (𝐴𝐵 + 𝐸)(𝐶 + 𝐷)

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

16 Digital Logic BIT

(a) (b)

(c)
Fig: Implementing 𝑭 = (𝑨𝑩 + 𝑬)(𝑪 + 𝑫) with NOR gates

Exclusive-OR (XOR)
The exclusive-OR (XOR) denoted by the symbol ⨁ is a logical operation that performs the
following Boolean operation:
𝑥⨁𝑦 = 𝑥𝑦 ′ + 𝑥 ′ 𝑦
It is equal to 1 if only 𝑥 is equal to 1 or if only 𝑦 is equal to 1 but not when both are equal to
1.

Realization of Ex-OR using basic gates and universal gates:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

17 Digital Logic BIT

Parity Generator and Checker

Parity Generator:
A parity generator is a combinational logic circuit that generates the parity bit in the
transmitter.
- A parity bit is used for the purpose of detecting errors during transmission of binary
information. It is an extra bit included with a binary message to make the number of 1’s
either odd or even.
- Types of parity: Even parity & Odd parity.
- In Even parity, added parity bit will make the total number of 1’s an even amount.
- In Odd parity, added parity bit will make the total number of 1’s an odd amount.
3-bit even parity generator truth table:

Solving the truth table for all the

cases where 𝑃 is 1 using SOP
method:

3-bit even parity generator circuit:

Parity checker:
A circuit that checks the parity in the receiver is called parity checker. The parity checker
circuit checks for possible errors in the transmission.
- Since the information transmitted with even parity, the received must have an even
number of 1’s. If it has odd number of 1’s, it indicates that there is an error occurred
during transmission.
3-bit even parity checker truth table;

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

18 Digital Logic BIT

The output of the parity checker is denoted by 𝑃𝐸𝐶 (Parity Error Checker). If there is error,
that is, if it has odd number of 1’s, it will indicate 1. If no then 𝑃𝐸𝐶 will indicate 0.

(Here truth
table’s 𝑃 = 𝐷)

3-bit even parity checker circuit:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

19 Digital Logic BIT

Q. Design a combinational circuit that multiplies 2-bit numbers, 𝒂𝟏 𝒂𝟎 and 𝒃𝟏 𝒃𝟎 to produce a

4-bit product, 𝒄𝟑 𝒄𝟐 𝒄𝟏 𝒄𝟎. Use AND gates and half-adders.
Soln:
Here’s how multiplication would take place:

In the above calculation 𝑎1 𝑎0 is the multiplicand and 𝑏1 𝑏0 is the multiplier. The first product
obtained from multiplying 𝑏0 with the multiplicand is called as partial product 1. And the second
product obtained from multiplying 𝑏1 with the multiplicand is known as the partial product 2.
Based on the above equation, we can see that we need four AND gates and two half
adders. The AND gate will performs the multiplication, and the half adders will add the partial
product terms. Hence the circuit obtained is as follows:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

20 Digital Logic BIT

Combinational Logic with MSI and LSI

Binary Adder
This circuit sums up two binary numbers 𝐴 𝑎𝑛𝑑 𝐵 of n-bits using full-adders to add each bit
pair and carry from previous bit position.

Binary Parallel Adder:

A binary parallel adder is a digital circuit that produces the arithmetic sum of two binary
numbers in parallel. It consists of full adders connected in cascade, with the output carry from
one full adder connected to the input carry of the next full adder. An 𝑛 bit parallel adder
requires 𝑛 full adders.
4-bit binary parallel adder:

Fig: 4-bit binary parallel adder

A 4-bit binary parallel adder consists of 4-full adder. The augend bits are 𝐴4 , 𝐴3 , 𝐴2 , 𝐴1 and
addend bits are 𝐵1 , 𝐵2 , 𝐵3 , 𝐵4 . This parallel adder produces their sum as 𝐶4 𝑆3 𝑆2 𝑆1 𝑆0 where
𝐶4 is the final carry. The carries are connected in chain through the full-adders. The input
carry to the first full adder is 𝐶1 and the output carry from MSB position of full adder is 𝐶4 .

Q. Design a BCD-to-excess-3 code converter using a 4-bit full adders MSI circuit.
Soln:
𝐸𝑥𝑐𝑒𝑠𝑠 − 3 𝑐𝑜𝑑𝑒 = 𝐵𝐶𝐷 𝑐𝑜𝑑𝑒 + (0011)2

Augend bits = 𝑋4 𝑋3 𝑋2 𝑋1 (Input bits)

Addend bits = 𝑌4 𝑌3 𝑌2 𝑌1 = 0011
Excess-3 code = 𝑆4 𝑆3 𝑆2 𝑆1 (output)

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

21 Digital Logic BIT

Decimal adder/BCD adder:

BCD adder is a combinational digital circuit that adds two BCD digits in parallel and
produces sum which is also BCD.
- In BCD adder, each input digit does not exceed 9, so the output sum can’t be greater than
9 + 9 + 1 = 19, the 1 in the sum being an input carry.
- Suppose we apply two BCD digits to a 4-bit binary adder. The adder will form the sum in
binary and produce a result which may range from 0 to 19.

Truth table for BCD adder is:

- In examining the content of the table, it is apparent that when the binary sum is equal to
or less than 1001, the corresponding BCD number is identical, and therefore no
conversion is needed.
- When the binary sum is greater than 1001, we obtain a non- valid BCD representation.
The addition of binary 0110 (6 in decimal) to the binary sum converts it to the correct
BCD representation and also produces an output carry.
- It is obvious from the table that a correction is needed when the binary sum has an output
carry 𝑘 = 1.
- The other six combination from 1010 to 1111 that need a correction have a 1 in position
𝑍8 . To distinguish them from binary 1000 and 1001, which also have a 1 in position 𝑍8 ,
we specify further that either 𝑍4 or 𝑍2 must have 1.
- The condition for a correction and an output carry can be expressed by the Boolean
function: 𝑪 = 𝑲 + 𝒁𝟖 𝒁𝟒 + 𝒁𝟖 𝒁𝟐
- When output carry C = 0, nothing is added to the binary sum.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

22 Digital Logic BIT

- When output carry C = 1, binary 0110 is added to the binary sum through the bottom 4-
bit binary adder to convert the binary sum into BCD sum. (In fig. below)

Fig: BCD adder

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

23 Digital Logic BIT

Magnitude Comparator
A magnitude comparator is a combinational circuit that compares two numbers 𝐴 & 𝐵 and
determines their relative magnitudes. The outcome of the comparison is specified by three
binary variables that indicate whether 𝐴 > 𝐵, 𝐴 = 𝐵, 𝑜𝑟 𝐴 < 𝐵.

Note: Out of these three outputs only one

output will be 1 and other two outputs will
be 0 at a time.

4-bit magnitude comparator:

4-bit magnitude comparator is a combinational logic circuit that compares two binary
numbers each of 4-bits.
Consider two numbers 𝐴 & 𝐵 with four digits each.
𝐴 = 𝐴3 𝐴2 𝐴1 𝐴0
𝐵 = 𝐵3 𝐵2 𝐵1 𝐵0

Verification of (𝑨 = 𝑩):
- The equality relation of each pair of bits can be expressed:
𝑥𝑖 = 𝐴𝑖 𝐵𝑖 + 𝐴̅𝑖 𝐵̅𝑖 , 𝑖 = 0, 1, 2, 3
Where 𝑥𝑖 = 1 only if 𝐴𝑖 = 𝐵𝑖 and 𝑥𝑖 = 0 only if 𝐴𝑖 ≠ 𝐵𝑖 .
- For equality condition to exist, all 𝑥𝑖 variables must be equal to 1. 𝐴 & 𝐵 will be equal if
𝑥3 𝑥2 𝑥1 𝑥0 = 1.
∴ (𝑨 = 𝑩) = 𝒙𝟑 𝒙𝟐 𝒙𝟏 𝒙𝟎

Verification of (𝑨 > 𝑩):

- If 𝐴3 > 𝐵3 then 𝐴 > 𝐵, it means 𝐴3 = 1 & 𝐵3 = 0. Therefore 𝐴 is greater than 𝐵 if
𝑨𝟑 𝑩̅ 𝟑 = 𝟏.
- If 𝐴3 = 𝐵3 (𝑖. 𝑒 𝑥3 = 1) and 𝐴2 > 𝐵2 then 𝐴 > 𝐵. Therefore 𝐴 is greater than 𝐵 if
𝒙𝟑 𝑨𝟐 𝑩̅ 𝟐 = 𝟏.
- If 𝐴3 = 𝐵3 (𝑖. 𝑒 𝑥3 = 1) & 𝐴2 = 𝐵2 (𝑖. 𝑒 𝑥2 = 1) and 𝐴1 > 𝐵1 then 𝐴 > 𝐵. Therefore 𝐴 is
̅ 𝟏 = 𝟏.
greater than 𝐵 if 𝒙𝟑 𝒙𝟐 𝑨𝟏 𝑩
- If 𝐴3 = 𝐵3 (𝑖. 𝑒 𝑥3 = 1) & 𝐴2 = 𝐵2 (𝑖. 𝑒 𝑥2 = 1) & 𝐴1 = 𝐵1 (𝑖. 𝑒 𝑥1 = 1) and 𝐴0 > 𝐵0
̅ 𝟎 = 𝟏.
then 𝐴 > 𝐵. Therefore 𝐴 is greater than 𝐵 if 𝒙𝟑 𝒙𝟐 𝒙𝟏 𝑨𝟎 𝑩
̅ 𝟑 + 𝒙𝟑 𝑨𝟐 𝑩
∴ (𝑨 > 𝑩) = 𝑨𝟑 𝑩 ̅ 𝟐 + 𝒙𝟑 𝒙𝟐 𝑨𝟏 𝑩
̅ 𝟏 + 𝒙𝟑 𝒙𝟐 𝒙𝟏 𝑨𝟎 𝑩
̅𝟎

In the same manner we can derive the expression for (𝑨 < 𝑩).
̅ 𝟑 𝑩𝟑 + 𝒙𝟑 𝑨
∴ (𝑨 > 𝑩) = 𝑨 ̅ 𝟐 𝑩𝟐 + 𝒙𝟑 𝒙𝟐 𝑨
̅ 𝟏 𝑩𝟏 + 𝒙𝟑 𝒙𝟐 𝒙𝟏 𝑨
̅ 𝟎 𝑩𝟎

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

24 Digital Logic BIT

Logic Diagram:

Decoders
A decoder is a combinational circuit that converts binary information from 𝑛 input lines to a
maximum of 2𝑛 unique output lines.
- If 𝑛-bit decoded information has unused or don’t care combinations, the decoder output
will have less than 2𝑛 outputs.
- The decoders presented here are called 𝑛 − 𝑡𝑜 − 𝑚 line decoders where 𝑚 ≤ 2𝑛 . Their
purpose is to generate the 2𝑛 (or less) minterms of 𝑛 input variables.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

25 Digital Logic BIT

3-to-8 line decoder:

The three inputs are decoded into eight outputs, each output representing one of the minterms
of the 3-input variables.
A particular application of this decoder would be a binary-to-octal conversion. The input
variable may represent a binary number and the outputs will then represent the eight digits in
the octal number system
Three inputs: 𝑋, 𝑌 & 𝑍
Eight outputs: 𝐷0 − 𝐷7

Fig: 3-to-8 line decoder

Truth table:

From the truth table it is observed that the output variables are mutually exclusive because
only one output can be equal to 1 at any one time. The output line whose value is equal to 1
represents the minterm equivalent of the binary number presently available in the input lines.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

26 Digital Logic BIT

BCD-to-Decimal Decoder

The decoder which convert binary decimal code into decimal values is called BCD to decimal
decoder. The BCD code uses 4-bits and therefore there can be 24 input combinations. This
produces 16-different output signals but the decimal digits are from 0 to 9. Hence six input
combinations are not used in decimal system. Therefore we can use don’t care to represent 10
to 15 and use K-map to simplify the circuit.

Simplified expression for different outputs are:

Logic diagram of BCD-to-decimal decoder:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

27 Digital Logic BIT

Fig: BCD to Decimal decoder

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

28 Digital Logic BIT

Q. Implement a full-adder circuit with a decoder and two OR gates.

Soln:
The truth table for full adder:

From the truth table

𝑆(𝐴, 𝐵, 𝐶𝑖𝑛 ) = ∑(1, 2, 4, 7)
𝐶 (𝐴, 𝐵, 𝐶𝑖𝑛 ) = ∑(3, 5, 6, 7)
Since there are three inputs and a total of eight minterms. So we need 3-to-8 line decoder.
The decoder generates the eight minterms for 𝐴, 𝐵 & 𝐶𝑖𝑛 . The OR gate for output sum (𝑆)
forms the sum of minterms 1, 2, 4 & 7. The OR gate for the output carry (𝐶) forms the sum
of minterms 3, 5, 6 & 7.

Fig: Full adder implementation with decoder

Encoder
An encoder is a combinational circuit that performs the inverse operation from that of
decoder. It has 2𝑛 input lines and 𝑛 output lines.
The output lines generate the binary code corresponding to the input value.

Fig: Block diagram of encoder

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

29 Digital Logic BIT

E.g. Octal to binary encoder which has 8 inputs and 3 outputs.

Truth table for octal to binary encoder:

Boolean function of output variables:

𝑋 = 𝐷4 + 𝐷5 + 𝐷6 + 𝐷7
𝑋 = 𝐷2 + 𝐷3 + 𝐷6 + 𝐷7
𝑋 = 𝐷1 + 𝐷3 + 𝐷5 + 𝐷7

Logic circuit:

Limitation: Only one input can be enabled at a time. If two inputs are enabled at the same
time, then output is undefined.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

30 Digital Logic BIT

Q. Design a 3 to 8 line decoder using two 2 to 4 line decoder and explain it.
Soln:

X
2×4
Y 𝐷0 − 𝐷3
Decoder
E

2×4
𝐷4 − 𝐷7
Decoder

Fig: 3 to 8 decoder using two 2 to 4 decoder

The figure shows two 2 × 4 decoder with enable input (E) connected to form a 3 × 8
decoder. When 𝐸 = 0, the top decoder is enabled and the other is disabled. The bottom
decoder outputs are all 0’s and the top four outputs generate minterms 000 to 001. When 𝐸 =
1, the enable conditions are reversed. The bottom decoder outputs generate minterms 100 to
111 while the outputs of the top decoder are all 0’s.

Q. Design a 2-to-4 line decoder using NAND gates.

Soln:

Truth table:
Inputs Outputs
A B 𝐷0 𝐷1 𝐷2 𝐷3 For the NAND decoder only one output can be
0 0 0 1 1 1 LOW and equal to logic ‘0’ at any given time
0 1 1 0 1 1 with all other outputs being HIGH at logic ‘1’.
1 0 1 1 0 1
1 1 1 1 1 0

Note: Similar method for 3-to-8 line decoder in which 3-lines of input are present and 8
output lines.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

31 Digital Logic BIT

Q. Using a decoder and external gates, design the combinational circuit defined by the
following three Boolean functions:
𝑭𝟏 = 𝒙′ 𝒚′ 𝒛 + 𝒙𝒛′
𝑭𝟐 = 𝒙′ 𝒚𝒛′ + 𝒙𝒚′
𝑭𝟑 = 𝒙𝒚𝒛′ + 𝒙𝒚
Soln:
Truth table:

Logic Diagram

Multiplexer (MUX)
- A multiplexer is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line.
- Multiplexing is the process of transmitting a large number of information over a single
line.
- The selection of a particular input lines is controlled by a set of selection lines. Normally
there are 2𝑛 input lines and 𝑛 selection lines whose bit combinations determine which
input is selected.
- A multiplexer is also called a data selector, since it selects one of many inputs and steers
the binary information to the output line.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

32 Digital Logic BIT

4-to-1 line Multiplexer:

Q. Design a 8-to-1 line multiplexer using lower order multiplexers and explain it.
Soln:

The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of
upper 4x1 Multiplexer are I0 to I3 and the data inputs of lower 4x1 Multiplexer are I 4 to I7.
Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines,
s1 & s0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

33 Digital Logic BIT

 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 0 to I3 based
on the values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 4 to I7 based
on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer performs
as one 8x1 Multiplexer.

Q. Implement the Boolean function 𝑭(𝑨, 𝑩, 𝑪) = ∑(𝟏, 𝟑, 𝟓, 𝟔) with multiplexer.

Soln:
The multiplexer can be implemented with 4 to 1 multiplexer.
Note: It is possible to generate n+1 variables with 2𝑛 to 1 mutiplexer.

Now, truth table for the given function is:

Now the implementation table is  If the minterms in a column are not circled, then
apply 0 to the corresponding multiplexer unit.
 If the 2 minterms are circled, then apply 1 to the
corresponding multiplexer unit.
 If the bottom minterm is circled, and top is not circled
then apply 𝐴 to the corresponding multiplexer unit.
 If the top minterm is circled, and bottom is not circled
then apply 𝐴′ to the corresponding multiplexer unit.
Multiplexer implementation:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

34 Digital Logic BIT

Q. Implement the Boolean function 𝑭(𝑨, 𝑩, 𝑪, 𝑫) = ∑(𝟎, 𝟏, 𝟑, 𝟒, 𝟖, 𝟗, 𝟏𝟓) by multiplexer.

Soln:
This function can be implemented with 8 to 1 MUX.
The truth table for the function is
Minterm A B C D F
0 0 0 0 0 1
1 0 0 0 1 1
2 0 0 1 0 0
3 0 0 1 1 1
4 0 1 0 0 1
5 0 1 0 1 0
6 0 1 1 0 0
7 0 1 1 1 0
8 1 0 0 0 1
9 1 0 0 1 1
10 1 0 1 0 0
11 1 0 1 1 0
12 1 1 0 0 0
13 1 1 0 1 0
14 1 1 1 0 0
15 1 1 1 1 1

Now the implementation table and multiplexer implementation are given below:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

35 Digital Logic BIT

Demultiplexer (DEMUX)
- A decoder with an enable input can function as a de-multiplexer.
- A de-multiplexer is a circuit that receives information on a single line and transmit this
information on one of 2𝑛 possible output lines. The selection for particular output line is
controlled by the bit values of 𝑛 selection lines.

Fig: A 2-to-4 line decoder with enable (E) input

The decoder of fig can function as a de-multiplexer if the 𝐸 line is taken as a data input line
and lines A and B are taken as the selection lines.

1 to 4 DEMUX:
The 1:4 Demux consists of 1 data input bit, 2 control bits and 4 output bits. I is the input bit,
Y0, Y1, Y2, Y3 are the four output bits and S0 and S1 are the control bits.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

36 Digital Logic BIT

1 to 8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-Multiplexer:

The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs of
upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y3 to
Y0.
The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one of the four
outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of selection
lines s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper 1x4 De-Multiplexer
will be equal to input, I based on the values of selection lines s1 & s0.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

37 Digital Logic BIT

MUX-DEMUX Application Example

- This enables sharing a single communication line among a number of devices.

- At any time, only one source and one destination can use the communication line.

Read Only Memory (ROM)

- A read-only memory (ROM) is a device that includes both the decoder and the OR
gates within a single IC package. The connections between the outputs of the decoder
and the inputs of the OR gates can be specified for each particular configuration by
“programming” the ROM.
- A ROM is essentially a memory (or storage) device in which a fixed set of binary
information is stored.
- The binary information must first be specified by the user and is then embedded in the
unit to form the required interconnection pattern. ROM’s come with special internal links
that can be fused or broken. The desired interconnection for a particular application
requires that certain links be fused to form the required circuit paths. Once a pattern is
established for a ROM, it remain fixed even when power is turned off and then on again.
- A ROM consists of 𝑛 input lines and 𝑚 output lines. 
- Each bit combination of input variables is called an address.
- Each bit combination that comes out of the output lines is called a word. The number of
bits per word is equal to the number of output lines m.
- A ROM with n input lines has 2𝑛 distinct addresses, so there are 2𝑛 distinct words which
are said to be stored in the unit.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

38 Digital Logic BIT

 Internally, the ROM is a combinational circuit with AND gates connected as a decoder
and a number of OR gates equal to the number of outputs in the unit.

Combinational Logic implementation of ROM:

When a combinational circuit is implemented by means of ROM the function must be
expressed in sum of min terms or better yet by a truth table.

Q. Implement the following combinational logic function with a 4X2 ROM.

Soln:
Truth table specifies a combinational circuit with 2 inputs and 2 outputs. The Boolean
function can be represented in SOP as;

Combinational-circuit implementation with a 4 x 2 ROM:

ROM with AND-OR gates ROM with AND-OR-INVERT gates

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

39 Digital Logic BIT

Q. Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and
generates an output binary number equal to the square of the input number.
Soln:
First step is to derive the truth table for the combinational circuit

Output B0 is always equal to input A0; so there is no need to generate B0 with a ROM since it
is equal to an input variable. Moreover, output B1 is always 0, so this outputs is always
known.
Implementation by ROM:

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

40 Digital Logic BIT

Types of ROM:
1. Mask ROM
- Permanent programming done at fabrication time
- Fabrication take place at factory as per customer order
- Very expensive and therefore feasible only for large quantity orders
- Once the memory is programmed during the manufacturing process, the user cannot
alter the programs.
2. PROM (Programmable ROM)
- A blank chip which can be programmed only once using a special device called
programmer.
- Once it’s programmed its content cannot be modified or erased.
3. EPROM (Erasable Programmable ROM)
- Can be programmed multiple times.
- Its content can be erased by using UV (ultra violet) light.
- Exposure to the UV light will erase all contents.
4. EEPROM (Electrically Erasable Programmable ROM)
- Similar to EPROM but its contents can be electrically erased and re-written without
having to remove it from the computer.

Programmable Logic Array (PLA)

A combinational circuit may occasionally have don’t care conditions. When implemented
with a ROM, a don’t care condition becomes an address input that will never occur. The
words at the don’t care addresses need not be programmed and may be left in their original
state (all 0’s or all 1’s). The result is that not all the bit patterns available in the ROM are
used, which may be considered as waste of available equipment.
For example, a combinational circuit that converts a 12-bit card code to a 6-bit internal
alphanumeric code.
* It consists 12 inputs and 6 outputs. The size of the ROM must be 4096 × 6 (212 × 6).
* There are only 47 valid entries for the card code, all other input combinations are don’t
care. The remaining 4049 words of ROM are not used and are thus wasted.

So, Programmable Logic Array is a LSI component that can be used in economically as an
alternative to ROM where number of don’t-care conditions is excessive.

 PLA does not provide full decoding of the variables and does not generate all the
minterms as in the ROM.

Block diagram of PLA:

A block diagram is shown in fig. It consists 𝑛 inputs, 𝑚-outputs, 𝑘 product terms and 𝑚 sum
terms. The product terms constitute a group of 𝑘 AND gates and the sum terms constitute a
group of 𝑚 OR gates.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

41 Digital Logic BIT

 The number of programmed links is 𝟐𝒏 × 𝒌 + 𝒌 × 𝒎 + 𝒎, whereas that of a ROM is

𝟐𝒏 × 𝒎 .

Implementation of combinational circuit by PLA:

PLA program table:

Input side:
1=uncomplemented in term
0=complemented in term
- = does not participate
Output side:
1= term connected to output
- = no connection to output

PLA Logic Circuit:

Fig: PLA with 3 inputs, 3 product terms, and 2 outputs

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

42 Digital Logic BIT

PLA program table consists of three columns:

- First column: lists the product terms numerically.
- Second column: specifies the required paths between inputs and AND gates.
- Third column: specifies the paths between the AND gates and the OR gates.
Under each output variable, we write a T (for true) if the output inverter is to be bypassed,
and C (for complement) if the function is to be complemented with the output inverter.

Note: PLA implements the functions in their sum of products form (standard form, not
necessarily canonical as with ROM). Each product term in the expression requires an AND
gate. It is necessary to simplify the function to a minimum number of product terms in order
to minimize the number of AND gates used.

Q. A combinational circuit is defined by the functions:

𝑭𝟏 (𝑨, 𝑩, 𝑪) = ∑(𝟑, 𝟓, 𝟔, 𝟕)
𝑭𝟐 (𝑨, 𝑩, 𝑪) = ∑(𝟎, 𝟐, 𝟒, 𝟕)
Implement the circuit with a PLA having three inputs, four product terms, and two outputs.
Soln:
First of all we have to write the function in minimize SOP form:

There are six product terms in 𝐹1 and 𝐹2 , but only four product terms are allowed to use.
Now implement 𝐹1′ (𝐴, 𝐵, 𝐶)
𝐹1′ (𝐴, 𝐵, 𝐶 ) = ∑(0, 1, 2, 4)
𝐹2 (𝐴, 𝐵, 𝐶 ) = ∑(0, 2, 4, 7)
From these equation it is clear that the minterms 0, 2 and 4 are common.
Now obtain the minimized expression by using them

Now four product terms are 𝐵′ 𝐶 ′ , 𝐴′ 𝐶 ′ , 𝐴′ 𝐵′ 𝑎𝑛𝑑 𝐴𝐵𝐶.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

43 Digital Logic BIT

𝐹1 = 𝐵′ 𝐶 ′ + 𝐴′ 𝐶 ′ + 𝐴′ 𝐵′
𝐹2 = 𝐵′ 𝐶 ′ + 𝐴𝐵𝐶 + 𝐴′ 𝐶 ′

Now, PLA program table:

Note that output 𝐹1 is the normal (or true) output even though a C is marked under it. This is
because 𝐹1′ is generated prior to the output inverter. The inverter complements the function to
produce 𝐹1 in the
output.
Draw PLA circuit yourself.

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel

44 Digital Logic BIT

Reference:

M. Morris Mano, “Digital Logic & Computer Design”

https://collegenote.pythonanywhere.com Prepared By: Jayanta Poudel