Lesson Combinational Logic (arithmetic)

Points to Remember on Combinational Logic Circuit:

 Output depends upon the combination of inputs.

 Output is pure function of present inputs only i.e., Previous State inputs won’t have any effect
on the output. Also, It doesn’t use memory.
 In other words,

OUTPUT=f(INPUT)

 Inputs are called Excitation from circuits and outputs are called Response of combinational
logic circuits.

Classification of Combinational Logic Circuits:

1. Arithmetic:

 Adders
 Subtractors
 Multipliers
 Comparators

2. Data Handling:

 Multiplexers
 DeMultiplexers
 Encoders and Decoders

3. Code Converters:

 BCD to Excess-3 code and vice versa

 BCD to Gray code and vice versa
 Seven Segment

Design of Half Adders and Full Adders:

 A combinational logic circuit that performs the addition of two single bits is called Half Adder.
 A combinational logic circuit that performs the addition of three single bits is called Full
Adder.
 Adder circuit is a combinational digital circuit that is used for adding two numbers.
A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C)
as the output. Typically adders are realized for adding binary numbers but they can be
also realized for adding other formats like BCD (binary coded decimal, XS-3 etc. Besides
addition, adder circuits can be used for a lot of other applications in digital electronics
like address decoding, table index calculation etc. Adder circuits are of two types: Half
adder ad Full adder.

Half adder is a combinational arithmetic circuit that adds two numbers and
produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then
sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From
this it is clear that a half adder circuit can be easily constructed using one X-OR gate and
one AND gate. Half adder is the simplest of all adder circuit, but it has a major
disadvantage. The half adder can add only two input bits (A and B) and has nothing to
do with the carry if there is any in the input. So if the input to a half adder have a carry,
then it will be neglected it and adds only the A and B bits. That means the binary addition
process is not complete and that’s why it is called a half adder. The truth table, schematic
representation and XOR//AND realization of a half adder are shown in the figure below.

NAND gates or NOR gates can be used for realizing the half adder in universal logic and
the relevant circuit diagrams are shown in the figure below.
 Let us observe the addition of single bits,

0+0=0
0+1=1
1+0=1
1+1=10

Since 1+1=10, the result must be two bit output. So, Above can be rewritten as,

0+0=00
0+1=01
1+0=01
1+1=10

The result of 1+1 is 10, where ‘1’ is carry-output (Cout) and ‘0’ is Sum-output (Normal
Output).

Half Adder and Full Adder Using K-Map

Even the sum and carry outputs for half adder can also be obtained with the method of
Karnaugh map (K-map). The half adder K-map is

Limitations:
Adding of Carry is not possible in Half adder.
  To overcome the above limitation faced with Half adders, Full Adders are implemented.
 It is a arithmetic combinational logic circuit that performs addition of three single bits.
 It contains three inputs (A, B, Cin) and produces two outputs (Sum and Cout).
 Where, Cin -> Carry In and Cout -> Carry Out

K-map Simplification for output variable Sum

The full adder K-Map is

The equation obtained is,

S = A'B'Cin + AB'Cin' + ABC + A'BCin'

The equation can be simplified as,

S = B'(A'Cin+ACin') + B(AC + A'Cin'

S = B'(A xor Cin) + B (A xor Cin)'
S = A xor B xor Cin
3. Half Subtractor:

 It is a combinational logic circuit designed to perform subtraction of two single bits.

 It contains two inputs (A and B) and produces two outputs (Difference and Borrow-output).

Truth Table of Half Subtractor:

K-map Simplification for output variable ‘D’ :

The equation obtained is,

D = A'B + AB'
which can be logically written as,
D = A xor B

K-map Simplification for output variable ‘B out‘ :

The equation obtained from above K-map is,

Bout = A'B

Logic Diagram of Half Subtractor:

4. Full Subtractor:

 It is a Combinational logic circuit designed to perform subtraction of three single bits.

 It contains three inputs(A, B, Bin) and produces two outputs (D,
 Bout).
 Where, A and B are called Minuend and Subtrahend bits.
 And, Bin -> Borrow-In and Bout -> Borrow-Out

Truth Table of Full Subtractor:

K-map Simplification for output variable ‘D’ :

The equation obtained from above K-map is,

 D = A'B'Bin + AB'Bin' + ABBin + A'BBin'

which can be simplified as,

D = B'(A'Bin + ABin') + B(ABin + A'Bin')

D = B'(A xor Bin) + B(A xor Bin)'
D = A xor B xor Bin

K-map Simplification for output variable ‘Bout‘ :

The equation obtained is,

Bout = BBin + A'B + A'Bin

Logic Diagram of Full Subtractor:

Applications:

1. For performing arithmetic calculations in electronic calculators and other digital devices.
2. In Timers and Program Counters.
3. Useful in Digital Signal Processing