ABSTRACT

This project focuses on the design and implementation of a 4-bit Arithmetic

Logic Unit (ALU) to perform addition, subtraction, comparison, and AND
operations, with a particular emphasis on estimating its critical path and
maximum delay. ALU is constructed using Verilog HDL to model its hardware
behaviour and functionality. NG Spice simulator is employed for
comprehensive testing and verification of the designed ALU prior to hardware
implementation. Hardware restrictions have necessitated the prototype to be
limited to two 4-bit operands.To achieve the desired operational flexibility
within the ALU, independent functional blocks are employed for each
arithmetic or logical operation. These blocks are selectively activated based on
opcode decoding, ensuring efficient resource utilization and adaptable
functionality.

Keywords: Testability, Power Optimization, Technology Scaling

Signature of HoD Signature of Guide

Dr. B. Rama Rao S Dr. PENDYALAV.MURALIDHAR

M. Tech, Ph.D., SIMEEE, MISTE, MIETE M. Tech, Ph.D.
Professor & Head of the Department , Asso.professor
Department of ECE, AITAM Department of ECE, AITAM

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 CONTENTS

S.no Title Page.no

Introduction
1 3-5

2 Literature survey
6-7

3 Problem statement
8

4 Proposed model
9-10

5 References
11

2
 INTRODUCTION

Block Diagram:

1.ALU-Block:
Here ALU block acts as router to out computational circuit. The operations that needed to
be done by ALU is as follows

S1 S0 operation
0 0 Add
0 1 Subtract
1 0 Compare
1 1 And

To establish this, we can use a 2-4 decoder.

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The enables for the following circuits are as follows; D0 – Adder; D1 – Subtractor; D2 –
Comparator; D3 – And

2.Enable Block:
This is made-up of 8 AND gates whose main purpose is send our values A3A2A1A1,
B3B2B1B0 to their respective block if enable is 1 else 0.

3.Adder/Subtractor:
Here instead of making a separate Adder and Subtractor we can use a single block which can
both act as adder and subtractor. So here we can tie out C0/M wite to S0 directly which
would give us an ADDER if input is 00 and a SUBTRACTOR if out input is 01.

1.Adder operation is A3A2A1A1+ B3B2B1B0

2.Subtractor operation is A3A2A1A1- B3B2B1B0

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4.Comparator:
This block would compare our 4-Bit number and give result whether A3A2A1A1 is
greater than or less than or equal to B3B2B1B0.

5.AND Block:
This block Performs AND operation on A3&B3; A0&B0; A1&B1; A0&B0.

Combining all these blocks would give us our ALU.

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 LITERATURE SURVEY

Author name Title Result

S.no

David Harris and Digital Design and It provides

1
Sarah Harris(2015) Computer comprehensive
Architecture coverage of ALU
design principles and
implementation
techniques

Sachin Sapatnekar Timing Analysis and It tells the timing

2
(2013) Optimization for Analysis and
VLSI Circuits Optimization for
VLSI Circuits

Samir Palnitkar Verilog HDL: A It is widely used

3
(2003) Guide to Digital textbook for learning
Design and Verilog syntax and
Synthesis design techniques.

4 Andrei Vladimirescu The Spice Book It is a comprehensive

(2010) reference for SPICE-
based circuit
simulation, including
Ngspice.

6
 5 James O. Hamblen, Rapid Prototyping of It discusses
Michael D. Furman, Digital Systems hardware
and Donald P. prototyping
Egan(2008) strategies and
techniques

6 A. S. Mahajan, S. S. Design and It presents a

Patil, and P. S. Implementation of 4- Verilog-based ALU
Waykole(2015) Bit ALU Using design with critical
Verilog HDL path analysis.

 Design and Implementation of 4-Bit ALU Using Verilog HDL" by A. S. Mahajan, S.

S. Patil, and P. S. Waykole (2015) presents a Verilog-based ALU design with critical
path analysis.

 "Performance Analysis of 4-Bit ALU Using Different Simulation Tools" by S. S.

Ghumbre, S. S. Shelke, and S. S. Sanas (2016) compares simulation results of a 4-bit
ALU using multiple simulators, including NGspice.

 " Implementation of 4-Bit ALU Using Verilog" by A. S. Mahajan, S. S. Patil, and P.

S. Waykole (2014) demonstrates FPGA-based prototyping of a 4-bit ALU.

 "Circuit Simulation with SPICE OPUS" by John Keown (2013) covers NGspice
usage for circuit analysis and verification.
 Verilog Quickstart: A Practical Guide to Simulation and Synthesis" by James O.
Hamblen (2017) offers a concise introduction to Verilog for beginners.

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 PROBLEM STATEMENT
The carry signal in a full adder is generated based on the inputs and the carry from the
previous stage. If there are multiple full adders cascaded in a system, this dependency can
lead to increased overall propagation delay, affecting the speed of arithmetic operations. This
delay becomes more prominent as the number of stages in the adder increases, impacting the
overall performance of the addition operation in terms of speed.While Carry Look-Ahead
Adders (CLA) offer improved speed compared to ripple carry adders, they come with certain
drawbacks. One significant drawback is the increased hardware complexity. CLA requires
additional logic gates for the generation of lookahead carries, leading to a larger and more
intricate circuit design. This complexity can result in higher power consumption, increased
area on the integrated circuit, and potentially slower carry lookahead signal calculation for
larger word sizes.

Design Requirements:

 Verilog HDL Implementation: The ALU's hardware behavior and functionality must
be modeled using Verilog HDL.

 Independent Functional Blocks: Separate blocks for each operation

(addition, subtraction, comparison, AND) are required for flexibility and resource
optimization.

 Opcode Decoding: The selection of the appropriate functional block should be

controlled by a versatile opcode decoding mechanism.

 Critical Path Analysis: The ALU's critical path and maximum delay must be
accurately estimated to assess its performance and identify potential bottlenecks.

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 PROPSAL MODEL
Develop a Carry Look-Ahead Adder (CLA) capable of efficiently performing
binary addition in digital circuits. The goal is to design an adder that reduces the
propagation delay associated with carry generation, enabling faster
computation.The CLA should optimize for minimal critical path delay, efficient
use of hardware resources, and scalability of logic gates, while considering
factors such as power consumption and overall performance of adder circuit
which offers efficient ALU design.

Design and implement a 4-bit ALU capable of performing

addition, subtraction, comparison, and AND operations..Estimate the critical
path and maximum delay within the circuit.Develop a Verilog HDL model for
simulation and verification.Utilize NGspice simulator for functional testing and
timing analysis.Construct a hardware prototype with two 4-bit operands within
hardware constraints.Implement independent functional blocks for flexibility
and modularity.Employ opcode decoding to select desired operations .

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Internal working of ALU

ADDER

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 REFERENCES
G. Karthik Reddy, “Low Power-Area Pass Transistor Logic Based ALU Design
Using Low Power Full Adder Design, ” IEEE Sponsored 9th (ISCO), 2015
References for VHDL coding and alu designing for 4bit addition, subtraction,
comparator, AND logic gate https://allaboutfpga.com/vhdl-code-for-4-bit-alu/
References for ng spice software coding for simulating and testing
https://ngspice.sourceforge.io/ngspice-control-language-
tutorial.html#:~:text=You%20start%20ngspice%20by%20ngspice,saving%20th
e%20data%20etc.).

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