ANNA UNIVERSITY REGIONAL CAMPUS COIMBATORE

COIMBATORE – 641046.

DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

BONAFIDE CERTI FICATE

LABORATORY RECORD

EE3022 - VLSI DESIGN

Name (In Capital letters) : Mr./Ms.

University Exam. Regn. No. :
Branch : Electrical and Electronics Engineering
Year/Semester : 4TH Year / 7th Semester

Certified that bonafide record of work done by Mr./Ms.

Staff-in-charge Head of the Department

Submitted for the Anna University Practical Examination for the subject titled

held on

Internal Examiner External Examiner

S.NO NAME OF THE EXPERIMENT DATE OF PAGE NO SIGNATURE
SUBMISSION
SIMULATION DIAGRAM

SIMULATION OUTPUT

1
 EXP.NO: 1

IMPLEMENTATION OF CARRY LOOK AHEAD ADDER WITH FPGA

DATE:

AIM

APPARATUS REQUIRED

S.No SOFTWARE REQUIRED Quality

1 PC with windows 1

2 Quartus project Navigator 1

THEORY

The adder produce carry propagation delay while performing other arithmetic operations
like multiplication and divisions as it uses several additions or subtraction steps. This is a
major problem for the adder and hence improving the speed of addition will improve the
speed of all other arithmetic operations. Hence reducing the carry propagation delay of
adders is of great importance. There are different logic design approaches that have been
employed to overcome the carry propagation problem. One widely used approach is to
employ a carry look-ahead which solves this problem by calculating the carry signals in
advance, based on the input signals. This type of adder circuit is called a carry look-ahead
adder.

PROCEDURE

1. Setting Up Your FPGA Project

1. Open Quartus II software to create New project file . Go to File> New Project Wizard
2. Specify a working directory and project name (e.g., CLA_Adder).
3. Set the top-level entity name (e.g., CarryLookaheadAdder).
4. Choose your target FPGA device family and model.
5. Writing the Verilog HDL code and Save the file using .v extension
6. Add the Design File to the Project. Go to Assignments > Settings > Files.

2
PROGRAM

module CarryLookaheadAdder (

input [3:0] A, // 4-bit input A

input [3:0] B, // 4-bit input B

input Cin, // Carry input

output [3:0] Sum, // 4-bit Sum output

output Cout // Carry output

);

wire [3:0] P; // Propagate

wire [3:0] G; // Generate

wire [4:0] C; // Carry signals (C0 = Cin)

assign C[0] = Cin;

// Propagate and Generate terms

assign P = A ^ B; // Propagate = A XOR B

assign G = A & B; // Generate = A AND B

// Carry lookahead logic

assign C[1] = G[0] | (P[0] & C[0]);

assign C[2] = G[1] | (P[1] & G[0]) | (P[1] & P[0] & C[0]);

assign C[3] = G[2] | (P[2] & G[1]) | (P[2] & P[1] & G[0]) | (P[2] & P[1] & P[0] & C[0]);

assign C[4] = G[3] | (P[3] & G[2]) | (P[3] & P[2] & G[1]) | (P[3] & P[2] & P[1] & G[0]) |

(P[3] & P[2] & P[1] & P[0] & C[0]);

// Sum outputs

assign Sum = P ^ C[3:0]; // Sum = Propagate XOR Carry

// Final carry-out

assign Cout = C[4];

endmodule

7.Assign Pin Locations

3
 Define FPGA I/O Pins:

o Assign pins for inputs (A[3:0], B[3:0], Cin) and outputs (Sum[3:0], Cout) based on your FPGA
board's pin configuration.
o Open Assignments > Pin Planner and map the signals to physical pins.
o For example:
▪ A[3:0] → PIN_1, PIN_2, PIN_3, PIN_4
▪ B[3:0] → PIN_5, PIN_6, PIN_7, PIN_8
▪ Cin → PIN_9
▪ Sum[3:0] → PIN_10, PIN_11, PIN_12, PIN_13
▪ Cout → PIN_14
o Refer to the FPGA development board's user manual for the exact pin mappings.

8. Compile the Design and Simulate the Design Go to Tools > Simulation > RTL Simulation. Create a
test bench to verify the functionality of the CLA. Run the simulation to verify the correctness of the adder.

9.Connect your FPGA board to your computer via USB. Go to Tools > Programmer.

10. Select the programming hardware (e.g., USB Blaster). Add the .sof file generated during compilation and
Click Start to program the FPGA.

LOGIC DIAGRAM

RESULT

4
SIMULATION DIAGRAM

SIMULATION OUTPUT

PROGRAM

module alu(
input [2:0]opcode,
input [7:0]OperandA,OperandB,
output reg [7:0]result
);
always @(*)begin
case(instruction)
3'b000: result = OperandA + B;

5
 EXP.NO: 2

IMPLEMENTATION OF ALU WITH FPGA

DATE

AIM

APPARATUS REQUIRED

S.No SOFTWARE REQUIRED Quality

1 PC with windows 1

2 Quartus project Navigator 1

THEORY

The arithmetic and Logical Unit(ALU) is the digital circuit used by the processor for
performing various arithmetic and logical operations like addition, subtraction, logical AND
operation etc. It may have one or more than one operand and an opcode. The opcode will tell
the ALU which operations to perform. If the processor is n-bit then ALU will perform the
operation on n-bit operand. The length of the opcode given to the ALU will decide at maximum
how much ALU can perform operations.

PROCEDURE
• Create a new project in your FPGA design software and specify the working directory and project
name.
• Select the target FPGA device based on your board's specifications.
• Write the Verilog HDL code for the ALU, defining operations such as addition, subtraction, AND,
OR, and XOR based on a control signal.
• Save the code with a .v extension and add it to your project.
• Assign the FPGA I/O pins for inputs, outputs, and control signals using the Pin Planner tool.
• Refer to the FPGA board’s documentation for the correct pin mappings.
• Compile the design to generate a configuration file and fix any syntax or design errors that appear
during synthesis or fitting.

6
3'b001: result = OperandA - B;
3'b010: result = OperandA / B;
3'b011: result = OperandA * B;
3'b100: result = OperandA & B;
3'b101: result = OperandA | B;
3'b110: result = ~OperandA;
3'b111: result = OperandA ^ OperandA;

default:
result = 0;
endcase
end
endmodule
ALU TEST BENCH CODE
module alu_tb;
reg [2:0]instruction;
reg [7:0]A,B;
wire [7:0]result;
alu uut(instruction,A,B,result);
integer i;
initial begin
A = 50; B = 10; instruction = 0;
for(i = 1; i < 8; i = i+ 1)begin
#10
instruction = i;
end
#10
$finish();
end
endmodule

7
 • Create a testbench to verify the functionality of the ALU by simulating the design.
• Apply test inputs and control signals to confirm the ALU's outputs match the expected results for
each operation.
• Connect your FPGA board to the computer via USB, configure the programmer, and upload the
design using the generated configuration file.
• Test the ALU on the FPGA by applying inputs through switches or other input mechanisms and
observing outputs via LEDs or a logic analyzer.
• Debug as necessary, checking the design code, pin mappings, and simulation results.
• Iterate until the ALU performs as expected.

LOGICAL DIAGRAM

RESULT

8
TRUTH TABLE

AND GATE
EQUATION LOGICSYMBOL TRUTHTABLE
in1 in2 out
0 0 0

out=in1&in2 0 1 0
1 0 0
1 1 1

OUTPUT – AND GATE

TRUTH TABLE

OR GATE
EQUATION LOGICSYMBOL TRUTHTABLE
in1 in2 out
0 0 0
out=in1|in2 0 1 1
1 0 1
1 1 1
OUTPUT- OR GATE

9
 EXP.NO:3

STRUCTURAL MODELLING OF BASIC LOGICAL GATES

DATE:

AIM

APPARATUS REQUIRED

S.No SOFTWARE REQUIRED Quality

1 PC with windows 1

2 Quartus project Navigator 1

THEORY

AND GATE : The output of an AND gate is true only when all of the inputs are true. If one
or more of an AND gate's inputs are false, then the output of the AND gate is false.

OR GATE :. The output of an OR gate is true when one or more of its inputs are true. If all
of an OR gate's inputs are false, then the output of the OR gate is false.

NOT GATE :NOT gate is logic gate that gives a negative mathematical output. Hence it is
also called an Inverter. That means it gives False when input is True and True when the input
is False.

10
TRUTH TABLE – NOT GATE

EQUATION LOGICSYMBOL TRUTHTABLE

A Y
Y=~a 0 1
1 0

OUTPUT – NOT GATE

PROGRAM

input wire B,
module AND_Gate (
output wire Y );
input wire A,
or u1 (Y, A, B);
input wire B,
endmodule
output wire Y
NOT GATE
);
module NOT_gate (
and u1 (Y, A, B);
input wire A,
endmodule
output wire Y
OR GATE
)
module OR_Gate (
not (Y, A);
input wire A,
endmodule

11
PROCEDURE
Create individual modules for each gate with appropriate input and output ports (e.g., A, B for inputs and
Y for output in AND/OR, and A for input and Y for output in NOT).
Implement Gate Logic: Use Verilog operators (& for AND, | for OR, ~ for NOT) in assign statements to
define the functionality of each gate.
Combine Modules (Optional): If desired, create a top-level module to instantiate the individual gates
and test them together.
Simulate and Verify: Write a testbench to apply various input combinations, simulate in Quartus, and
verify the outputs using waveform analysis.

RESULT

12
TRUTH TABLE – NAND GATE

EQUATION LOGICSYMBOL TRUTHTABLE

in1 in2 out
0 0 1
out=~(in1&in2) 0 1 1
1 0 1
1 1 0

OUTPUT – NAND GATE

TRUTH TABLE – NOR GATE

EQUATION LOGICSYMBOL TRUTHTABLE

in1 in2 out
0 0 1
out=~(in1|in2)
0 1 0
1 0 0
1 1 0
OUTPUT – NOR GATE

13
 EXP NO:4

BEHAVIOURAL MODELLING OF BASIC LOGICAL GATES

DATE

AIM

APPARATUS REQUIRED
S.No SOFTWARE REQUIRED Quality

1 PC with windows 1

2 Quartus project Navigator 1

THEORY
NAND GATE : a digital logic gate with two or more inputs and one output with behaviour
that is the opposite of an AND gate. The output of a NAND gate is true when one or more,
but not all, of its inputs are false. If all of a NAND gate's inputs are true, then the output
of the NAND gate is false.

NOR GATE : a digital logic gatewith two or more inputs and one output with
behaviour that is the opposite of an OR gate. The output of a NOR gate is true all of its
inputs are false. If one or more of a NOR gate's inputs are true, then the output of the
NOR gate is false.

EX-OR GATE : a digital logic gate with two or more inputs and one output that
performs exclusive disjunction. The output of an XOR gate is true only when exactly one
of its inputs is true. If both of an XOR gate's inputs are false, or if both of its inputs are
true, then the output of the XOR gate is false.

14
TRUTH TABLE – EX-OR GATE
EQUATION LOGICSYMBOL TRUTHTABLE
in1 in2 out
0 0 0
out=in1^in2
0 1 1
1 0 1
1 1 0

OUTPUT – EX-OR GATE

PROGRAM

NAND GATE );
module nand_gate( always @(*) begin
input wire A, NOR_out = ~(A | B);
input wire B, end
output reg NAND_out endmodule
);
always @(*) begin EX-OR GATE
NAND_out = ~(A & B); module xor_gate(
end input wire A, // Input A
endmodule input wire B, // Input B
output reg XOR_out // XOR gate output
NOR GATE );
module nor_gate( always @(*) begin
input wire A, XOR_out = A ^ B; // XOR gate logic
input wire B, end
output reg NOR_out endmodule

15
PROCEDURE • Create separate modules for each gate

with appropriate input and output ports (e.g., A, B for inputs and Y for output).
• Write Gate Logic: Use Verilog operators (~& for NAND, ~| for NOR, ^ for XOR) to
describe the behavior of each gate in an assign statement.
• Combine Modules (Optional): If needed, integrate the individual gate modules into a
single module with separate outputs for NAND, NOR, and EXOR gates.
• Simulate and Test: Write a testbench to apply various input combinations, simulate in
Quartus, and verify the outputs using waveforms or simulation logs.

RESULT :

16
4-BIT FULL ADDER- LOGIC
DIAGRAM:

TRUTH TABLE:

a b c Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

OUTPUT

17
EXP.NO:5

IMPLEMENTATION OF COMBINATIONAL DIGITAL LOGIC

DATE
WITH FPGA

AIM

APPARATUS REQUIRED
S.No SOFTWARE REQUIRED Quantity

1. PC with windows 1

2. Quartus project Navigator 1

3. FPGA Cyclone-III Altera DE0 Boards 1

THEORY
4-BIT FULL ADDER
A 4-bit full adder is a combination of four full adders, each handling the addition of single
bits. It takes two 4-bit binary numbers and adds them together, including a carry input from
the previous lower bit addition.

4-BIT FULL SUBTRACTOR

A 4-bit full subtractor is a combination of four full subtractors, each capable of subtracting
single-bit binary numbers. It takes two 4-bit binary numbers and performs the subtraction,
considering borrow inputs from the previous lower bit subtraction.

18
4-BIT FULL SUBTRACTOR -LOGIC DIAGRAM

TRUTH TABLE:

OUTPUT

19
PROCEDURE
1. Create a Verilog module with inputs (A[3:0], B[3:0], Cin) and outputs (Sum[3:0],
Cout) for the adder, and (A[3:0], B[3:0]) and output (Diff[3:0], Borrow) for the
subtractor.
2. Use the assign statement or behavioral logic to implement the 4-bit addition by
cascading full adders with Cin and propagate Cout.
3. Implement the subtraction using bitwise logic (A - B) or as an addition of A and ~B
with borrow handling.
4. Combine both designs into a single module if needed, with a mode selection input for
operation (add/subtract) and write a testbench to simulate.
5. Compile in Quartus, synthesize the design for FPGA, and verify using waveform
analysis or hardware testing.

20
PROGRAM full_subtractor FS1 (.A(A[1]),
.B(B[1]), .Bin(B1), .Diff(Diff[1]),
4-BIT FULL ADDER
.Bout(B2));
module full_adder_4bit(
full_subtractor FS2 (.A(A[2]),
input [3:0] A,
.B(B[2]), .Bin(B2), .Diff(Diff[2]),
input [3:0] B,
.Bout(B3));
input Cin,
full_subtractor FS3 (.A(A[3]),
output [3:0] Sum,
.B(B[3]), .Bin(B3), .Diff(Diff[3]),
output Cout
.Bout(Bout));
);
endmodule
wire C1, C2, C3;
full_adder FA0 (.A(A[0]),
.B(B[0]), .Cin(Cin), .Sum(Sum[0]),
.Cout(C1));
full_adder FA1 (.A(A[1]),
.B(B[1]), .Cin(C1), .Sum(Sum[1]),
.Cout(C2));
full_adder FA2 (.A(A[2]),
.B(B[2]), .Cin(C2), .Sum(Sum[2]),
.Cout(C3));
full_adder FA3 (.A(A[3]),
.B(B[3]), .Cin(C3), .Sum(Sum[3]),
.Cout(Cout));
endmodule

4-BIT FULL SUBTRACTOR

module full_subtractor_4bit(
input [3:0] A,
input [3:0] B,
input Bin,
output [3:0] Diff,
output Bout
);
wire B1, B2, B3;
full_subtractor FS0 (.A(A[0]),
.B(B[0]), .Bin(Bin), .Diff(Diff[0]),
.Bout(B1));

21
RESULT:

22
JK FLIP FLOP: LOGIC DIAGRAM

TRUTH TABLE:
Inputs Outputs
Comments
clk j k q qbar
1 0 0 Qn Qn` No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 Qn Qn Toggle

OUTPUT:

23
EXP NO:6

IMPLEMENTATION OF SEQUENTIAL DIGITAL LOGIC WITH

DATE FPGA

AIM

APPARATUS REQUIRED
S.No SOFTWARE REQUIRED Quantity

1. PC with windows 1

2. Quartus project Navigator 1

3. FPGA Cyclone-III Altera DE0 Boards 1

THEORY
A JK flip-flop is a type of sequential logic circuit that serves as a memory
element, storing one bit of data. It has two inputs, labeled J and K, along with a
clock input and two outputs: Q and Q' (the inverse of Q). The JK flip-flop is a
versatile flip-flop, as it can operate in various modes depending on the values of
J and K. When J = K = 0, the state remains unchanged. When J = 0 and K = 1,
the output resets (Q = 0). When J = 1 and K = 0, the output sets (Q = 1). When
both J and K are 1, the flip-flop toggles its state. It is widely used in digital circuits
for timing and control operations.

24
PROGRAM if (RESET)
Q <= 0;
module jk_flip_flop(
else begin
input J,
case ({J, K})
input K,
2'b00: Q <= Q;
input CLK,
2'b01: Q <= 0;
input RESET,
2'b10: Q <= 1;
output reg Q,
2'b11: Q <= ~Q;
output Qn
endcase
);
end
assign Qn = ~Q;
end
always @(posedge CLK or
endmodule
posedge RESET) begin

25
PROCEDURE

• Start by declaring the module with inputs (J, K, clk, reset) and outputs (Q,
Qn).
• Use an always block sensitive to the clock and reset, defining state
transitions based on J and K values.
• Include logic for asynchronous or synchronous reset to initialize the output
states.
• Compile the code in Quartus, simulate the design, and verify the
functionality using test bench waveforms

RESULT :

26
 LOGIC DIAGRAM- NOT GATE LOGIC GATE- NAND GATE

CMOS DESIGN DIAGRAM

CMOS DESIGN DIAGRAM

TRUTH TABLE TRUTH TABLE

27
 EXP.NO:7

DATE: CMOS BASED LOGIC CIRCUIT SIMULATION

AIM

APPARATUS REQUIRED

S.No SOFTWARE REQUIRED Quality

1 PC with windows 1

2 Quartus project Navigator 1

THEORY

The logic gates are the basic building blocks of all digital circuits and computers. These
logic gates are implemented using transistors called MOSFETs. A MOSFET transistor is a
voltage-controlled switch. The MOSFET acts as a switch and turns on or off depending on
whether the voltage on it is either high or low. There are two types of MOSFETs: NMOS
and PMOS. The NMOS turns on when the voltage is high and off when the voltage is low.
The PMOS, on the other hand, turns on whenever the voltage is low and goes off as the
voltage goes high. When the two are used together to realize the logic gates, they are called
CMOS (Complementary MOS). The reason they are called complementary is that NMOS
and PMOS work in a complementary fashion. When the NMOS switch turns on, the PMOS
gets off, and vice-versa.

28
SIMULATION DIAGRAM

SIMULATION OUTPUT

29
PROCEDURE

1. Define the desired logic function (e.g., AND, OR, NOT) based on the truth table or Boolean
expression.
2. Use PMOS transistors to form the pull-up network that implements the logic when the output should
be high (1).
3. Use NMOS transistors to form the pull-down network that implements the logic when the output
should be low (0).
4. Verify that PUN and PDN are complementary, meaning for every path that connects the output to
VDDV_{DD}VDD, a corresponding path connects the output to ground.
5. Optimize for size, speed, and power consumption, then simulate the circuit to ensure correct
functionality and performance.

RESULT

30