FUNDAMENTALS OF MECHATRONICS / MICROPROCESSOR ORGANISATION AND DESIGN

CLASS TEST
THREE HOURS
ATTEMPT ALL FOUR QUESTIONS
QUESTION ONE
a) Table Q.1 is that of the memory address decoding table of the MC6809 microprocessor based system. Draw
the corresponding memory map to scale. Determine the size of each range. Calculate the start and end
address of each range. [10]

Table Q.1 Memory Address Decoding Table

A15 A14 A13 A12 A11 SELECTED Size Start End
DEVICE kilobytes Address Address
0 X X X X RAM 32 0000 7FFF
1 0 0 X X EEPROM 16 8000 9FFF
1 0 1 0 0 ACIA 4 A000 A7FF
1 0 1 0 1 PIA_0 4 A800 AFFF
1 0 1 1 0 PIA_1 4 B000 B7FF
1 0 1 1 1 PIA_2 4 B800 BFFF
1 1 X X X EPROM 16 C000 FFFF

b) Use discrete logic gates: AND, OR, NAND, NOR and NOT to implement the memory address decoding
logic. [10]

A15 A15 A13

A15 CS CS CS
A14 A14
RAM EPROM EEPROM
A14
A11
A12

A14
A11
A11
A15
A13

A13
A15

A15

A11
A13

A12

A13
A15
A12

A14
A14
A12

CS1 CS0 CS2 CS1 CS0 CS2 CS1 CS0 CS2 CS1 CS0

ACIA PIA_0 PIA_1 PIA_2

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 A15

A14

A13

A12

A11

RAM

EEPROM

ACIA

PIA_0

PIA_1

PIA_2

EPROM

c) Draw the diagram of an FPGA which can be used to implement the memory address decoding logic much
more compactly as one chip. [5]

QUESTION TWO
a) The serial link on the MC68HC11 uses 8 bits per character, no parity bit and 1 stop bit. Draw the TTL and
RS232 character frames’ timing diagrams when the two bytes: $A5 and $97 are transmitted. [8]

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 $A5 and $97
1 1010 0101 0 1 and 1 1001 0111 0 1
I DLE ST 0 1 2 3 4 5 6 7 STOP

b) An MC68HC11 is driven by a 4 MHz crystal. The required baud rate is 4800 bps. Determine the value that
must be written into the register BAUD during initialization. What is the exact accurate baud rate being
used? Calculate the percentage difference from the industry standard baud rate. Hence explain why the two
systems will still communicate despite a slight difference in baud rates? [7]
PR = 4000000/64 *4800 = 13.02083333333
Select P = 13 and R = 1. Write $30 into Baud during initialization.
Actual Baud Rate is 4 000 000 / (13 * 1 * 64) = 4807.6923. % Baud Rate difference = 0.1602%
This is much lower than the theoretical difference of 4.1666% calculated in a class tutorial which
would result in the incorrect errors at the receiving side.
BAUD $102B
TCLR SCP2 SCP1 SCP0 RCKB SCR2 SCR1 SCR0

PRESCALE FACTOR (P) SCI RATE SELECT FACTOR (R)

E/16 Divided by Prescale Factor P Prescaler Divided by factor
SCP2 SCP1 SCP0 FACTOR SCR2 SCR1 SCR0 Factor
X 0 0 1 0 0 0 1
0 0 1 3 0 0 1 2
X 1 0 4 0 1 0 4
X 1 1 13 0 1 1 8
1 0 1 9 1 0 0 16
1 0 1 32
1 1 0 64
1 1 1 128

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c) 137 bytes are to be written to the 25LC640 serial EEPROM starting at its internal address $1897. Come up
with a schedule of write operations using the usual format showing the start and end addresses for each
write operation in both binary and hexadecimal, the actual number of bytes written in each operation and the
balance, number of bytes yet to be written. [10]

Write Enable Latch

0001 1000 100 1 0111 $1897 9 bytes written 137 bytes left
0001 1000 100 1 1111 $189F
Write Enable Latch
0001 1000 101 0 0000 $18A0 32 bytes written 128 bytes left
0001 1000 101 1 1111 $18BF
Write Enable Latch
0001 1000 110 0 0000 $18C0 32 bytes written 96 bytes left
0001 1000 110 1 1111 $18DF
Write Enable Latch
0001 1000 111 0 0000 $18E0 32 bytes written 64 bytes left
0001 1000 111 1 1111 $18FF
Write Enable Latch
0001 1001 000 0 0000 $1900 32 bytes written 32 bytes left
0001 1001 000 1 1111 $191F
Write Enable Latch
0001 1001 001 0 0000 $1920 32 bytes written 0 bytes left
0001 1001 001 1 1111 $193F

QUESTION THREE
a) An MC68HC11 microcontroller is driven by a 7.3728 MHz crystal. The main timer Prescale Factor has been
set to 16 by writing “11” to the time protected bits (PR1:PR0) during initialization. Calculate the time
interval between main timer counter (TCNT) overflows. [4]
Enable Frequency = 7.3728 MHz / 4 = 1.8432 MHz. Enable Period = 1/1.8432 = 0.5425347222222
microsec. TCNT update interval is 16 * 0.542534722222 * 16 = 8.680555555 microsec.
65536 updates between TCNT overflows = > 65536 * 8.680555555 microsec => 0.5688888 seconds

b) The same microcontroller has the two bits RTR1:RTR0 set to “11” meaning a real time interrupt occurs
every 216 enable clocks. Calculate the time interval between real time interrupts and hence the number of
such interrupts which occur every second. Hence calculate the values which must be periodically written to
the variables time_out and adjust for the maintenance of a real time clock using the approach
introduced in lectures. [8]
Interval between Real Time Interrupts = 0.5425347222 * 65536 microsec. = 35 555.5555555 microseconds
0.035555555555 microsecs. Real Time Interrupt Rate = 1/0.03555 => 28.125 interrupts per second.
time_out is initialized with 28 decimal or $1C. Adjust = 28.125/0.125 = 225 or $E1

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 c) An input capture channel is to be used to measure the speed of an AC motor which has a proximity sensor
installed on its shaft being activated once every revolution. The falling edge on the sensor output is used for
input capture. The following successive captured readings are obtained by the main control program:
$ED7F, $117F, $357F and $597F. Calculate the speed of the AC motor in revolutions per minute
(RPM). [10]
$117F - $ED7F = $2400 is the number of TCNT updates between successive Input Capture Interrupts.
$2A00 => 256 *(2 * 16 + 4) => 256*36 => 9216. 9216 * 8.680555555 => 80 000.00 microsec.
0.08 sec. 1/0.08 = 12.5 RPS => 12.5 * 60 RPM = 750RPM.
QUESTION FOUR
Listing Q.4 is that of an MC6809 Microprocessor Assembly Language program. Assemble the program by
hand to convert it into Machine code using the standard listing format used by most assemblers. Generate the
corresponding Intel hex format and Motorola S format records. Include the end of file (EOF) record in each
case at the end. [25]
0400 BUFFER_SIZE EQU 1024
1000 BUFFER_START EQU BUFFER
13FF BUFFER_END EQU BUFFER_START + BUFFER_SIZE – 1
ORG $1000
1000 BUFFER RMB BUFFER_SIZE
1400 TAIL RMB 2
1402 HEAD RMB 2
B000 ACIA EQU $B000
B000 ACIA_TDR EQU ACIA
B001 ACIA_STATUS EQU ACIA + 1
10 ACIA_TDRE EQU $10
DF90 BE 1402 TRANSMIT_LOOP LDX HEAD
DF93 BC 1400 CMPX TAIL
DF96 27 FA BEQ TRANSMIT_LOOP
DF98 B6 B001 WAIT_TDRE LDA ACIA_STATUS
DF9B 85 10 BITA #ACIA_TDRE
DF9D 27 F9 BEQ WAIT_TDRE
DF9F A6 80 LDA 0,X+
DFA1 B7 B000 STA ACIA_TDR
DFA4 8C 13FF CMPX #BUFFER_END
DFA7 23 03 BLS NO_WRAP_AROUND
DFA9 8E 1000 DO_WRAP_AROUND LDX #BUFFER_START
DFAC BF 1402 NO_WRAP_AROUND STX HEAD
DFAF 20 DF BRA TRANSMIT_LOOP
Listing Q.4

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:10DF9000BE1402BC140027FAB6B001851027F9A6QQ
:10DFA00080B7B0008C13FF23038E1000BF140220QQ
:01DFB000E1QQ
:00000001FF

S113DF90BE1402BC140027FAB6B001851027F9A6QQ
S113DFA080B7B0008C13FF23038E1000BF140220QQ
S104DFB0E1QQ
S9030000FC