Mod-5: PIC 18 Introduction 1

Module 5

Contents:

Overview of PIC 18, memory organisation, CPU, registers, pipelining, instruction format,
addressing modes, instruction set, interrupts, interrupt operation, resets, parallel ports,
timers, CCP.
Features of the PIC18 microcontroller
 8-bit CPU
 2 MB program memory space
 256 bytes to 1KB of data EEPROM
 Up to 3968 bytes of on-chip SRAM
 4 KB to 128KB flash program memory
 Sophisticated timer functions that include: input capture, output compare, PWM, real-
time interrupt, and watchdog timer
 Serial communication interfaces: SCI SPI I2C and CAN
 Background debug mode (BDM)
 10-bit A/D converter
 Memory protection capability
 Instruction pipelining
 Operates at up to 40 MHz crystal oscillator

Overview of the PIC18 MCU

Microchip has introduced six different lines of 8-bit MCUs over the years:
1. PIC12XXX: 8-pin, 12- or 14-bit instruction format
2. PIC14000: 28-pin, 14-bit instruction format (same as PIC16XX)
3. PIC16C5X: 12-bit instruction format
4. PIC16CXX: 14-bit instruction format
5. PIC17: 16-bit instruction format
6. PIC18: 16-bit instruction format

Each line of the PIC MCUs supports different number of instructions with slightly
different instruction formats and different design in their peripheral functions. This makes
products designed with a different family of PIC MCUs incompatible. The members of the

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Mod-5: PIC 18 Introduction 2

PIC18 family share the same instruction set and the same peripheral function design and
provide from eight to more than 80 signal pins. This makes it possible to upgrade the PIC18-
based product without changing the MCU family. One of the design goals of the PIC18 MCU
is to eliminate the design flaws of other earlier MCU families and provide a better upgrade
path to other families of MCUs. In terms of cost, the PIC18 MCUs are not more expensive
than those in other families with similar capability.

The PIC18 MCUs provide the following peripheral functions:

1. Parallel I/O ports
2. Timer functions, including counters, input capture, output compare, real-time interrupt, and
watchdog timer
3. Pulse width modulation (PWM)
4. SPI and I2C serial interface
5. Universal Synchronous/Asynchronous Receiver Transmitter (USART)
6. A/D converter with 10-bit resolution
7. Analog comparator
8. Low-power operation mode
9. SRAM and EEPROM
10. EPROM or flash memory
11. Controller Area Network (CAN)

Memory Organisation

Memory consists of a sequence of directly addressable “locations.” A memory

location is referred to as an information unit. A memory location in the PIC18 holds eight bits
of information. Eight bits of information are called a byte. Sometimes one must deal with
four bits of information at a time. Four bits of information are called a nibble. A memory
location can be used to store data, instruction, the status of peripheral devices, and so on. An
information unit has two components: its address and its contents, shown in Figure.

Each location in memory has an address that must be supplied before its contents can
be accessed. The CPU communicates with memory by first identifying the address of the

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Mod-5: PIC 18 Introduction 3

location and then passing this address on the address bus. This is similar to the fact that a
mail carrier needs an address in order to deliver a letter. The data is transferred between
memory and the CPU along the data bus.

Separation of Data Memory and Program Memory

As shown in Figure, the PIC18 MCU assigns data and program to different memory
spaces and provides separate buses to them so that both are available for access at the same
time.

The PIC18 MCU has a 21-bit program counter that is divided into three registers:
PCU, PCH, and PCL. Among them, only the PCL register is directly accessible to the user.
Both the PCH and the PCL are eight bits, whereas the PCU is five bits.

Many digital systems have a large amount of memory. Therefore, special terms are often used
to refer to the size of memory system. Among them, KB, MB, and GB are most often used:

_ 1 KB refers to 210 (1,024) bytes of memory.

_ 1 MB refers to 2 20 (1,048,576) bytes of memory.

_ 1 GB refers to 230 (1,073,741,824) bytes of memory.

PIC18 Data Memory

The PIC18 data memory is implemented as SRAM. Each location in the data memory
is also referred to as a register or file register. The PIC18 MCU supports 4096 bytes of data

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Mod-5: PIC 18 Introduction 4

memory. It requires 12 bits of address to select one of the data registers. The data memory
map of the PIC18 MCU is shown in Figure.

Because of the limited length of the PIC18 instruction (most instructions are 16 bits),
only eight bits of the PIC18 instruction are used to specify the file register to be operated on.
As a result, the PIC18 designers divided the 4096 file registers into 16 banks. Only one bank
of 256 file registers is active at any time. An additional four bits are placed in a special
register called bank select register (BSR) to select the bank to be active. The user needs to
change the contents of the BSR register in order to change the active bank.

There are two types of registers: general-purpose registers (GPRs) and special-
function registers (SFRs). GPRs are used to hold dynamic data when the PIC18 CPU is
executing a program. SFRs are registers used by the CPU and peripheral modules for
controlling the desired operation of the MCU. These registers are implemented as SRAM.
The SFRs are assigned from the highest addresses and downward, whereas GPRs start from
address 0 and upward. Depending on the device, some of the GPRs in the middle are not
implemented.

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Mod-5: PIC 18 Introduction 5

For example, the PIC18F452 has 1536 (six banks) bytes of data memory, and then
banks 0 to 5 and bank 15 are implemented. The first 96 bytes (in bank 0, 0x000-0x05F) of the
GPRs and the last 160 bytes (in bank 15, 0xF60-0xFFF) of the SFRs are grouped into a
special bank called access bank. For the PIC18F242/ 252/442/452 MCUs, the access bank
comprises of the upper 128 bytes in bank 15 and the lower 128 bytes in bank 0.

EEPROM Data Memory

At the time of this writing, all the PIC18 devices that have on-chip flash program
memory also have either 256 bytes or 1024 bytes of data EEPROM. The data EEPROM is
readable and writable during normal operation over the entire power supply range. The data
EEPROM memory is not directly mapped in the register file space. Instead, it is indirectly
addressed through the special function register.

Program Memory Organization

Each PIC18 member has a 21-bit program counter and hence is capable of addressing
the 2-MB program memory space. Accessing a nonexistent memory location will cause a
read of all 0s. Different members of the PIC18 family have different memory configurations.
The PIC18CXX2 and PIC18CXX8 devices have on-chip EPROM program memory only and
cannot access external memory. The PIC18C601 and PIC18C801 do not have on-chip
memory. The PIC18C601 is capable of accessing 256 KB of external program memory,
whereas the PIC18C801 can access 2 MB of external program memory. The PIC18FXX2,
PIC18FXX8, and the PIC18F6620/6720 devices have on-chip flash program memory only.
The PIC18F8585/8680/8621/8620/8720 can also access external program memory in addition
to their on-chip flash program memory.

The PIC18 MCU has a 31-entry return address stack that is used to hold return
addresses for subroutine call and interrupt processing. This return address stack is not part of
the program memory space. The program memory map is illustrated in Figure.

As shown in Figure, the address 000000h is assigned to the reset vector, which is the
program-starting address after power-on or manual reset. The address 000008h is the starting
address of the high-priority interrupt service routine. Sixteen bytes are allocated to the high-
priority interrupt service routine by default. The address 000018h is the starting address for

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Mod-5: PIC 18 Introduction 6

the low-priority interrupt service routine, and there is no default size for this service routine.
The user program should follow the low-priority interrupt service routine.

The PIC18 CPU Registers

The PIC18 MCU has a group of registers, from 0xFD8 to 0xFFF (listed in Table 1.2),
in the data memory space that are dedicated to the general control of the CPU operation. This
group of registers can be referred to as CPU registers. Each of these CPU registers is
discussed in an appropriate chapter of this book.

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Mod-5: PIC 18 Introduction 7

The STATUS register, shown in Figure 1.6, contains the arithmetic status of the ALU.
As with any other register, the STATUS register can be the destination of any instruction. If
the STATUS register is the destination for an instruction that affects the Z, DC, C, OV, or N
bits, then the write to these five bits is disabled. These bits are set or cleared according to the

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Mod-5: PIC 18 Introduction 8

device logic. Therefore, the result of an instruction with the STATUS register as the
destination may be different than intended. It is recommended, therefore, that only BCF,
BSF, SWAPF, MOVFF, and MOVWF instructions be used to alter the STATUS register
because these instructions do not affect the Z, C, DC, OV, or N bits of the STATUS register.

The WREG register (referred to as working register) is a special register that is

involved in the execution of many instructions and can be the destination of many
instructions.

The PIC18 Pipelining

The PIC18 designer divided the execution of most of the PIC18 instructions into two
stages (instruction fetch and instruction execution) and then overlapped the execution of two
consecutive instructions. Each stage takes one instruction clock cycle to complete. The result

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Mod-5: PIC 18 Introduction 9

of the overlap of instruction execution is that most instructions take one instruction clock
cycle to complete. This scheme is called instruction pipelining. An example of instruction
pipelining is illustrated in Figure 1.7.

There are two problems caused by instruction pipelining: data dependency hazard and
control hazard. In a program, it is common for one instruction to perform further operation
on the result produced by the previous instruction. If the pipeline is designed in a way that the
earlier instruction cannot write the result back to the register or memory location before it is
used by the following instruction(s), then the data-dependency hazard has occurred. Most of
the data dependency hazards can be solved by result forwarding. However, if an instruction
reads from a memory location (e.g., a load instruction) whereas the following instruction will
use the returned value to perform certain operation, then result forwarding cannot resolve the
hazard.
This problem is usually solved by rearranging the instruction sequence to avoid this
type of data dependency or inserting a no-op instruction. The dependency hazard problem
will occur on pipelined processors with more than two stages. The PIC18 instruction pipeline
has only two stages and does not have data-dependency hazard problems. Control hazard is
caused by branch instructions. Whenever a branch instruction reaches the execution stage and
the branch is taken, then the following instructions in the pipeline need to be flushed because
they are not allowed to take any effect by the program logic. In Figure 1.7, the instruction
BSF PORTA, BIT3 is flushed when it reaches the execution stage for this reason. There are
several options to deal with control hazards in a pipelined processor. However, this issue is
beyond the scope of this text.
The PIC18 MCU needs to access program memory during the instruction fetch stage
and needs to access data memory during the instruction execute stage. When pipelining the
execution of instructions, the PIC18 MCU needs to access the program memory and the data

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Mod-5: PIC 18 Introduction 10

memory in the same clock cycle. This requirement is satisfied by separating the program
memory from the data memory and providing separate buses to them. The pipelined
processor is explained clearly in Patterson and Hennessy’s book Computer Organization
published by Morgan Kaufman.

PIC18 Instruction Format

It was mentioned in Section 1.5.2 that data memory is divided into banks. Why would
the banking scheme be used to control the access of data memory? The instruction format
must be defined in order to understand this issue.
The instruction set is grouped into five basic categories:
1. Byte-oriented operations. The format of byte-oriented instructions is shown in Figure 1.8.
The 6-bit field opcode specifies the operation to be performed by the ALU.

2. Byte-to-byte operations (two-word). The format of the instruction in this category is shown
in Figure 1.9. There is only one instruction that uses this format: movff f1, f2. This
instruction allows one to move data from one file register to another.

3. Bit-oriented file register operations. The format of instructions in this category is shown
in Figure 1.10. This format uses an 8-bit field (f) to specify a file register as the operand.

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Mod-5: PIC 18 Introduction 11

4. Literal operations. Instructions in this category specify a literal (a number) as an operand.

The format of instructions in this category is shown in Figure 1.11.

5. Control operations. The format of instructions in this category is shown in Figure 1.12.
The notation n<7:0> stands for the bit 7 to bit 0 of the number n, whereas the notation
n<19:8> stands for the bit 19 to bit 8 of the number n. The notation n<10:0> means that the
number n is an 11-bit number. There are four different variations in their formats.

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Mod-5: PIC 18 Introduction 12

All the PIC18 instructions use eight bits to specify the data register operand. A data
register (excluding WREG) is also called a file register. Only 256 different registers can be
specified by eight bits. However, all the PIC18 devices have more than 256 file registers, and
hence additional information is needed to pinpoint the exact register to be operated on. This
additional information is stored in the BSR register. The designer of the PIC18 MCU divided
data memory into 16 (maximum) banks, with each bank having 256 data registers. The BSR
register specifies the bank, and the f field in the instruction specifies the register number
within the bank.
The banking scheme has been used in the PIC12, the PIC14000, the PIC16, and the
PIC17 MCUs. This scheme allows a PIC MCU to incorporate more than 256 data registers on
the CPU. However, it also adds a significant amount of overhead to the software because of
the need to switch from one bank to another. In addition, it is easy to forget about bank
switching, which will cause the software to fail.
In order to solve the problem caused by the banking scheme, the designers of the
PIC18 MCU incorporated the access bank. The access bank consists of the lowest 96 GPRs
and the highest 160 SFRs. As long as an instruction specifies a data register in the access
bank, banking is ignored, and bank switching is unnecessary. All SFRs except a subset in the
CAN module are in the access bank (CAN stands for controller area network). This makes
bank switching unnecessary in many cases.
When bank switching is needed, the movlb k instruction can be used. This instruction
places the value of k in the lower four bits of the BSR register. The result of the execution of
this instruction is that it caused the data registers in bank k to become active. In Figures 1.8
and 1.10, the a field in the PIC18 instruction allows the user to select the access bank. When
writing program in assembly language, the assembler (MPASM) allows the user to use the
letter A (a = 0) to specify the access bank. When the access bank is not chosen, one should
use the word BANKED (a = 1) to allow the BSR register to do the bank selection. The d field
in Figure 1.8 allows the user to choose either the WREG or the file register as the destination
of the instruction. The assembler allows the user to use the letter F (d = 1) to specify a file
register and use the letter W (d = 0) to specify the WREG register as the destination. For
example,
addwf sum, F, A ; sum is a GPR
adds the WREG register and sum in the access bank and places the result in sum.
addwf sum,W, A
performs the same operation but leaves the result in the WREG register.

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Mod-5: PIC 18 Introduction 13

Addressing Modes

All MCUs use addressing modes to specify the operand to be operated on. The PIC18
MCU provides register direct, immediate, inherent, indirect, and bit-direct addressing modes
for specifying instruction operands. As discussed in Chapter 2, assembler directives allow the
user to use symbols to refer to memory locations. Using symbols to refer to memory locations
makes the user program more readable. During the following discussion, symbols are used to
refer to memory locations when appropriate.
1. Register Direct
The PIC18 device uses an 8-bit value to specify a data register as an operand. The
register may be in the access bank or other banks. In the first case, the 8-bit value is used to
select a register in the access bank, and the bank value in the BSR register is ignored. If the
access bank is not selected, then the access is completed from the memory of the bank
specified in the BSR register. The following instructions illustrate the register direct
addressing mode:
movwf 0x1A, BANKED

copies the contents of the WREG register to the memory location 0x1A in the bank specified
by the BSR register. The word BANKED (must be in uppercase) informs the assembler that
the BSR register must be included in specifying the data register to be operated on.
movwf 0x45, A
copies the contents of the WREG register to the memory location 0x45 in the access bank.
movff reg1, reg2
copies the contents of the register reg1 to the register reg2. Both reg1 and reg2 are 12-bit
values.
The value of BSR is ignored.
2. Immediate Mode
In the immediate addressing mode, the actual operand is provided in the instruction.
There is no need to access any memory location. The following instructions illustrate the
immediate addressing mode:
addlw 0x20
adds the hex value 20 to the WREG register and places the sum in the WREG register.
movlw 0x15
loads the hex value 15 into the WREG register.

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Mod-5: PIC 18 Introduction 14

movlb 3
places the decimal value 3 in the lower four bits of the BSR register. The lower four bits
become 0011. This instruction makes bank 3 the active bank. The value to be operated on
directly is often called literal.
3. Inherent Mode
In the inherent mode, the operand is implied in the opcode field. The instruction
opcode does not provide the address of the implied operand. The following instructions
illustrate the inherent mode:
movlw 0x20
places the hex value 20 (decimal 32) in the WREG register. In this example, the value 0x20 is
specified in the instruction machine code. The destination WREG is implied in the opcode
field. No other address information for the WREG register is supplied.
andlw 0x13
performs an AND operation on the corresponding bits of the hex number 13 and the WREG
register (i.e., bit i of WREG and with bit i of the value 0x13; i = 0 . . . 7). In this example,
only the immediate value 0x13 is specified in the instruction machine code. The address of
the WREG register 0xFE8 is not specified.
4. Indirect Mode
In this mode, a special function register is used as a pointer to the data memory
location that is to be read and written. Since this register is in SRAM, the contents can be
modified by the program. This can be useful for data tables in data memory and for software
stacks. The software stack will be explained in Chapter 4.
There are three indirect addressing registers: FSR0, FSR1, and FSR2. To address the entire
data memory space (4096 bytes), 12 bits are required. To store the 12-bit address
information, two 8-bit registers are used. These indirect addressing registers are the
following:
1. FSR0: composed of FSR0H and FSR0L
2. FSR1: composed of FSR1H and FSR1L
3. FSR2: composed of FSR2H and FSR2L
After placing the address of the data in one of the FSR registers, one needs to read from or
write into one of the three registers that are not physically implemented in order to activate
indirect addressing. These three registers are INDF0, INDF1, and INDF2. If an instruction
writes a value to INDF0, the value will be written to the data register with the address
indicated by the register pair FSR0H:FSR0L. A read from INDF1 reads the data from the

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Mod-5: PIC 18 Introduction 15

data register with the address indicated by the register pair FSR1H:FSR1L. INDFn can be
used in a program anywhere an operand can be used. The process of indirect addressing is
illustrated in Figure 1.13.

Each FSR register has an INDF register associated with it plus four additional register
addresses. Performing an operation on one of these five registers determines how the FSR
will be modified during indirect addressing:
1. Do nothing to FSRn after an indirect access. This access is specified by using the register
INDFn (n = 0 . . . 2).
2. Auto-decrement FSRn after an indirect access (postdecrement). This access is specified by
using the register POSTDECn (n = 0 . . . 2).
3. Auto-increment FSRn after an indirect access (postincrement). This access is specified by
using the register POSTINCn (n = 0 . . . 2).
4. Auto-increment FSRn before an indirect access (preincrement). This access is specified by
using the register PREINCn (n = 0 . . . 2).
5. Use the value in the WREG register as an offset to FSRn. The signed value in WREG is
added to the value in FSR to form an address before performing an indirect access. Neither

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Mod-5: PIC 18 Introduction 16

the WREG nor the FSRn is modified after the access. This access is specified by using the
register PLUSWn.
The following examples illustrate the usage of indirect addressing modes:
movwf INDF0
copies the contents of the WREG register to the data memory location specified by the FSR0
register. After the execution of this instruction, the contents of the FSR0 register are not
changed.
movwf POSTDEC0
copies the contents of the WREG register to the data memory location specified by the FSR0
register. The contents of FSR0 are decremented by 1 after the operation.
movwf PREINC0
first increments the FSR0 register by 1 and then copies the contents of the WREG register to
the data memory location specified by the FSR0 register.
clrf PLUSW0
clears the memory location at the address equal to the sum of the value in the WREG register
and that in the FSR0 register.
In the previous examples, one does not need to specify whether the register is in the
access bank because the complete 12-bit data register address is taken from one of the FSR
registers.
5. Bit-Direct Addressing Mode
The PIC18 MCU has five instructions to deal with an individual bit. These
instructions use three bits to specify the bit to be operated on. For example,
BCF PORTB,3,A ; integer 3 specifies the bit to be cleared
clears bit 3 of the data register PORTB, which will then pull the port B pin RB3 to low.
BSF PORTA,4,A ; integer 4 specifies the bit to be set
sets bit 4 of the data register PORTA, which will then pull the port A pin RA4 to high.

PIC18 Instructions

The PIC18 has 77 instructions. Four of these are 32-bit instructions, whereas the
others are all 16 bits. A subset of the PIC18 instructions is examined in this section.

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Mod-5: PIC 18 Introduction 17

Word list
f- any memory location in a microcontroller
W- work register
b- bit position in 'f' register
d- destination bit
label- group of eight characters which marks the beginning of a part of the program
TOS- top of stack
[ ]- option
< >- bit position inside register
Data Transfer Instructions

Data Transfer within the microcontroller takes place between working register W (called
accumulator) and a register which represents any location of internal RAM regardless of
whether it is about special function or general purpose registers.

These instructions provide for: -a constant being written in W register (MOVLW) - data to be
copied from W register onto RAM. - data from RAM to be copied onto W register (or on the
same RAM location, at which point only the status of Z flag changes). -Instruction CLRF
writes constant 0 in 'f ' register, - Instruction CLRW writes constant 0 in register W. SWAPF
instruction exchanges places of the 4-bit nibbles field inside a register.

Arithmetic-logic Instructions

Similar to most microcontrollers, PIC supports only two arithmetic instructions- addition and
subtraction. Flags C, DC, Z are automatically set depending on the results of addition or
subtraction. The only exception is the flag C. Since subtraction is performed as addition with
negative value, the flag C is inverted after subtraction. It means that the flag C is set if it is
possible to perform operation and cleared if the larger number is subtracted from smaller one.

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Mod-5: PIC 18 Introduction 18

Logic one (1) of the PIC is able to perform operations AND, OR, EX-OR, inverting (COMF)
and rotation (RLF and RRF).

Instructions which rotate a register actually rotate its bits through the flag C by one bit left
(toward bit 7) or right (toward bit 0). The bit shifted from the register is moved to the flag C
which is automatically moved to the bit on the opposite side of the register.

Bit-oriented Instructions

Instructions BCF and BSF clear or set any bit in memory. Although it seems to be a simple
operation, it is not like that. CPU first reads the entire byte, changes one its bit and rewrites
the whole byte to the same location.

Program Control Instructions

The PIC16F887 executes instructions GOTO, CALL, RETURN in the same way as all other
microcontrollers do. A difference is that stack is independent from internal RAM and has 8

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Mod-5: PIC 18 Introduction 19

levels. The ‘RETLW k’ instruction is identical to RETURN instruction, with exception that a
constant defined by instruction operand is written to the W register prior to return from
subroutine. This instruction enables Lookup tables to be easily created by creating a table as
a subroutine consisting of ‘RETLWk‘instructions, where the literals ‘k’ belong to the table.
The next step is to write the position of the literals k (0, 1, 2, 3...n) to W register and call the
subroutine (table) using the CALL instruction.

Interrupts
Interrupts, as the name suggests interrupts the normal execution and Requests and
urgent attention of CPU. Interrupts are situations that the CPU can’t predict when they will
happen, they can happen any time, so the CPU does not wait for them. So the CPU keeps on
doing its normal job unless and interrupt occurs. For example when the USART (Serial
Communication Hardware) will receive data is unknown, it can receive data any time. So the
CPU keeps on doing its normal job, which may be for example read temperature using LM35
sensor and display on LCD. The CPU keeps on doing the "normal" job, but as soon as the
USART receive data it informs the CPU using an interrupt. The CPU save its current state (so
that it can resume), and jumps to the ISR (interrupt service routine) immediately. Where we
can process the command or put it in a FIFO queue (to process latter). The ISR is generally
kept very small and fast. As soon as the ISR ends, the CPU restores its saved state and
resumes where it left. In this way CPU does not missed any data byte.
Example of sources of Interrupts in PIC18 (also common in other MCUs)

 External interrupts – they are named INTx (like INT0, INT1 etc), they provide a
means for external hardware to generate interrupts. Like if you connect a touch screen
controller to your PIC MCU. Then the touch screens PENINT (pen interrupt) can be
connected to INT0 (or any other INTx). Then when ever the pen (or stylus) touches

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Mod-5: PIC 18 Introduction 20

the screen it will interrupt the CPU. This interrupt will be explained in details in its
own tutorial.
 TIMER interrupts – They are also very common in MCUs. Today’s MCUs comes
with very sophisticated timers that can do lots of magic for you. They have they
related interrupts. In most simple situation they can act like alarm clocks that can
interrupt the CPU at predefined intervals. If you toggle a i/o pin in response to these
alarms (interrupts), what you have is a frequency generator! For more info on timers
on PIC18, read this article.
 Analog to Digital Converter Interrupts – A/D Converter takes some time to
complete its operation. So the CPU can either wait for it to complete or set up an AD
conversion complete interrupt. In the latter case CPU can do other tasks while A/D
converter converts the input. As soon as A/D converter completes its job it will
inform CPU to read the value from its buffer. For more info on A/D Converter of
PIC18, read this article.
 Data Interrupts – MCUs have many different types of data i/o engines, like USART,
SPI, I2C, Parallel etc. They can also interrupt the CPU when data transmission is
complete or data arrives from external source. Like an RFID reader send a packet
because a user just brought his or her card near the reader. Or the GSM module
detected an incoming call.

Interrupts handling

In general each interrupt source have following related bits.

 Enable Bit – They are suffixed with IE (Interrupt Enable) example TMR0IE stands
for TIMER0 Interrupt Enable. It can be used to enable/disable the related interrupt.
When set to ’1′ it enables the interrupt.
 Flag Bit – It is set automatically by the related hardware when the interrupt condition
occurs. It is generally suffixed with IF (Interrupt Fag). When it is set to ’1′ we know
that interrupt has occurred. For example when TMR0IF is set by TIMER0, it indicates
that TIMER0 has overflowed.
 Priority Bit - We can leave this for now to keep things simple. We won’t be using
interrupt priority feature of PIC18.

In global level their are following bits to control the interrupts globally.

 GIE – Global Interrupt Enable, enables/disables interrupts globally.

 PEIE – Enable/disable all peripheral interrupts.

Interrupt Vector
It is the address where the CPU jumps when an interrupt occurs. In PIC18 this address
is 0008(hex). CPU jumps to this address for any interrupt. The ISR or Interrupt service
routine is placed in this address. The ISR must determine the source of interrupt from the flag
bit(described above).

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Mod-5: PIC 18 Introduction 21

The ten registers used to control interrupts on the PIC18F2455 are:

 RCON – Reset Control register

This register contains the interrupt priority enable bit (IPEN) along with some other
bits that can be used to determine why a device reset occurred.
 INTCON, INTCON2, INTCON3 – Interrupt control registers
These registers contain the GIEH and GEIL bits, used to enable interrupts, along with
interrupt enable, priority, and flag bits for various interrupt sources.
 PIR1, PIR2 – Peripheral Interrupt Request registers
The PIR registers contain the interrupt flags for the “peripheral” interrupt sources,
which include: The ADC, UART, CCP, USB, TMR3, TMR2, TMR1, and TMR0 modules.
 PIE1, PIE2 – Peripheral Interrupt Enable registers
The PIE registers contain the enable bits for the peripheral interrupt sources. Setting a
bit in the register enables the associated interrupt source, while clearing a bit disables
interrupt for that source.
 IPR1, IPR2 – Interrupt Priority Registers
If the IPEN bit is set then interrupt priority is enabled and these registers are used to
set the priority of the individual interrupt sources. Setting a source’s associated IPR bit makes
that source a high priority interrupt, while clearing it makes it low priority.

Every interrupt source has three bits in the above registers (three bits total, not three in
each register..) which are used to set the interrupt source’s priority to high or low, enable or
disable interrupts for the source, and to set or clear the interrupt flag for the source. (note:
clear the interrupt flag before enabling interrupts for it)

Interrupt Priority

When interrupt priority is enabled, all enabled interrupts must be configured as "high
priority" or "low priority." Interrupt priority allows a more important interrupt (high priority)
to interrupt a not-as-important interrupt (low priority). In most cases, interrupt priority is not
needed and is not recommended because of performance consequences.
If interrupt priority is enabled, because the high interrupt vector is small in size, usually a go
to instruction is placed in the interrupt vector to call the actual interrupt handler. If a high
priority interrupt occurs while the low priority interrupt service routine (ISR) is being
executed, the program will branch to the high priority ISR and return when it’s done.

Using interrupts

1. Set interrupt priority

The Interrupt Priority Enable (IPEN) bit determines whether the Interrupt Priority feature is
enabled or not. The GIE/GIEH bit and the PEIE/GEIL bit have different meanings depending
on the IPEN bit. Set

2. Enable unmasked interrupts

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Mod-5: PIC 18 Introduction 22

When IPEN = 1:
Interrupt priority is enabled and GIEH and GIEL allow you to enable high priority interrupts,
low priority interrupts, or both. A source’s interrupt priority is determined by its associated
bit in the IPR registers.

Set the following bits:

GIEH (INTCON<7>) – Global Interrupt Enable High: enables high priority interrupts (1), or
disables interrupts (0).
GIEL (INTCON<6>) – Global Interrupt Enable Low: enables low priority interrupts (1), or
disables low priority interrupts (0).

When IPEN = 0:
Interrupt priority is disabled; the interrupt priority registers become irrelevant and all
interrupts branch to the high priority interrupt vector.

Set the following bits:

GIE (INTCON<7>) – Global Interrupt Enable: enables interrupts (1), or disables interrupts
(0).
PEIE (INTCON<6>) – Peripheral Interrupt Enable: enables peripheral interrupts (1), disables
peripheral interrupts (0).

3. Unmask interrupts
Now that interrupts are enabled, and interrupt priority has been configured, it's time to
unmask (enable) individual interrupt sources. This is done by setting the interrupt source's
enable bit, which is located in either INTCON, INTCON2, INTCON3, PIE1, or PIE2. Clear
the source's interrupt flag before enabling it.
4. Set interrupt source priorities
If interrupt priority is enabled, then each interrupt source must have its interrupt priority bit
set to either 1 (high priority) or 0 (low priority). This step is not necessary if interrupt priority
is not enabled.

The ISR

An ISR (Interrupt Service Routine) is a function that the processor branches to when an
interrupt occurs.

As previously mentioned, the low priority and high priority interrupt vectors are located at 8h
and 18h respectively.

Resets

Microcontroller PIC16F84’s several sources of resets are:

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Mod-5: PIC 18 Introduction 23

a) Reset during power on, POR (Power-On Reset)

b) Reset during regular work by bringing logical zero to MCLR microcontroller's pin.
c) Reset during SLEEP regime
d) Reset at watchdog timer (WDT) overflow
e) Reset during at WDT overflow during SLEEP work regime.

The most important reset sources are a) and b). The first one occurs each time a power supply
is brought to the microcontroller and serves to bring all registers to a starting position initial
state. The second one is a product of purposeful bringing in of a logical zero to MCLR pin
during normal operation of the microcontroller. This second one is often used in program
development.

During a reset, RAM memory locations are not being reset. They are unknown during a
power up and are not changed at any reset. Unlike these, SFR registers are reset to a starting
position initial state. One of the most important effects of a reset is setting a program counter
(PC) to zero (0000h) , which enables the program to start executing from the first written
instruction.

Parallel Ports

I/O pins are often grouped into ports. A port consists of up to 8 pins, a data direction
register (TRISx), a latch register (LATx) , and a data register (PORTx); where, x = A…H, J,
K. Data to be output is written into the latch, which in turn drives the output pins. A PIC18
may have as many as 10 I/O ports. An I/O port is often multiplexed with one or more
peripheral functions. When a peripheral function is enabled, the I/O pins cannot be used for
general purpose I/O.

Data direction needs to be set before the I/O operation. To configure an I/O pin for
input, set the associated bit in the TRIS register to 1. To configure an I/O pin for output, set
the associated bit in the TRIS register to 0.

Timers

Timers are common features of most microcontrollers. In simplified terms a timer is just a
register whose value keeps increasing (or decreasing) by a constant rate without the help of
the CPU. The CPU can read or write this register any time. It reads it find out how much time
has elapsed. The Timer register can have the following bit length.

 8 bit timers – These can count between between 0-255

 16 bit timers – These can count between 0-65536
 32 bit timers – These can count between 0-4294967296

A PIC18 microcontroller may have up to 5 timers: Timer0…Timer4. Timer0, Timer1,

and Timer3 are 16-bit timers whereas Timer2 and Timer4 are 8-bit.When a timer rolls
over, an interrupt may be generated if it is enabled. Both Timer2 and Timer4 use
instruction cycle clock as the clock source whereas the other three timers may also use
external clock input as the clock source.

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 Mod-5: PIC 18 Introduction 24

Timer0
Timer 0 Can be configured as an 8-bit or 16-bit timer or counter. It can select the internal
instruction cycle clock or the T0CKI signal as the clock signal. The user can choose to divide
the clock signal by a prescaler before connecting it to the clock input to Timer0. The T0CON
register controls the operation of Timer 0. Timer0 can operate as a timer or as a counter.
When the clock source is the instruction cycle clock, it operates as a timer. When the clock
source is the T0CKI pin, it operates as a counter.

Timer1

It is a 16-bit timer/counter depending upon the clock source. An interrupt may be

requested when Timer1 rolls over from 0xFFFF to 0x0000. Timer1 can be reset when the
CCP module is configured to compare mode to generate a special event trigger. Timer1
operation is controlled by the T1CON register. Timer1 can be configured to use the oscillator
connected to the T1OSO and T1OSI pins. The Timer1 oscillator is primarily intended for a
32 KHz crystal. Timer1 can be used to create time delays and measure the frequency of an
unknown signal.

Timer2

It is 8-bit timer TMR2 and 8-bit period register PR2. TMR2 is counting up and
comparing with PR2 in every clock cycle. When TMR2 equals PR2, the EQ signal will reset
TMR2. A postscaler is applied to the EQ signal to generate the TMR2 interrupt. The TMR2
output is fed to the synchronous serial port module. The operation of Timer2 is controlled by
T2CON register.

Timer3

Timer3 consists of two 8-bit registers TMR2H and TMR2L. Timer3 can choose to use
either the internal (instruction cycle clock) or external signal as the clock source. Reading
TMR3L will load the high byte of Timer3 into the TMR3H register. Timer3 operation is
controlled by the T3CON register.

Timer4

Only available to the PIC18F8X2X and PIC6X2X devices. The value of TMR4 is
compared to PR4 in each clock cycle.When the value of TMR4 equals that of PR4, TMR4 is
reset to 0. The contents of T4CON are identical to those of T2CON.

CCP

CCP stands for Capture/Compare/PWM.

The CCP module is a peripheral which allows the user to time and control different events.

The Capture/Compare/PWM module has three modes of operation:

 Capture - Capture the time of an event.

 Compare - Generate an output when Timer 1 reaches a value.
 PWM - Pulse Width Modulation.

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Mod-5: PIC 18 Introduction 25

Capture

Capture mode is used to capture the value of Timer 1 when a signal at the CCP pin goes high
(or low depending on how the CCP is set up). The CCP can accurately capture the arrival
time of a signal at the CCP pin so it can be used for pulse time measurement.

Compare

Compare mode is used to generate an output when Timer 1 reaches a value you put into
CCPR1. One special event trigger mode lets you start the ADC when the compare mode
triggers.

PWM

PWM gives you one Pulse Width Modulation output with 10 bit resolution and with no
software overhead - once started it operates all by itself unless you want to change the duty
cycle.

It uses Timer 2 to define its operation using Timer 2 period register to define the frequency of
the PWM.

Muhammed Riyas A.M, Assistant Professor,Department of E.C.E, M.C.E.T Pathanamthitta