15/09/17

Lecture 1: EVOLUTION OF COMPUTER SYSTEM

Lecture1:48:
Lecture DIRECT MEMORY
EVOLUTION ACCESS
OF COMPUTER SYSTEM

PROF.
DR. KAMALIKA DATTA
DR.INDRANIL
KAMALIKASENGUPTA
DATTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, IIT MEGHALAYA
KHARAGPUR
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

1 2

Introduc)on
• In the data transfer methods discussed under programmed I/O, it is
assumed that machine instruc;ons are used to transfer the data between
I/O device and memory.
– Not very suitable when large blocks of data are required to be transferred at
high speed (e.g. transfer of a disk block).
• An alternate approach is Direct Memory Access (DMA).
– Allows transfer of a block of data directly between an I/O device and memory,
without con;nuous CPU interven;on.

2 2

1
 15/09/17

• Why programmed I/O is not suitable for high-speed data transfer?

a) Several program instruc;ons have to be executed for each data word
transferred between the I/O device and memory.
• Suppose 20 instruc;ons are required for each word transfer.
• The CPI of the machine running at 1 GHz clock is 1.
• So, 20 nsec is required for each word transfer à maximum 50 M words/sec
• Data transfer rates of fast disks are higher than this figure.

3 2

b) Many high speed peripheral devices like disk have a synchronous mode of
opera;on, where data are transferred at a fixed rate.
• Consider a disk rota;ng at 7200 rpm, with average rota;onal delay of 4.15 msec.
• Suppose there are 64 Kbytes of data recorded in every track.
• Once the disk head reaches the desired track, there will be a sustained data transfer at
rate 64 Kbytes / 4.15 msec = 15.4 MBps.
• This sustained data transfer rate is comparable to the memory bandwidth, and cannot
be handled by programmed I/O.

4 2

2
 15/09/17

DMA Controller
• A hardwired controller called the DMA controller can enable direct data
transfer between I/O device (e.g. disk) and memory without CPU
interven;on.
– No need to execute instruc;ons to carry out data transfer.
– Maximum data transfer speed will be determined by the rate with which
memory read and write opera;ons can be carried out.
– Much faster than programmed I/O.

5 2

MEMORY

Address Bus
CPU Data Bus
Control Bus

DMA-ACK
DMA-RQ

DMA Controller DISK

6 2

3
 15/09/17

Steps Involved

a) When the CPU wants to transfer data, it ini;alizes the DMA controller.
– How many bytes to transfer, address in memory for the transfer.
b) When the I/O device is ready for the transfer, the DMA controller sends DMA-RQ
signal to the CPU.
c) CPU waits ;ll the next DMA breakpoint, relinquishes control of the bus (i.e. puts
them in high impedance state), and sends DMA-ACK to DMA controller.
d) Now DMA controller enables its bus interface, and transfers data directly to/from
memory.
e) When done, it deac;vates the DMA-RQ signal.
f) The CPU again begins to use the bus to access memory.

7 2

• The DMA breakpoints:

– DMA request can be acknowledged at the end of any machine cycle.
DMA
breakpoints
Why cannot we have
interrupt breakpoints
at the end of any
IF ID EX MEM WB
machine cycle?

Instruc;on Cycle

8 2

4
 15/09/17

• For every DMA channel, the DMA controller will have three registers:
a) Memory address
b) Word count
c) Address of data on disk
• CPU ini;alizes these registers before each DMA transfer opera;on.
• Before the data transfer, DMA controller requests the memory bus from
the CPU.
• When the data transfer is complete, the DMA controller sends an
interrupt signal to the CPU.

9 2

DMA-RQ DMA-RQ1
DMA-ACK1
DMA-ACK

CPU
DMA ..
Controller .
INTR
DMA-RQ4
DMA-ACK4

10 2

5
 15/09/17

DMA Transfer Modes

• DMA transfer can take place in two modes:
a) DMA cycle stealing
• The DMA controller requests for the for a few cycles 1 or 2.
• Preferably when the CPU is not using memory.
• DMA controller is said to steal cycles from the CPU without the CPU knowing it.
b) DMA block transfer
• The DMA controller transfers the whole block of data without interrup;on.
• Results in maximum possible data transfer rate.
• CPU will lie idle during this period as it cannot fetch any instruc;ons from memory.

11 2

Cycle Block
DMA controller Stealing DMA controller
Transfer
takes over bus Mode takes over bus
Mode

DMA controller DMA controller

transfers one word transfers one word

DMA controller DMA controller

return bus control return bus control

12 2

6
 15/09/17

Others Applica)ons of DMA

• Other than data transfer to/from high-speed peripheral devices, DMA can
be used in some other areas as well:
– High-speed memory-to-memory block move.
– Refreshing dynamic memory systems, by periodically genera;ng dummy read
requests to the columns.

13 2

END OF LECTURE 48

14 2

7
 15/09/17

Lecture 1: EVOLUTION OF COMPUTER SYSTEM

Lecture 49: SOME
Lecture EXAMPLE
1: EVOLUTION OFDEVICE INTERFACING
COMPUTER SYSTEM

DR. KAMALIKA DATTA

PROF.
DR.INDRANIL
KAMALIKASENGUPTA
DATTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, IIT MEGHALAYA
KHARAGPUR
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

15 2

Introduc)on
• Here we consider two simple examples to illustrate the I/O device interfacing
techniques discussed earlier.
a) Keyboard interfacing
b) Printer interfacing

16 2

8
 15/09/17

Keyboard Interfacing
• What is a keyboard?
– A set of pushbufon switches (keys) interfaced to a computer.
– Typically arranged in the form of a two-dimensional matrix.
• A key is connected to a row line and a column line at every junc;on.
• Results in minimiza;on of the number of port lines required.

17 2

Interfacing VCC

Switches R
ON
• How to check status for P1.0
asynchronous transfer? P1.1
P1.2
P1.3
P1.4
Read from port P1.5
P1.6
P1.7
= FF? PORT
Yes 8051
DIP
No SWITCH

18 2

9
 15/09/17

Interfacing a +5V

Keyboard
P1.0
• One key per port line. P1.1

• For N keys, number of port P1.2

lines required will be N. P1.3

P1.4
• Too expensive.
P1.5
P1.6
P1.7

PORT
8051

19 2

Interfacing a
Keyboard
3 2 1 0
PULL-UP
P1.0 REGISTERS
• Keys organized in matrix X1
7 6 5 4 10KΩ
form. P1.1
X2
• For N keys, number of port B A 9 8
P1.2
lines required will be 2 √N. X3
F E D C
• Possible to interface P1.3
large keyboards. X4 Y4 Y3 Y2 Y1

2-D
8051 P2.3 P2.2 P2.1 P2.0

20 2

10
 15/09/17

• How to detect the status of the device (i.e. whether any key has been
pressed)?
– Output all-0’s to the rows.
– Read the column port, and check whether all the bits are 1.
– If any of the bits is 0, it means a key has been pressed.
• Allows asynchronous mode of transfer.

21 2

• How to detect which key has been pressed?

– Requires a process called keyboard scanning.
– One of the rows is made 0 at a ;me, and the column bits are checked.
– We basically check whether some key in that par;cular row has been pressed.
• We find out both the row number and the column number of the key that
has been pressed.

22 2

11
 15/09/17

• How to interface a keyboard in interrupt driven mode?

– Normally all the rows of the keyboard are connected to ground; possibly
through a set of AND gates with a control input that is made 0.
– The column lines are connected to the inputs of a NAND gate, the output of
which is connected to the INTR input.
– The output of the NAND gate will become 1 whenever any key is pressed.
• Inside the ISR:
– The control inputs of the AND gates are set to 1.
– Normal keyboard scanning is carried out to iden;fy the key pressed.

23 2

Printer Interfacing
• Older printers has serial and parallel ports for interfacing to computer
systems.
– RS-232C serial data interface.
– LPT parallel data interface (8 data lines).
• Modern-day printers support the much higher speed Universal Serial Bus
(USB) interface.
– Almost all devices today have USB interfaces.

24 2

12
 15/09/17

• The LPT port used a 25-pin connector:

– 8 data lines
– STROBE
– BUSY
– ACK
• Aler sending the data, the CPU ac;vates the STROBE input to inform the
printer that data is ready.
– The printer will ac;vate BUSY and start prin;ng; once done, it will send back
ACK to the CPU.
• The interface allows asynchronous data transfer using handshaking.

25 2

26 2

13
 15/09/17

END OF LECTURE 49

27 2

Lecture 1: EVOLUTION OF COMPUTER SYSTEM

Lecture
Lecture 50: EXERCISES
1: EVOLUTION OFON I/O TRANSFER
COMPUTER SYSTEM

DR. KAMALIKA DATTA

PROF.
DR.INDRANIL
KAMALIKASENGUPTA
DATTA
DEPARTMENT
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING,
OF COMPUTER SCIENCE AND NIT
ENGINEERING, IIT MEGHALAYA
KHARAGPUR
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

28 2

14
 15/09/17

Example 1

• Suppose we want to read 2048 bytes in programmed I/O mode of

transfer. The bus width is 32 bits. Each ;me an interrupt occurs, it takes 4
μsec to service it (i.e. transfer 32 bits). How much CPU ;me is required to
read 2048 bytes?

29 2

Example 2

• A DMA module is transferring bytes to main memory from an external

device at 76800 bps. The CPU can fetch instruc;ons at a rate of 2 million
instruc;ons per second. Assume instruc;on size is 32 bits. How much will
the processor be slowed down due to DMA ac;vity?

30 2

15
 15/09/17

Example 3

• A DMA controller transfers 32-bit words to memory using cycle stealing.

The words are assembled from a device that transmits bytes at a rate of
2400 bytes per second. The CPU is fetching and execu;ng instruc;ons at
an average rate of 1 million instruc;ons per second. By how much ;me
will the CPU be slowed down because of the DMA transfer?

31 2

Example 4

• Consider a system employing interrupt-driven I/O for a device that transfers

data at 8 KB/s on a con;nuous basis. The interrupt processing takes about
100μsec and the I/O device interrupts the CPU for every byte.
While execu;ng the ISR, the processor takes about 8μsec for the transfer of
each byte. What is the frac;on of CPU ;me consumed by the I/O device?

32 2

16
 15/09/17

Example 5

• Consider a disk drive with 16 surfaces, 512 tracks per surface, and 512
sectors per track, 1024 bytes per sector, and a rota;on speed of 3600 rpm.
The disk is operated in cycle stealing mode whereby whenever one 4-byte
word is ready, it is sent to memory. Similarly for wri;ng, the disk interface
reads a 4-byte word from memory in each DMA cycle. The memory cycle
;me is 40 nsec. Find the maximum percentage of ;me that the CPU gets
blocked during DMA opera;on.

33 2

Example 6

• A hard disk is connected to a 50 MHz processor through a DMA controller.

Assume that the ini;al set-up ;me for a DMA transfer takes 2000 clock cycles
for the processor, and also assume that the handling of the interrupt on DMA
comple;on requires 1000 clock cycles for the processor. The hard disk has a
transfer rate of 4000 KB/s and average block size transferred is 8 KB. What
frac;on of the processor ;me is consumed by the disk, assuming that data
are transferred only during the idle cycles of the CPU?

34 2

17
 15/09/17

Example 7

• A device with transfer rate of 20 KB/s is connected to a CPU. Data is

transferred byte wise. Let the interrupt overhead be 6 μsec. The byte transfer
;me between the device interface register and CPU or memory is negligible.
What is the minimum performance gain of opera;ng the device under
interrupt-driven mode?

35 2

END OF LECTURE 50

36 2

18
 15/09/17

Lecture 1: EVOLUTION OF COMPUTER SYSTEM

Lecture
Lecture 51: BUSOF
1: EVOLUTION STANDARDS
COMPUTER SYSTEM

DR. KAMALIKA DATTA

PROF.
DR.INDRANIL
KAMALIKASENGUPTA
DATTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, IIT MEGHALAYA
KHARAGPUR
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

37 2

Introduc)on
• A bus is a collec;on of wires and connectors through which the data is
transmifed.

• Bus = address bus + data bus

– Data bus: transfers actual data.
– Address bus: transfers informa;on about data and where it should go.

19
 15/09/17

• Bus Protocol:
– Rules determining the format and transmission of data through bus.
• Parallel Bus:
– Data transmifed in parallel.
– Advantage: It is fast.
– Disadvantage: High cost for long distance communica;on, inter-line interference
at high frequency.
• Serial Bus:
– Data transmifed serially.
– Advantage: low cost for long distance communica;on, no interference.
– Disadvantage: Slow.

39 2

• Bus Master and Slaves:

– The device that controls the bus is called master; others are slaves.
• Local or System Bus:
– Bus that connects CPU and memory.
• Front-Side Bus:
– Original concept: connects CPU to components.
– Modern Intel architecture: connects CPU to NorthBridge chipset.
• Back-Side Bus:
– Connects CPU to L2 cache.
• Memory Bus:
– Connects NorthBridge chipset to memory.

40 2

20
 15/09/17

• AGP Bus:
– Connects NorthBridge chipset to the GPU.
• ISA, PCI, Firewire, USB, PCI-Express Bus:
– Connects motherboard to peripherals.

41 2

Source: Intel Corp.

42 2

21
 15/09/17

Some Features of a Bus

• Bus width:
– Number of wires available in the bus for transferring data.
• Bus bandwidth:
– Total amount of data that can be transferred over the bus per unit
;me.

43 2

Bus Width (bit) Bandwidth (MB/s)

16-bit ISA 16 15.9
EISA 32 31.8
PCI 32 127.2
64-bit PCI 2.1 (66 MHz) 64 508.6
AGP 8x 32 2,133
USB 2 1 Slow-Speed: 1.5 Mbit/s
Full-Speed: 12 Mbit/s
Hi-Speed: 480 Mbit/s
Firewire 400 1 400 Mbit/s
PCI-Express 16x version 2 16 8,000

44 2

22
 15/09/17

Synchronous versus Asynchronous Bus

• Synchronous Bus:
– There is a common clock between the sender and the receiver that
synchronizes bus opera;on.
• Asynchronous Bus:
– There is no common clock.
– Bus master and slave have to handshake during the process of
communica;on.

45 2

Example 1: Synchronous Memory Read

1. CPU places the address of the memory loca;on on address lines

46 2

23
 15/09/17

2. Aler the voltages on the address line have become stable, CPU
asserts MREQ and RD lines

47 2

3. Memory controller accesses memory loca;on and loads the data

on the data lines

48 2

24
 15/09/17

4. CPU reads data from the data lines, and then de-asserts MREQ
and RD to release the bus

49 2

Example 2: Asynchronous Memory Read

1. CPU puts the address of the memory loca;on on the address lines

50 2

25
 15/09/17

2. Aler the voltages on the address line have become stable, CPU
asserts MREQ and RD lines

51 2

3. CPU asserts the MSYN line. Memory controller accesses memory.

52 2

26
 15/09/17

4. Memory controller loads data from memory to data lines, and asserts SSYN.

53 2

5. CPU takes data from the data lines, and then de-asserts MREQ, RD and MSYN.

54 2

27
 15/09/17

6. Finally, memory controller de-asserts SSYN.

55 2

Bridge-Based Bus Architectures

• System includes a lot of buses that are
segregated by bridges.
• The advantage is that different buses
can operate in parallel.
• Intel follows this kind of architecture.

56 2

28
 15/09/17

Source: Intel Corp.

57 2

END OF LECTURE 51

58 2

29
 15/09/17

Lecture 1: EVOLUTION OF COMPUTER SYSTEM

Lecture
Lecture 52: UNIVERSAL
1: EVOLUTION OFSERIAL BUSSYSTEM
COMPUTER (USB)

DR. KAMALIKA DATTA

PROF.
DR.INDRANIL
KAMALIKASENGUPTA
DATTA
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, IIT MEGHALAYA
KHARAGPUR
DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING, NIT MEGHALAYA

59 2

Universal Serial Bus (USB)

• USB is the most popular external bus standard in use today.
– Allows connec;on of almost all types of peripheral devices.
– USB interfaces exist today in keyboard, mouse, printer, scanner, mobile
phones, disks, pen drives, camera, etc.
• Facilitates high-speed transfer of data.
– USB 1.1 (1998): up to 12 Mbps
– USB 2.0 (2000): up to 480 Mbps
– USB 3.0 (2008): up to 5 Gbps
– USB 3.1 (2013): up to 10 Gbps

60 2

30
 15/09/17

History of USB
• A group of 7 companies (Compaq, DEC, IBM, Intel, Microsol, NEC, Nortel)
ini;ated the development of the USB standard in 1994.
• Main Goal:
– Simplify the problem of connec;ng external devices by replacing the variety of
connectors that were available earlier.
– Simplify solware configura;on of the connected devices.
• The first USB version 1.0 appeared in 1996, which was followed by many
other genera;ons, with USB 3.1 being the latest.

61 2

• How are data transmifed?

– Data are transmifed serially using differen;al NRZI encoding.
Bit to be sent Previous line state New line state
0 0 1
0 1 0
1 0 0
1 1 1
– Bit stuffing is used to ensure minimum bit toggle frequency during
communica;on.
• A 0 is inserted whenever a sequence of 6 1’s is encountered.
• 1101 1111 1101 0100 à 1101 1111 10101 0100

62 2

31
 15/09/17

USB Connectors
• There are two pre-defined connectors in any USB system.
– The Type-A plug has an elongated cross-sec;on, inserts into a Type-A
receptacle on a downstream port on a USB host or hub, and carries both
power and data.
– The Type-B plug has a near square cross-sec;on with the top exterior corners
beveled. As part of a removable cable, it inserts into an upstream port on a
device (e.g. printer).
• For connec;ng smaller devices like mobile phones and digital cameras,
mini and micro USB connectors have also been developed.

63 2

Mini
Type-A

Type-B Micro

64 2

32
 15/09/17

Bus CPU Bus Memory Bus

Main
Hierarchy CPU Memory

System Bus
USB Internal Bus and i/f
Host Computer
USB Host
Hub

USB External Bus and i/f

External Device USB Device

65 2

Bus Topology

• Connects computer (host) to peripheral devices.

– Largely successful in replacing serial and parallel ports.
• Tiered Star Topology:
– All devices are linked to a common point called the root hub.
– The USB specifica;on supports up to 127 different devices.
– 4-wire cable is used to interconnect – power, ground, and two differen;al
signaling lines.
– USB is a polled bus – all transac;ons are ini;ated by the host.

66 2

33
 15/09/17

Host Root
Hub D

FuncJonal USB
Device

Hub Hub Hub

D Hub D D

D D

67 2

• USB Host:
– It is a device that controls the en;re system (usually a computer).
– It processes data arriving to and from the USB port.
– It contains a sophis;cated set of solware drivers.
• Drivers schedule and compose USB transac;ons.
• Access individual devices to obtain configura;on informa;on.
– Solware dependence of USB systems make it difficult to use on stand-
alone systems (with no OS support).
– The physical interface to USB Root Hub is called the USB Host Controller.

68 2

34
 15/09/17

• USB Hub:
– It checks for new devices and maintains status informa;on of child
devices.
– It serves as repeater, boos;ng strength of upstream and downstream
signals.
– It electrically isolates devices from one another, thus allowing an
expanded number of devices.
• Allows malfunc;oning devices to be removed.
• Allows slower devices to be placed on a faster branch.
– Can be purchased as stand-alone devices.

69 2

• USB Devices:
– All func;onal USB devices are slaves; only responding to data reads or
writes, never ini;a;ng any.
– May indicate a need to transmit or receive data through polling.
– Contain registers that iden;fy relevant configura;on informa;on.
– Exist in conjunc;on with corresponding set of solware drivers inside
the host system.

70 2

35
 15/09/17

USB SoYware Interfaces

Host System USB Device

Client Solware Func;on

USB System Solware USB Logical Device

USB Host Controller USB Bus Interface

71 2

• The Client SoMware determines what transac;ons are required with a

given device.
– What data is to be transferred?
• Scheduling and configura;on of data transfers in completed in USB System
SoMware level.
– When and how olen data is to be transferred?
• Data transfers are composed and regulated at the USB Host Controller
level.
– How are data to appear to the func;onal device?
– How does system keep track of data sent and received?

72 2

36
 15/09/17

Future of USB
• USB Type-C Plug:
– They are about the same size as micro USB connectors.
– Can deliver power output of 20 volts and 5 amps (100 wafs).
• Can be used for charging laptops and phones.
• Thunderbolt 3 port uses the same port type as USB-C.
– Peak speed up to 40 Gbps.
– Available on Apple machines.

73 2

END OF LECTURE 52

74 2

37