UNIT 8

I/P O/P Organization

Topics to be covered
• Input-Output Interface,
• Asynchronous Data Transfer,
• Modes Of Transfer,
• Priority Interrupt,
• Input-Output Processor (IOP),
• CPUIOP Communication,
• Serial communication.
Input-Output Interface
 Input-output interface provides a method for transferring information
between internal storage and external I/O devices.
 Peripherals connected to a computer need special communication links for
interfacing them with
the central processing unit.
 The purpose of the communication link is to resolve the differences that
exist between the central computer and each peripheral.The major
differences are:
1. Peripherals are electromechanical and electromagnetic devices and their
manner of operation is different from the operation of the CPU and memory,
which are electronic devices. Therefore, a conversion of signal values may
be required.
2. The data transfer rate of peripherals is usually slower than the transfer
rate of the CPU, and consequently, a synchronization mechanism may be
needed.
To resolve these differences,
computer systems include
special hardware components
between the CPU and
peripherals to supervise and
synchronize all input and
output transfers. These
components are called
interface units because they
interface between the
processor bus and the
peripheral device.
Input-Output Interface
 In addition to communicating with I/O, the processor must communicate with the memory
unit. There are three ways that computer buses can be
used to communicate with memory and I/O:
1. Use two separate buses, one for memory and the other for I/O.
2. Use one common bus for both memory and I/O but have separate control lines for each.
3. Use one common bus for memory and I/O with common control lines.
Asynchronous Data Transfer

• Section - 1
Asynchronous Data Transfer
 Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to
indicate the time at which data is being transmitted.
 Two ways of achieving
1. Strobe
2. Handshaking
Strobe Method
 1.1 Source initiated  1.2 Destination initiated
Strobe Strobe
Data Data
Source Bus Destinatio Source Bus Destinatio
unit Strob Strob
n unit unit n unit
e e

Dat Valid Dat Valid

a Data a Data

Strob Strob
e e
Strobe method limitation??
 Source never know weather data received by destination or not
2.1 Source initiated Handshake
Source Destination
Data unit data on unit
Place
Source bus
Data Destinati bus.
unit valid
Data on unit Enable data
Accept data from
accepted valid.
bus.
Enable data
Valid accepted.
Data Data Disable data
bus valid.
Invalidate data
on bus. Disable data
Data accepted.
valid Ready to accept
data (initial
state).
Data
accepted
2.2 Destination initiated Handshake
Data
Source bus
Data Destinatio Source Destination
unit valid for
Ready n unit unit unit
data Ready to
accept data.
Place data on Enable Ready
bus. for data.
Ready for Enable data
data valid.
Accept data
from bus.
Data Disable data Disable Ready
valid valid. for data.
Invalid data
Valid on bus
Data Data (initial state).
bus
Asynchronous Serial Transfer
 Rules for transmission
1. When a character is not being sent, the line is kept in the 1-state.
2. The initiation of a character transmission is detected from the start bit, which is
always 0.
3. The character bits always follow the start bit.
4. After the last bit of the character is transmitted, a stop bit is detected when the line
returns to the 1-state for at least one bit time.

1 1 0 0 0 1 0 1

Star Sto
Character
t p
bit
bit bits
Modes Of Transfer

• Section - 2
Modes of Transfer
 Data transfer between the central computer and I/O devices may be
handled in a variety of modes.
 Some modes use the CPU as an intermediate path; others transfer the
data directly to and from the memory unit.
 Data transfer to and from peripherals may be handled in one of three
possible modes:
1. Programmed I/O
2. Interrupt-initiated I/O
3. Direct memory access (DMA)
Programmed
I/O Read data register

Check flag bit

= Fla
Data Interfa 0 g
I/O
bus ce bus =
Address Data
register I/O 1
CPU bus Data Read status register
I/O valid device
read Status
I/O F Data
register Transfer data to memory
write accepted

Operatio
n no
complet
e?
ye
s
Continue with program
Programmed I/O limitation?
 CPU need to check every time that operation is completed or not in result
wasting time and do not perform any other task
Interrupt-initiated I/O
 An alternative to the CPU constantly monitoring the flag is to let the
interface inform the computer when it is ready to transfer data.
 While the CPU is running a program, it does not check the flag.
 However, when the flag is set, the computer is momentarily interrupted
from proceeding with current program and is informed of the fact that the
flag has been set.
 The CPU deviates from what it is doing to take care of the input or output
transfer.
 After the transfer is completed, the computer returns to the previous
program to continue what it was doing before the interrupt.
Two method to accomplish this
 Non vectored interrupt – manually need to assign address with branch
instruction
 Vectored interrupt – vector means address,by default address is shared on
which location need to transfer when interrupt occur
Priority Interrupt

• Section - 3
Priority Interrupt (Daisy-Chaining Technique)
 Determines which interrupt is to be served first when two or more requests are
made simultaneously
 Also determines which interrupts are permitted to interrupt the computer while
another is being serviced.
 Higher priority interrupts can make requests while servicing a lower priority
interrupt. Processor data
bus
VAD VAD VAD
1 2 3
Device Device Device
P 1 P P 2 P P 3 P
I O I O I O To
next
device
Interrupt
IN
request
T
CP
Interrupt U
acknowledge INTAC
K
One stage of
the daisy-
chain
priority
arrangement
DMA (Direct Memory Access)

• Section - 4
DMA (Direct Memory Access)
 The transfer of data between a fast storage device such as magnetic disk
and memory is often limited by the speed of the CPU.
 Removing the CPU from the path and letting the peripheral device manage
the memory buses directly would improve the speed of transfer.
 This transfer technique is called direct memory access (DMA).
 During DMA, CPU is idle and has no control of the memory buses.
 A DMA controller takes over the buses to manage the transfer directly
between the I/O device and memory.

ABUS Address bus High-

Bus request BR impedance
DBUS Data bus
CPU (disabled)
RD Read when BG is
Bus granted BG WR Write enabled
DMA Controller
DMA Controller Address bus
 DMA controller
- Interface Data bus
Data bus Address bus
which allows buffers buffers
I/O transfer

Internal Bus
directly Address register
between DMA Select DS Word count
Memory and Register select RS register
Device, freeing Read RD Contr Control register
CPU for other Write WR ol
tasks Bus request BR logic
Bus grant BG
 CPU initializes DMA Request
Interru Interrupt
DMA Controller pt DMA Acknowledge to I/O device
by sending
memory
address and
the block size
Input-Output Processor (IOP)

• Section - 5
Input-Output Processor (IOP)

Central
Processing
Unit (CPU)

Memory Bus
Peripheral Device
Memory P P P P
Unit D D D D

Input-Output
Processor
I/O Bus
 CPU IOP
operations operations
CPU – IOP Send instruction to
test IOP path
Transfer status
word to memory
Communicat location
If status OK, send
ion start I/O
instruction to IOP Access memory
for IOP program

CPU continues Conduct I/O

with another transfers using
program DMA; prepare
status report
I/O transfer
completed;
Request IOP status interrupt CPU
Transfer status
word to memory
Check status word location
for correct transfer

Contin
Serial communication.
• A data communication processor is an I/O processor that distributes and collects data
from many remote terminals connected through telephone and other
communication lines. It is a specialized I/O processor designed to communicate
directly with data communication networks.
• A communication network may consist of any of a wide variety of devices, such as printers,
interactive display devices, digital sensors, or a remote computing facility.
• With the use of a data communication processor, the computer can service fragments of
each network demand in an interspersed manner and thus have the apparent behavior of
serving many users at once. In this way the computer is able to operate efficiently in a
time-sharing environment.
• The most striking difference between an I/O processor and a data communication
processor is in the way the processor communicates with the I/O devices. An I/O processor
communicates with the peripherals through a common I/O bus that is comprised of many
data and control lines.
Serial communication.
• All peripherals share the common bus and use it to transfer information to and from the I/O
processor. A data communication processor communicates with each terminal through a
single pair of wires. Both data and control information are transferred in a serial fashion
with the result that the transfer rate is much slower.
• The task of the data communication processor is to transmit and collect digital information
to and from each terminal, determine if the information is data or control and respond to
all requests according to predetermined established procedures. The processor, obviously,
must also communicate with the CPU and memory in the same manner as any I/O
processor.
• The communication lines, modems, and other equipment used in the
• transmission of information between two or more stations is called a data link. The orderly
transfer of information in a data link is accomplished by means of a protocol .
• Protocols are divided into two major categories according to the message- framing
technique used.
Serial communication.
 The character-oriented protocol is based on the binary code of a character set. The
code most commonly used is ASCII (American Standard Code for Information
Interchange). The character-oriented protocol was originally developed to
communicate with keyboard, printer, and display devices that use alphanumeric characters
exclusively. As the data communication field expanded, it became necessary to
transmit binary information which is not ASCII text.
 The bit-oriented protocol does not use characters in its control field and is
independent of any particular code. It allows the transmission of serial bit stream
of any length without the implication of character boundaries.