Analysis and Design of Analog Integrated Circuits

Lecture 1

Overview of Course, NGspice Demo,

Review of Thevenin/Norton Modeling

Michael H. Perrott
January 22, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Analog Electronics are Pervasive in our Lives
Smart Fiber Optic Data Medical
Phones Communication Instruments

Automotive Monitoring
Instruments & Control

But what do analog circuits do?

M.H. Perrott 2
 Analog Circuits Process “Real World” Signals
 Wireless systems:
- Cell phones, wireless LAN, computer peripherals
Electrical Circuits Electromagnetic Waves
 Optical networks:
- High speed internet
Electrical Circuits Light
 Micromechanical devices:
- Resonators, accelerometers, gyroscopes
Electrical Circuits MEMS
 Bio-electrical applications
- Imaging, patient monitoring, drug delivery, neural stimulation
Electrical Circuits Biological Systems
M.H. Perrott 3
 Analog Circuits Allow Interfacing with Digital Processors

 Sensor devices create analog signals which are responsive

to some “real world” signal such as light, temperature, etc.
 Signal conditioning is used to amplify and filter signals so
that they may be more easily digitized
 Analog-to-Digital conversion samples the analog signal and
then generates its corresponding digital representation
 Digital processors run algorithms on the digital signal
 Communication interface outputs the key signal information
M.H. Perrott 4
 Modern Approach: Mixed-Signal Circuit Design

 Traditional interface

Digital Analog Real

Circuits Circuits World

 The mixed signal approach

Digital Analog Real

Circuits Circuits World

Lower power, smaller size, better performing interface

… But we need to understand analog design first!
M.H. Perrott 5
 Basics of Analog Design Methodology

System Schematic Level Layout of

Architecture Circuit Design Circuits

Ibias M3 M4
M1

M1 M2

R1 R2

 System level – determine specifications that circuit

must achieve
 Schematic level – choose circuit topology and device
sizes and simulate with SPICE
 Layout – draw circuit topology which matches
schematic (this is sent to a fabrication plant to be made)
M.H. Perrott 6
 Example 1: A 3 Gb/s Limit Amplifier for PON Networks

Settling time (< 1 microsecond) Eye Diagram

E.A. Crain, M.H. Perrott,

JSSC, Feb 2006

M.H. Perrott 7
Example 2: A VCO-Based Analog-to-Digital Converter

M. Park, M.H. Perrott

JSSC, Dec. 2009

Explicit
DWA

 Peak SNDR of 78 dB with

20 MHz bandwidth
 Figure of merit: 330 fJ/step
8
 Example 3: An Optical/Electrical Demodulator and ADC
Custom  ADC FFT of Digitized Output
0
Integrated Circuit
-20
Laser rep. rate:
-40 foffset = 1.35 MHz
969.75 Mhz

Amplitude (dB)
Harmonic due to non-linearity
RF input: -60

1.938 GHz -80

Data rate (GMSK):
-100
100 kb/s
-120
Digitized ADC Output
Σ−Δ ADC
-140
0 1 2 3 4 5
Frequency (MHz)
Pout(t) Pout(t) Vector Signal
Generator Recovered Eye Diagram
1.5 From Digitized Output

Pin(t) I

-1
Optical
1
phase modulator
Ti:sapphire
ML-laser Q

Sagnac-loop π/2 phase -1.5

shift device 0 10 20 30 40
interferometer Time (microseconds) 9
M.H. Perrott
 Example 4: Using Analog Circuits to Change Paradigms
Quartz Oscillators MEMS-based Oscillator

source: www.ecliptek.com

 A part for each frequency  Same part for all frequencies

and non-plastic packaging and plastic packaging
- Non-typical frequencies - Pick any frequency you want
require long lead times without extra lead time

We can achieve high volumes at low cost using IC fabrication

M.H. Perrott 10
 Die Photo for Example 4
M.H. Perrott, et. al., MEMS-based Oscillator
JSSC, Dec. 2010

M.H. Perrott 11
 Key Skills To Be Learned In This Class

 Analyzing transistor level circuits

- Biasing, small signal, frequency response, noise analysis
 Simulating analog circuits
- SPICE simulation and analysis with Matlab
 Understanding basic building blocks
- Amplifiers, current mirrors, samplers
 Understanding analog circuit techniques
- Cascoding, gain boosting, filtering
 Familiarity with analog circuit non-idealities
- Mismatch, offset, noise, nonlinearity
 Putting together larger circuits
- Multi-stage amplifiers, Opamps
 General principles of modeling and synthesis

M.H. Perrott 12
 Prerequisite Skills

 Familiarity with basic circuit elements

- Resistors, capacitors, transistors, diodes
 Circuit network analysis
- KVL, KCL, Superposition, Thevenin and Norton models
 Frequency domain analysis
- Bode plot analysis, Laplace and Fourier transform, basic
understanding of filters (lowpass, highpass, bandpass)
 Classical feedback design
- Black’s formula, stability analysis using phase margin
 Basics of nonlinear circuit analysis
- Biasing, small signal analysis
 Device physics (MIC503)

M.H. Perrott 13
 Class Flow

 Lectures:
- Sundays, Wednesdays from 10:00-11:15 am
 Office hours: Sun 11:30-12:30, Wed 11:30-12:30, By Appt.
 Homework:
- One problem set per week
 Short quizzes (15 minutes at end of lecture):
- Once per week covering homework material
- You are granted one “ignore” credit for these short quizzes
 Full quiz: Wednesday, March 7
 Project: Passed out on April 11, Due May 2
 Final exam: During finals week

M.H. Perrott 14
 Lecture Style and Recommendations

 Lecture notes will have gaps in them that need to be

filled in while you are in class
- Goal is to facilitate learning
- Consider using blank back-side of slides for notes and
then show results in given slide
 If you miss a class, you will need to ask others in
class for their notes
- You can ask me follow up questions once you have
gone through those notes
 As you do each homework, try to fill in to a one page
sheet with the key information that you need to know
to solve the problems
- You will be able to bring this sheet (front and back side)
to the quizzes

M.H. Perrott 15
 Class Policies
 Homework and projects are to be completed individually,
though you are allowed to work with others
- You must specify the names of anyone you work with on
each assignment/project
- You must not show identical work to others for any
assignment/project (i.e., no copying)
 Homework and projects must be turned in at the beginning
of class (i.e., 10:15 am) on their due date
- Reduction of grade by 10% for every day late
 Anything after beginning of class counts as at least one day
- You will have 7 days total of “late” day credits for homeworks
and projects (not 7 days for homeworks, 7 days for projects)
 No reduction of grade when applying this credit – use it wisely
 Absolutely no copying or collaborating during a quiz/final
- One summary sheet allowed during quizzes, two during final
M.H. Perrott 16
 Homework and Project Clarity

 You must present your work clearly

- Box answers
- Show supporting work before the boxed answer with
clearly shown steps of how you arrived at the answer
- Grade reduction will occur for sloppy work
 Example of correct presentation
Problem 1:
Drawing

Equation(s)

Answer = ……….

M.H. Perrott 17
 Simulation Tools Will Be Run On Your Laptop

 NGspice will be the main simulation tool

- Windows only, download CppSim onto your laptop from
http://www.cppsim.com/download
- Go through the Ngspice Primer Within CppSim manual
at http://www.cppsim.com/manuals
 Octave will be used to run postprocessing on Ngspice
results
- Download from http://octave.sourceforge.net/
- Be sure to add most toolboxes except for oct2map
 Causes an error that can fixed by running:
 pkg rebuild -noauto oct2mat

Short, in-class demo now…

M.H. Perrott 18
 Basics of One-Port Modeling

Linear Network
Thevenin Equivalent Norton Equivalent
Zth

Vth Ith Zth

 Vth computed as open circuit voltage at port nodes

 Ith computed as short circuit current across port
nodes
 Zth computed as Vth/Ith
- All independent voltage and current sources are set to
zero value

M.H. Perrott 19
 Thevenin/Norton Modeling: Example 1
From Electric Circuits 5kΩ 2.5kΩ
By James Nilsson a

Vab
5V 5kΩ 1mA
b

 Compute Thevenin and Norton models…

M.H. Perrott 20
 Thevenin/Norton Modeling: Example 2
From Electric Circuits 2kΩ
By James Nilsson a
i1
5V 3v1 20i1 v1 25Ω
b

ix
 Compute ix and Thevenin and Norton models…

M.H. Perrott 21
 Analysis and Design of Analog Integrated Circuits
Lecture 2

Two-Port Models, Frequency Response

Michael H. Perrott
January 25, 2011

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Review: Basics of One-Port Modeling

Linear Network
Thevenin Equivalent Norton Equivalent
Zth

Vth Ith Zth

 Vth computed as open circuit voltage at port nodes

 Ith computed as short circuit current across port
nodes
 Zth computed as Vth/Ith
- All independent voltage and current sources are set to
zero value

M.H. Perrott 2
 Basics of Two-Port Modeling (Unilateral)

Linear Network  We now include a

Zs dependent current or
Vin
voltage source
ZL
 Zin
- Solve using 1-Port
No Independent analysis at input
Sources
 Zout
- Solve using 1-Port
analysis at output
Zs
with V1 = 0
Vin V1 Zin GmV1 Zout ZL  GM
- Short circuit output
current as a function
OR of V1
Zs Zout  Av
Vin V1 Zin AvV1 ZL
- Open circuit output
voltage as a function
of V1

M.H. Perrott 3
 Analysis of Cascaded Blocks
Block 1 Block 2 Block 3
Linear Network Linear Network Linear Network

Vin Va Vb Vc ZL

No Independent No Independent No Independent

Sources Sources Sources

Vin Zin GmVin Zout Va Zin GmVa Zout Vb Zin GmVb Zout Vc ZL

Zout,effective

Vth,effective Vb Zin,effective

Analysis carried out without solving simultaneous equations!

M.H. Perrott 4
 Problem: Most Circuits are Very Nonlinear!
Block 1 Block 2 Block 3

NonLinear NonLinear NonLinear

Vin Va Vb Vc ZL
Network Network Network

No Independent No Independent No Independent

Sources Sources Sources

 Thevenin/Norton modeling only applies to linear

networks
 Direct analysis of nonlinear networks is challenging

Can we still leverage two-port modeling?

M.H. Perrott 5
 Small Signal Modeling Allows Us to Linearize
Block 1 Block 2 Block 3

NonLinear NonLinear NonLinear

Vin Va Vb Vc ZL
Network Network Network

No Independent No Independent No Independent

Sources Sources Sources

Linearization
Block 1 Block 2 Block 3
Linear Network Linear Network Linear Network

Vin Va Vb Vc ZL

No Independent No Independent No Independent

Sources Sources Sources

Small signal model is only valid about a specific operating point

M.H. Perrott 6
 Small Versus Large Signal Modeling
NonLinear Gain Block

Vout

Vin Vout ZL

Vin

 Sketch Vout versus Vin as the amplitude of Vin is increased

M.H. Perrott 7
 Impact of Operating Point on Small Signal Modeling
NonLinear Gain Block

Vout

Vout_dc
Vin Vout ZL

Vin
Vin_dc

 Sketch Vout versus Vin as the DC operating point is changed

M.H. Perrott 8
 Achieving a Small Signal Model
NonLinear Gain Block

Vout

Vout_dc
Vin Vout ZL

Vin
Vin_dc

 Create a two port model of the above block

M.H. Perrott 9
 Including Impedances in Two-Port Models

Zs Zout

Vin V1 Zin A v V1 ZL Vout

 Compute Vout as a function of Vin

M.H. Perrott 10
 Example of Two-Port Derivation
Device Small Signal Model
RG g d

vin rin vgs gmvgs -gmbvs ro RD vout

vs RS

g d
RG

Vin V1 Zin GmV1 Zout RD vout

 Compute Zin, Zout, and Gm

- Assume r in = infinity, gmb = 0
M.H. Perrott 11
 Frequency Domain Modeling of Impedances

 Determine Laplace Transform of Impedances Below:

L R C

R
Zin C C R Zout

M.H. Perrott 12
 Example: Transfer Function of Two-Port Circuit
Rsrc g d

Vin V1 Cin GmV1 ro Cload vout

 Derive the transfer function Vout(s)/Vin(s)

 Label the poles and zeros of the transfer function

M.H. Perrott 13
 Frequency Response

 Frequency response is readily derived from a transfer

function:
- For w (rad/s), you substitute s = jw
- For f (Hz), you substitute s = j2f
- Note that j = sqrt(-1)
 Example, for the transfer function on the previous
page, the frequency response (in f (Hz)) is:

M.H. Perrott 14
 Bode Plot Basics

 The magnitude and phase of the frequency response

is often depicted in the form of a Bode plot
 Example:

- Log of magnitude (dB):

 Taking the log allows the poles and zeros to be plotted

separately and then added together
- Phase:

 Phase of poles and zeros can also be plotted separately

and then added together

M.H. Perrott 15
 Plotting the Magnitude of Poles

 Plot the magnitude response of pole wp1

- For w << w p1:

- For w >> w p1:

20log|H(ω)|

0 dB ω
ωp1
-20 dB/decade

M.H. Perrott 16
 Plotting the Magnitude of Zeros

 Plot the magnitude response of pole wz

- For w << w :
z

- For w >> w :
z

20log|H(ω)|

20 dB/decade

0 dB ω
ωz
M.H. Perrott 17
 Putting It All Together

 Example Frequency Response:

Vout (w) 1 + jw/wz
H(w) = =
Vin (w) (1 + jw/wp1 )(1 + jw/wp2 )
- Assume w z << wp1 << wp2

20log|H(ω)| 0 dB/dec

20 dB/dec -20 dB/dec

0 dB ω
ωz ωp1 ωp2

 What happens if wp1 << wz << wp2 ?

M.H. Perrott 18
 Changing the Order of Poles and Zeros

 Example Frequency Response:

Vout (w) 1 + jw/wz
H(w) = =
Vin (w) (1 + jw/wp1 )(1 + jw/wp2 )
- Assume w p1 << wz << wp2
20log|H(ω)|

0 dB
-20 dB/dec

0 dB/dec

-20 dB/dec

ω
ωp1 ωz ωp2
M.H. Perrott 19
 Changing the DC Gain from 1 to K

 Example Frequency Response:

Vout (w) 1 + jw/wz
H(w) = =K
Vin (w) (1 + jw/wp1 )(1 + jw/wp2 )
- Assume w p1 << wz << wp2
20log|H(ω)|

20log(K) dB
-20 dB/dec

0 dB/dec

-20 dB/dec

ω
ωp1 ωz ωp2
M.H. Perrott 20
 Analysis and Design of Analog Integrated Circuits
Lecture 3

Large Signal Modeling of CMOS Transistors

Michael H. Perrott
January 29, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Introducing CMOS Devices
NMOS PMOS

(Bulk) (Source) (Gate) (Drain) (Bulk) (Source) (Gate) (Drain)

p+ n+ n+ n+ p+ p+
p- n-
(Bulk) (Bulk)
p-

(Drain) (Source)
D S

(Gate) G B (Bulk) (Gate) G B (Bulk)

S D
(Source) (Drain)

 CMOS: Complementary Metal Oxide Semiconductor

- Current flow through channel between Drain and Source
is controlled by Gate
- Complementary: both PMOS and NMOS are available
M.H. Perrott 2
 Simplified MOS Symbol for Typical Bulk Connections
NMOS PMOS

(Bulk) (Source) (Gate) (Drain) (Bulk) (Source) (Gate) (Drain)

Gnd Vdd

p+ n+ n+ n+ p+ p+
p- n-
(Bulk) (Bulk)
p-

(Drain) (Source)
D S

(Gate) G (Gate) G

S D
(Source) (Drain)

 Bulk silicon below the channel under the gate also has an
impact on the channel current
- We often tie the Bulk to Gnd/Vdd for NMOS/PMOS devices
 In such case, the symbol does not include the bulk terminal 3
M.H. Perrott
 Symbol Notation Often Includes Size

W
M1
W
L
L

 The designer is generally free to choose the width (W)

and length (L) of the device
- Wider width is often chosen to achieve higher channel
current for a given gate bias voltage
- Longer length is often avoided since it lowers the channel
current and decreases the operating speed of the device
 The minimum length for the gate is often used to define the
process name (i.e., 0.18u CMOS or 0.13u CMOS)
 Longer length is used in cases where better matching or
high resistance is desired
M.H. Perrott 4
 Channel Current as a Function of Gate Voltage
Id Vds > ΔV
d
Id
Note that we designate
g
M1 V as the overdrive voltage
Vgs s Id_op and that V = Vdsat
in strong inversion
Vgs
NMOS VTH Vgs_op

ΔV
 If Vgs < VTH, then current density Id/W is small
- The device is in the subthreshold operating region
 For Vgs > VTH, then Id/W is much larger
- The device is in strong inversion
- If V > V, then I is relatively independent of V
ds d ds
 The device is in the saturation operating region
- If V < V, then I is strongly dependent on V
ds d ds
 The device is in the triode operating region
M.H. Perrott 5
 PMOS Devices are Complementary to NMOS Devices
Id Vsd > ΔV
Vsg s
M2
g
d Id Id_op

Vsg
PMOS -VTH Vsg_op

ΔV

 Same observations and definitions apply to PMOS

- However, voltage and current signs are flipped
 Note that Vsg = -Vgs, Vsd = -Vds
 Note that Id as defined above for PMOS is in the
opposite direction as for NMOS
 Note that VTH becomes negative

M.H. Perrott 6
 Examine MOS Behavior As Vds is Increased
Triode ID

VGS
G Overall I-V Characteristic
VDS=0
S D

Cchannel = Cox(VGS-VTH)
ID

Pinch-off ID Saturation
Pinch-off
VGS
G
VD=ΔV
S D Triode

VDS
Saturation ΔV
ID

VGS
G
VD>ΔV
S D

How does VGS influence Id in the above curve ? 7

M.H. Perrott
 MOS Behavior Is A Function of Vgs and Vds

Overall I-V Characteristic

ID

Saturation
Pinch-off
See page 15-23 of Razavi…
Triode
ΔV Increasing Vgs

VDS

M.H. Perrott 8
 MOS Current Equations in Triode and Saturation Regions
Triode ID
ID = μnCox W (VGS - VTH - VDS/2)VDS
VGS L
G
VDS=0 for VDS << VGS - VTH
S D
ID μnCox W (VGS - VTH)VDS
L
Cchannel = Cox(VGS-VTH)

Pinch-off ID

VGS ΔV = VGS-VTH
G
VD=ΔV 2IDL
S D ΔV =
μnCoxW

Saturation ID

VGS 1 μ C W 2
G ID = n ox (VGS-VTH) (1+λVDS)
VD>ΔV 2 L
S D (where λ corresponds to
channel length modulation)

M.H. Perrott 9
 The Issue of Velocity Saturation

 When in saturation, the MOS current is calculated as

 Which is really

- Here V dsat,l is the saturation voltage at a given length

 It may be shown that

- If V gs-VTH
approaches LEsat in value, then
 We say that the device is in velocity saturation
 The current becomes linearly related to Vgs-VTH

M.H. Perrott 10
 Example: Current Versus Voltage for 0.18 Device

Id
Vgs
M1 W 1.8μ
= Id versus Vgs
L 0.18μ 1.4

1.2

Id (milliAmps) 1

0.8

0.6

0.4

0.2

0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
V (Volts)
gs
M.H. Perrott 11
 The Tricky Issue of Modeling MOS Devices

 The device characteristics of modern CMOS devices

lead to complicated analytical models
- This creates challenges for achieving accurate hand
calculations with reasonable effort
 Hand calculations are essential in achieving deeper
understanding and intuition of circuit and device
behavior
- Simple hand calculations lack accuracy
- Detailed hand calculations often do not yield the desired
insight and understanding to make them worthwhile
 A typical compromise
- Assume simple models for hand calculations
- Use SPICE to get a more accurate picture of the actual
circuit and device characteristics and performance

M.H. Perrott 12
 What is the Key Role of Large Signal Calculations?

 In analog circuits, we are often focused on amplifiers in

which the small signal behavior is of high importance
- Large signal calculations lead to the operating point
information of the circuit which is used to determine the
small signal model of the device
 Example amplifier circuit:

Small Signal Analysis Steps

ID RD
1) Solve for bias current Id
RG 2) Calculate small signal
vout parameters (such as gm, ro)
vin
3) Solve for small signal response
Vbias RS
using transistor hybrid-π small
signal model

M.H. Perrott 13
 A Key Small Signal Parameter: Transconductance
Id Vds > ΔV
d
Id
g
M1
ΔId
Vgs s Id_op gm =
ΔVgs
Vgs_op
Vgs
NMOS VTH Vgs_op

ΔV
 Transconductance from input gate voltage, Vgs, to
channel current, Id, is very important for amplifier circuits
- Assuming device is in saturation:

M.H. Perrott 14
 A Key Small-Signal Nonideality: Output Resistance
ID

Saturation
Pinch-off
ΔId
gds =
ΔVds
Triode Vds_op

Vds
ΔV Vds_op
 Ideally, Id would not change with Vds when the device is
in saturation
- Practical CMOS transistors exhibit I dependence on V
d ds
due to channel length modulation
- The parameter  is often used to characterize this effect

M.H. Perrott 15
 Another Non-Ideality: Back-Gate Effect
NMOS PMOS

(Bulk) (Source) (Gate) (Drain) (Bulk) (Source) (Gate) (Drain)

Gnd Vdd

p+ n+ n+ n+ p+ p+
p- n-
(Bulk) (Bulk) p-
 The threshold voltage of the device, VTH, is dependent on
the potential between the source and bulk

- This implies that changes in the source node voltage, V , s

lead to changes in the channel current, Id
 We model this effect as backgate transconductance, gmb

- MIC503 will provide details (also see pages 34-36 of Razavi)

M.H. Perrott 16
 MOS DC Small Signal Model

 Assuming transistor is in saturation:

- Note that designers often determine g mb impact from SPICE

RD RD
ID
RG
RG

vgs gmvgs -gmbvs ro

RS

gm = μnCox(W/L)(VGS - VTH)(1 + λVDS)

vs RS
= 2μnCox(W/L)ID (assuming λVDS << 1)

γ gm 2qεsNA
gmb = where γ =
See Chapter 2 of Razavi 2 2|ΦF| + VSB Cox
for more discussion of In practice: gmb = gm/5 to gm/3
these formulas
1
ro =
λID 17
M.H. Perrott
 MOS DC Small Signal Model

 Assuming transistor is in triode region:

- The channel of the device can be approximated as a
resistor whose value depends on the DC operating point
of Vgs

RD RD
ID
RG
RG

vgs rds

RS

1
vs RS rds =
μnCox(W/L)(VGS - VTH)

M.H. Perrott 18
 Example: Determine V and Operating Region (NMOS)

 Assume VTHn = 0.5V

1V 0.2V 1V
0.2V 1V 0.7V

ΔV = ΔV = ΔV =
Region = Region = Region =

1V 0.2V 1V
0.2V 1V 0.7V

0.4V 0.4V 0.4V

ΔV = ΔV = ΔV =
Region = Region = Region =
M.H. Perrott 19
 Example: Determine V and Operating Region (PMOS)

 Assume VTHp = -0.5V

1.3V 1.3V 1.3V

0.5V 0.9V 0.5V

0.7V 0.7V 1.1V

ΔV = ΔV = ΔV =
Region = Region = Region =

1.2V 0.8V 1.3V

0.5V 0.9V

1.3V 0.7V 1.1V

ΔV = ΔV = ΔV =
Region = Region = Region =
M.H. Perrott 20
 Example: Determine Operating Region of M1 and M2

 Assume VTHn = 0.5V, VTHp = -0.5V, nCox = 50A/V2,

pCox = 20A/V2,  = 0, and M1 and M2 have the same
value of W and L 1.3V
M2
vout
Vbias
M1

 Determine operating region for M1 and M2 assuming:

-V bias = 1.2
-V bias = 0.2
-V bias = 0.65

M.H. Perrott 21
 Example: Determine V and Operating Region

 Assume Vbiasp = 0.7V, VTHn = 0.5V, VTHp = -0.5V,

nCox = 50A/V2, pCox = 20A/V2,  = 0
1.3V
3.25u
0.13u
Vbiasp M2
vout
1.3u
0.13u
Vbiasn M1

 Determine Vbiasn such that Vout = 0.5V

- Note that with  = 0, a variety of V solutions will exist for
out
the same Vbiasn – I’m just trying to keep calculations simple
 Determine the resulting operating region of M1 and M2
M.H. Perrott 22
 Analysis and Design of Analog Integrated Circuits
Lecture 4

Small Signal Modeling of CMOS Transistors

Michael H. Perrott
February 1, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Lecture 3 Discussed Large Signal Calculations

 In analog circuits, we are often focused on amplifiers in

which the small signal behavior is of high importance
- Large signal calculations lead to the operating point
information of the circuit which is used to determine the
small signal model of the device
 Example amplifier circuit:

Small Signal Analysis Steps

ID RD
1) Solve for bias current Id
RG 2) Calculate small signal
vout parameters (such as gm, ro)
vin
3) Solve for small signal response
Vbias RS
using transistor hybrid-π small
signal model

M.H. Perrott 2
 A Key Design Parameter is the Sizing of Devices

W
M1
W
L
L

 The designer is generally free to choose the width (W)

and length (L) of the device
- Wider width is often chosen to achieve higher channel
current for a given gate bias voltage
- Longer length is often avoided since it lowers the channel
current and decreases the operating speed of the device
 The minimum length for the gate is often used to define the
process name (i.e., 0.18u CMOS or 0.13u CMOS)
 Longer length is used in cases where better matching or
high resistance is desired
M.H. Perrott 3
 MOS DC Small Signal Model (Saturation Assumed)

RD RD
ID
RG
RG

vgs gmvgs -gmbvs ro

RS

gm = μnCox(W/L)(VGS - VTH)(1 + λVDS)

vs RS
= 2μnCox(W/L)ID (assuming λVDS << 1)

γ gm 2qεsNA
gmb = where γ =
2 2|ΦF| + VSB Cox
In practice: gmb = gm/5 to gm/3

1
ro =
λID

 How do we model if device is in the triode region?

M.H. Perrott 4
 CMOS Devices Also Have Capacitance
Top View Side View
ID

VGS E
G
Cov Cov
VD>ΔV
S D W S Cgc D
Cjsb Ccb Cjdb
LD LD
L
B
E E
L junction bottom wall junction sidewall
cap (per area) cap (per length)

Cj(0) Cjsw(0)
source to bulk cap: Cjsb = WE + (W + 2E)
1 + VSB ΦB 1 + VSB ΦB (make 2W for "4 sided"
perimeter in some cases)
Cj(0) Cjsw(0)
drain to bulk cap: Cjsd = WE + (W + 2E)
1 + VDB ΦB 1 + VDB ΦB
2
overlap cap: Cov = WLDCox + WCfringe gate to channel cap: Cgc = C W(L-2LD)
3 ox

channel to bulk cap: Ccb - ignore in this class

M.H. Perrott 5
 MOS AC Small Signal Model (Device in Saturation)

RD
RG

ID RD
Cgd
Cdb
vgs Cgs gmvgs -gmbvs ro
RG

Csb
RS

vs RS

2
Cgs = Cgc + Cov = C W(L-2LD) + Cov
3 ox
Cgd = Cov
Csb = Cjsb (area + perimeter junction capacitance)
Cdb = Cjdb (area + perimeter junction capacitance)

M.H. Perrott 6
 Small Signal Modeling Strategy

 We will focus on the DC Small Signal Model first

- This will allow us to calculate the gain of amplifiers
- This will also allow us to derive Thevenin resistances
 We will later combine this information with the capacitors
within the AC Small Signal Model to estimate frequency
response information
 Homework 1 should have revealed to you how clumsy
the DC Small Signal Model can be in calculations
- We need a more streamlined approach
 Strategy: give up general approach, and focus on
achieving a simpler model that fits a large number of
circuit topologies that we will encounter

M.H. Perrott 7
 Thevenin Modeling of CMOS Transistors

Hybrid-π Model Key Small-Signal Parameters

Rthd RD
RG g d Parameter Strong Inversion Weak Inversion

gm qID
2μnCox(W/L)ID
Rthg vgs nkT
gmvgs -gmbvs ro
γ gm (n-1)qID
gmb
2 2|ΦF| + VSB nkT
s
Rths
vs RS 1 1
ro
λID λID

We will discuss weak inversion

(i.e., subthreshold region) later

 Use the Hybrid- model of transistor to calculate

Thevenin resistances at each transistor node
 Use these Thevenin resistance calculations for many
circuit topologies that we encounter
M.H. Perrott 8
 Thevenin Resistance Expressions

Hybrid-π Model Key Small-Signal Parameters

Rthd RD
RG g d Parameter Strong Inversion Weak Inversion

gm qID
2μnCox(W/L)ID
Rthg vgs nkT
gmvgs -gmbvs ro
γgm (n-1)qID
gmb
2 2|ΦF| + VSB nkT
s
Rths Note: gmb = 0
vs RS 1 1
ro
if RS=0 or Vsb=0 λID λID


Thevenin Resistances Exact
Rth = ro (1+(gm+gmb)RS)+RS
Thevenin resistances
d

RD
Rthg= infinite useful for many
ID 1
Rthd
Rth = (1+RD /ro ) (ro
s gm+gmb
) calculations
d
RG g Approximation
(gmb << gm, gmro >> 1)
 It would be nice to
s
Rthg
Rths Rthd= ro (1+gmRS) replace Hybrid-
RS Rthg= infinite model with a simpler
1 + RD /ro 1
Rth =
s gm gm
(RD<< ro ) alternative
M.H. Perrott 9
 Replace Hybrid- Model with Proposed Thevenin Model

Hybrid-π Model Key Small-Signal Parameters

Rthd RD
RG g d Parameter Strong Inversion Weak Inversion

gm qID
2μnCox(W/L)ID
Rthg vgs nkT
gmvgs -gmbvs ro
γ gm (n-1)qID
gmb
2 2|ΦF| + VSB nkT
s
Rths Note: gmb = 0
vs RS 1 1
ro
if RS=0 or Vsb=0 λID λID

Thevenin Resistances Exact Proposed Small Signal Transistor Model

Rthd= ro (1+(gm+gmb)RS)+RS g d
is
Rthg= infinite Rths
ID RD
Rths= (1+RD /ro ) (ro 1 ) Rthg vg Avvg α is Rthd
Rthd gm+gmb
RG d
g Approximation
(gmb << gm, gmro >> 1) s
Rthg s
Rths Rthd= ro (1+gmRS) Exact Approximation
gm
RS Rth = infinite Av = gmro Av = 1 (gmb<<gm, gmro>>1)
g gm+gmb
1 + RD /ro 1
Rth =
s gm gm
(RD<< ro ) α = 1+RD /Rthd α = 1 (RD<<Rthd)

M.H. Perrott 10
 Key Things to Know About the Proposed Thevenin Model
Thevenin Resistances Exact Proposed Small Signal Transistor Model

Rth = ro (1+(gm+gmb)RS)+RS g d
d
is
Rthg= infinite Rths
ID RD
Rths= (1+RD /ro ) (ro 1 ) Rthg vg Avvg α is Rthd
Rthd gm+gmb
RG d
g Approximation
(gmb << gm, gmro >> 1) s
Rthg s
Rths Rthd= ro (1+gmRS) Exact Approximation
gm
RS Rthg= infinite Av = gmro Av = 1 (gmb<<gm, gmro>>1)
gm+gmb
1 + RD /ro 1
Rths= gm gm
(RD<< ro ) α = 1+RD /Rthd α = 1 (RD<<Rthd)

 This model may be generally applied in cases where the

transistor is in saturation and where there is not strong
interaction between the transistor terminals
- Works well for open loop amplifier stages which will be our
initial focus
 Proposed model is not commonly taught – I developed it

M.H. Perrott 11
 A General View of Signal Flow in an Open Loop Device

Vin,d ID RD

d
RG g Vd
M1
M1
s Vs gate signal impacts source signal impacts
RS source and drain drain
Vin,g
RG Rths is
Vin,s g d

Rthg vg Avvg α is Rthd RD

s vd

vin,g RS vin,d
vs
vin,s

 To first order, influence of signals go from gate to

source or from gate and/or source to drain
M.H. Perrott
- This is only true when the device is in saturation 12
 Example: Small Signal Analysis of Amplifier Circuit

Key device characteristics

RD
that must be known:
RG Vout
M1
For gm, ro: W, L, nCox, 
Vin
RS
For gmb: gm, , F, VSB

 First step: determine the operating region of transistor

- For triode region, approximate channel as a resistance
 Id will usually be set primarily by drain and source network
- For subthreshold region, approximate channel as open
 Later on, we will take a more accurate view of this
- For saturation region, use proposed Thevenin model
 Id will usually be set by gate voltage and source network
(i.e., resistance and voltage)
 Small signal parameters (gm, ro, etc.) can be calculated
once Id is known
M.H. Perrott 13
 Substitute Proposed Thevenin Model (Assumes Saturation)

RD
RG Vout
M1

Vin
RS

M1

RG Rths is
g d

vin Rthg vg Avvg α is Rthd RD vout

RS

 Notice that all voltages and currents can be calculated

without requiring simultaneous equations!

M.H. Perrott 14
 Reduce to Two-Port

RG
RD
RG Vout
M1 vin vg Rthg Gmvg Rthd RD vout
Vin
RS

M1

RG Rths is
g d

vin Rthg vg Avvg α is Rthd RD vout

RS

 Calculation of Gm:

M.H. Perrott 15
 Detailed Example

1.3V Assumptions:
10kΩ nCox = 50A/V2, VTHn = 0.5V
Vout
100Ω  = 1/(10V),  = 0
13u
0.13u
Vin M1
100Ω
Vbias= 0.65V

 Determine operating point conditions

- Transistor operating region, I d
 Determine small signal parameters of transistor model
- If transistor is in saturation, this is g , r , etc.
m o
 Determine gain of amplifier

M.H. Perrott 16
 Analysis and Design of Analog Integrated Circuits
Lecture 5

Single Stage Amplifiers

Michael H. Perrott
February 5, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 From Lecture 4: Proposed Thevenin Model for Transistor

Hybrid-π Model Key Small-Signal Parameters

Rthd RD
RG g d Parameter Strong Inversion Weak Inversion

gm qID
2μnCox(W/L)ID
Rthg vgs nkT
gmvgs -gmbvs ro
γ gm (n-1)qID
gmb
2 2|ΦF| + VSB nkT
s
Rths Note: gmb = 0
vs RS 1 1
ro
if RS=0 or Vsb=0 λID λID

Thevenin Resistances Exact Proposed Small Signal Transistor Model

Rthd= ro (1+(gm+gmb)RS)+RS g d
is
Rthg= infinite Rths
ID RD
Rths= (1+RD /ro ) (ro 1 ) Rthg vg Avvg α is Rthd
Rthd gm+gmb
RG d
g Approximation
(gmb << gm, gmro >> 1) s
Rthg s
Rths Rthd= ro (1+gmRS) Exact Approximation
gm
RS Rth = infinite Av = gmro Av = 1 (gmb<<gm, gmro>>1)
g gm+gmb
1 + RD /ro 1
Rth =
s gm gm
(RD<< ro ) α = 1+RD /Rthd α = 1 (RD<<Rthd)

M.H. Perrott 2
 A General View of Signal Flow in an Open Loop Device

Vin,d ID RD

d
RG g Vd
M1
M1
s Vs gate signal impacts source signal impacts
RS source and drain drain
Vin,g
RG Rths is
Vin,s g d

Rthg vg Avvg α is Rthd RD

s vd

vin,g RS vin,d
vs
vin,s

 To first order, influence of signals go from gate to

source or from gate and/or source to drain
M.H. Perrott
- This is only true when the device is in saturation 3
 Why is a CMOS Transistor Useful?

 Key properties of a transistor:

- Converts voltage to current
- Funnels current between different impedance domains
 The above properties allow us to build amplifiers in
creative ways
- A number of circuit topologies are possible
- A good designer can leverage the right topology to
achieve the best performance for a given application

M.H. Perrott 4
 Basic Single-Stage CMOS Amplifiers
Common Source Common Gate Source Follower

Vin W1
ZL ZL Source
L
Vout Vout M1 Vout
id id
ZL
Vin W1 W1
Source
L L
M1 M1 iin

Common Source Source

with Source Degeneration

ZL
Vout
id
Source
Vin W1
Source Zsrc
L
M1 Vsrc Isrc Zsrc
ZS

M.H. Perrott 5
 Example: The Impact of Low Input Impedance

Vbuf
Zsrc

Vsrc
Zin Assume:
Zsrc = 10k
Zin = 100

 Here we consider how the gain is influenced by

having a source with large impedance driving a circuit
with low input impedance
- Calculate the gain from V to V
src buf
- What is the impact of low Z and high Z
in src?

What type of amplifier stage would alleviate the impact of

having high source impedance and low input impedance?
M.H. Perrott 6
 Consider a Source Follower Circuit

Vbuf
Zsrc

Vsrc
Zin Assume:
Zsrc = 10k
Zin = 100
ZL = 10k
gm = 1/(100)
Source Follower
gmb = 0
Vin W1 ro = 100k
Zsrc
L Vbuf
Vsrc M1

ZL
Zin

 Calculate the gain from Vsrc to Vbuf

 How did the source follower improve the situation?
M.H. Perrott 7
 Example: The Impact of Low Source Impedance

Vbuf

Isrc Zsrc
Zin

Assume:
Zsrc = 100
Zin = 1k

 Calculate the gain from Isrc to Vbuf

 What is the impact of low Zsrc?

What type of amplifier stage would alleviate the

impact of having low source impedance?
M.H. Perrott 8
 Consider a Common Gate Amplifier

Vbuf

Isrc Zsrc
Zin

Assume: Common Gate

Zsrc = 100
Zin = 1k ZL
ZL = 10k Vbuf
gm = 1/(100) id
gmb = 0
ro = 100k W1 Zin
L
M1 iin

Isrc Zsrc  Calculate the gain from Isrc to Vbuf

How can we further improve gain?
M.H. Perrott 9
 Add a Source Follower

Vbuf

Isrc Zsrc
Zin

Assume: Common Gate

Zsrc = 100 Source Follower
Zin = 1k ZL
ZL = 10k W2
gm = 1/(100) id L Vbuf
M2
gmb = 0
ro = 100k W1
L ZL
M1 iin Zin

Isrc

Zsrc
Calculate the gain from Isrc to Vbuf
 Did the source follower help?
M.H. Perrott 10
 Consider Using a Common Source Amplifier Instead

Vbuf

Isrc Zsrc
Zin

Assume:
Zsrc = 100 Common Source
Zin = 1k
ZL = 10k
ZL
gm = 1/(100) Vbuf
gmb = 0
ro = 100k id
Vin W1 Zin
L
Isrc Zsrc M1

 Calculate the gain from Isrc to Vbuf

How does the common gate approach compare to this?

M.H. Perrott 11
 Analysis and Design of Analog Integrated Circuits
Lecture 6

Current Mirrors

Michael H. Perrott
February 8, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 From Lecture 5: Basic Single-Stage CMOS Amplifiers
Common Source Common Gate Source Follower

Vin W1
ZL ZL Source
L
Vout Vout M1 Vout
id id
ZL
Vin W1 W1
Source
L L
M1 M1 iin

Common Source Source

with Source Degeneration

ZL
Vout
id
Source
Vin W1
Source Zsrc
L
M1 Vsrc Isrc Zsrc
ZS

M.H. Perrott 2
 A Closer Look at Load Impedance
Common Source Common Gate Source Follower

Vin W1
ZL ZL Source
L
Vout Vout M1 Vout
id id
ZL
Vin W1 W1
Source
L L
M1 M1 iin

Common Source Source

with Source Degeneration

 To achieve high gain (or low

ZL
attenuation in the case of a source
Vout
id follower), it is very desirable to
Vin W1 achieve high load impedance, ZL
Source
M1
L - Unfortunately, using a simple resistor
of high value has issues
ZS
 What are these issues?
M.H. Perrott 3
 Issue #1: Headroom Limitations
Common Source
Vdd

RL
Vout
Id
Vin
Source Want Vds > ΔV
M1

 The bias current of the device is a direct function of RL

Vdd − Vds
Id =
RL
-V dd is < 3.6V for most modern CMOS processes
-V ds must be greater than V to maintain device saturation

Large RL implies small Id

(implies small gm, poor frequency response, etc.)
M.H. Perrott 4
 Issue #2: Area of Circuit
Common Source
Vdd

RL
Vout
Id
Vin
Source Want Vds > ΔV
M1

 The most common resistors for precision analog

circuits are often based on unsilicided polysilicon
layers
- The sheet resistance of unsilicided polysilicon is often
< 1k/square

Large polysilicon RL implies relatively large circuit area

(implies high relative cost)
M.H. Perrott 5
 An Elegant Approach to Achieving High Gain
Common Source
Vdd
Ibias

Vout
Id
Vin
Source Vds1 > ΔV1
M1

 Replacement of resistor load with a current source

yields the highest possible DC gain out of the amplifier
- Current source determines I d of device
 We can make current sources out of transistors
- Generally smaller area than polysilicon resistors
What is the small signal gain of the above circuit?
M.H. Perrott 6
 A Simple Transistor Based Current Source
Vdd
Vbias Vsd2 > ΔV2
M2
Vout
Id
Vin
Source Vds1 > ΔV1
M1

 Simply use a PMOS load that is properly biased

- If we keep the PMOS in saturation, its current is
relatively constant despite Vsd variations
 This is the desired behavior of a current source

What are the nonideal issues of the above approach?

M.H. Perrott 7
 Issue #1: Impedance of PMOS Device
Vdd
Vbias Vsd2 > ΔV2
M2
ZL Vout
Id
Vin
Source Vds1 > ΔV1
M1

 An ideal current source has infinite impedance

 PMOS devices have finite impedance
- What is Z in the above circuit?
L
- How does finite Z impact the gain of the circuit?
L

We will later examine techniques to increase ZL

M.H. Perrott 8
 Issue #1: High Bias Sensitivity
Vdd
Vbias W2
L
M2
Vout
Id
Vin
Source Vds1 > ΔV1
M1

 The PMOS device current, Id, is very sensitive to the

value of Vbias
- We want I dto be relatively constant across temperature
and process variations

How can we achieve tighter control over Id across

temperature and process variations?
M.H. Perrott 9
 Key Technique: Use Current Mirror
Vdd
W3 Vbias W2
Vsd2 > ΔV2
L L
M3 M2
Vout
Ibias Id
Vin
Source Vds1 > ΔV1
M1

 Key idea: use a different PMOS device, M3, to transform a

bias current, Ibias, into bias voltage, Vbias
- V now yields a consistent current, I , in M (assumed to
bias d 2
be in saturation) across temperature and process variations
- Note that layout of M and M must be done properly to
2 3
achieve good device matching

How does Id relate to Ibias?

M.H. Perrott 10
 NMOS Devices Can Also Be Used for Current Mirrors

Ibias
Zo Id

W2 Vbias W1
Vds1 > ΔV1
L L
M2 M1

 We often use both NMOS and PMOS versions in

designs
- We’ll explore this issue further later in the semester
 General issue: current mirrors involve direct
feedback between drain and gate

Can we apply proposed Thevenin modeling

approach to current mirrors?
M.H. Perrott 11
 Issue: Thevenin Impedances Are Not Adequate
Zo

M1

RS

 Looking as purely Thevenin impedances

 But, in reality

 Issue: coupling between source, drain, or gate

- Do we have to abandon the Thevenin method?
M.H. Perrott 12
 Try Proposed Thevenin Model
Zo
itest
g d vtest
is
Rths
Rthg vg Avvg α is Rthd

s
Rs

 Key Calculations (ignore Rthd for now):

M.H. Perrott 13
 Proposed Thevenin Model Works!
Zo
itest
g d vtest
is
Rths
Rthg vg Avvg α is Rthd

s
Rs

 Now include Rthd:

M.H. Perrott 14
 Check Thevenin Resistance Calculation

Diode-Connected Derive Zo Using Resulting

Device Hybrid-π Model One-Port Model
Zo

Zo Zo

vgs gmvgs -gmbvs ro

M1 1 (gm+gmb)
RS
gm gm

RS
vs RS

 Plug in Hybrid- to do the analysis

- Answer agrees with proposed Thevenin model approach
 Easiest to just memorize this result:
Diode connected MOS looks like a resistor of value 1/gm
M.H. Perrott 15
 Now Apply Thevenin Approach to the Current Mirror

Zo
Ibias
Iref
node1 node2

M2 M1

Zo Zo

M2 node1 M1 node2 node2

g1 d1

1 Rthg1 Rthd1= ro1

vg1 g m1vg1 Rthd1
gm2

Diode-Connected Common Source

 Key parameter of current source: output resistance

- Corresponds to r o of device
16
M.H. Perrott
 Cascoded Current Source

Zo Zo
Iref
Ibias Vbias Vbias
Vds3 > ΔV3 M3
M3

ro1
Vds1 > ΔV1
M2 M1

 Offers increased output resistance

- Calculate using Thevenin resistance method
- How does I compare to I ?
ref bias

M.H. Perrott 17
 Double Cascode Current Source

I1 I2 Zo

Vbias2 M3
Vds3 > ΔV3

Vbias1 M2
Vds2 > ΔV2

M4 M1
Vds1 > ΔV1

 Offers further increased output resistance

- Calculate using Thevenin resistance method
- How does I compare to I ?
2 1

M.H. Perrott 18
 Analysis and Design of Analog Integrated Circuits
Lecture 7

Differential Amplifiers

Michael H. Perrott
February 12, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Review Proposed Thevenin CMOS Transistor Model

Hybrid-π Model Key Small-Signal Parameters

Rthd RD
RG g d Parameter Strong Inversion Weak Inversion

gm qID
2μnCox(W/L)ID
Rthg vgs nkT
gmvgs -gmbvs ro
γ gm (n-1)qID
gmb
2 2|ΦF| + VSB nkT
s
Rths Note: gmb = 0
vs RS 1 1
ro
if RS=0 or Vsb=0 λID λID

Thevenin Resistances Exact Proposed Small Signal Transistor Model

Rthd= ro (1+(gm+gmb)RS)+RS g d
is
Rthg= infinite Rths
ID RD
Rths= (1+RD /ro ) (ro 1 ) Rthg vg Avvg α is Rthd
Rthd gm+gmb
RG d
g Approximation
(gmb << gm, gmro >> 1) s
Rthg s
Rths Rthd= ro (1+gmRS) Exact Approximation
gm
RS Rth = infinite Av = gmro Av = 1 (gmb<<gm, gmro>>1)
g gm+gmb
1 + RD /ro 1
Rth =
s gm gm
(RD<< ro ) α = 1+RD /Rthd α = 1 (RD<<Rthd)

M.H. Perrott 2
 Key Observations
Thevenin Resistances Exact Proposed Small Signal Transistor Model

Rth = ro (1+(gm+gmb)RS)+RS g d
d
is
Rthg= infinite Rths
ID RD
Rths= (1+RD /ro ) (ro 1 ) Rthg vg Avvg α is Rthd
Rthd gm+gmb
RG d
g Approximation
(gmb << gm, gmro >> 1) s
Rthg s
Rths Rthd= ro (1+gmRS) Exact Approximation
gm
RS Rthg= infinite Av = gmro Av = 1 (gmb<<gm, gmro>>1)
gm+gmb
1 + RD /ro 1
Rths= gm gm
(RD<< ro ) α = 1+RD /Rthd α = 1 (RD<<Rthd)

 For calculations focusing on signal flow from gate or

source to the drain
- Observe that current through R equals is d
 True since  * Rthd/(Rd + Rthd) = 1
 You can avoid doing calculations involving  or Rthd
 For calculations focusing on signal flow from the drain

M.H. Perrott
- Drain simply looks like impedance R thd
3
 Basic Single-Stage Amplifiers and Current Mirrors
Common Source Common Gate Source Follower

Vin W1
ZL ZL Source
L
Vout Vout M1 Vout
id id
ZL
Vin W1 W1
Source
L L
M1 M1 iin

Common Source Source

with Source Degeneration

ZL
Vout
Current Mirror
id
Vin W1 iin iout
Source
L
M1
ZS W2 W1
L L
M2 M1
M.H. Perrott 4
 Today We Will Look At Differential Amplifiers
Common Source Common Gate Source Follower

Vin W1
ZL ZL Source
L
Vout Vout M1 Vout
id id
ZL
Vin W1 W1
Source
L L
M1 M1 iin

Common Source Source Differential

with Source Degeneration Amplifier

ZL
ZL ZL
Vout
Current Mirror
id Vo- Vo+
Vin iin iout Vin+ Vin-
W1 M1 M2
Source
L
M1
ZS W2 W1 Ibias
L L
M2 M1
M.H. Perrott 5
 Differential and Common Mode Signals

Vd/2
Vc
-Vd/2

 Consider positive and negative input terminal signals

Vi+ and Vi-
 Define differential signal as: Vid = Vin+ − Vin−
 Define common mode signal as: Vic = (Vin+ + Vin− )/2
 We can create arbitrary Vi+ and Vi- signals from
differential and common mode components:
+ 1 − 1
Vin = Vic + Vid Vin = Vic − Vid
2 2
 This also applies to differential output signals:
+ 1 − 1
Vo = Voc + Vod Vo = Voc − Vod
2 2
M.H. Perrott 6
 Differential Amplifier

RL RL

Vo- Vo+
Ibias1 Vin+ Vin-
M1 M2

M3 M4

 Useful for amplifying signals in the presence of noise

- Common-mode noise is rejected
 Useful for high speed digital circuits
- Low voltage swing allows faster gate/buffer
performance

M.H. Perrott 7
 First Steps in Small Signal Modeling

RL RL RL RL

Vo- Vo+ Vo- Vo+

Ibias1 Vin+ Vin- Vin+ Vin-
M1 M2 M1 M2

M3 M4 Rthd4= ro4

 Small signal analysis assumes linearity

- Impact of M on amplifier is to simply present its drain
4
impedance to the diff pair transistors (M and M ) 1 2
- Impact of V and V can be evaluated separately and
in+ in-
then added (i.e., superposition)
 By symmetry, we need only determine impact of Vin+
 Calculation of Vin- impact directly follows

M.H. Perrott 8
 Calculate Impact of Vin+ using Thevenin Models

RL RL

Vo- Vo+
Vin+
M1 M2

ro4
RL RL

M1 Vo- M2 Vo+

is1
Rths1
Vin+ Rthg1 vg1 Av1vg1 α 1is1 Rthd1 Rths2 α2 is2 Rthd2

is2

General Model ro4 Common Gate

 Analysis follows fairly easily, but there is a simpler way!

M.H. Perrott 9
 Method 2 of Differential Amplifier Analysis

RL RL RL RL

Vo- Vo+ Vo- Vo+

Vin+ Vin-
M1 M2 M1 M2
Vid -Vid
2 2

ro4 Vic ro4

 Partition input signals into common-mode and

differential components
 By superposition, we can add the results to determine
the overall impact of the input signals

M.H. Perrott 10
 Differential Analysis

is1= is2
RL RL iR = 0 R1 R2 R1 R2
Vid Vo- Vo+ -Vid Vid Vo- Vo+ -Vid Vid Vo- Vo+ -Vid
2 2 2 2 2 2
M1 M2 M1 M2 M1 M2

is1 is2
iR ro4

 Key observations
- Inputs are equal in magnitude but opposite in sign to each
other
- By linearity and symmetry, i must equal -i s1 s2
 This implies iR is zero, so that voltage drop across ro4 is zero
 The sources of M1 and M2 are therefore at incremental
ground and decoupled from each other!
 Analysis can now be done on identical “half-circuits”
What is the differential DC gain?
M.H. Perrott 11
 Common Mode Analysis

is1= is2
RL RL iR = 2is1= 2is2 RL RL RL RL

Vo- Vo+ Vo- Vo+ Vo- Vo+

Vic Vic Vic Vic Vic Vic
M1 M2 M1 M2 M1 M2

is1 is2 is1 idiff = 0 is2

iR ro4 2ro4 2ro4 2ro4 2ro4

 Key observations
- Inputs are equal to each other
- By linearity and symmetry, i must equal i s1 s2
 This implies i = 2i = 2i R s1 s2
- We can view r as two parallel resistors that have equal
o4
current running through them
 Analysis can also be done on two identical half-circuits

What is the common mode DC gain?

M.H. Perrott 12
 Useful Metric for Differential Amplifiers: CMRR

Vinput Vnoise Vid=Vsig Vod

 Common Mode Rejection Ratio (CMRR)

- Define: a vd: differential gain, avc: common mode gain
µ ¶
avd
CMRR =
avc
- CMRR corresponds to ratio of differential to common
mode gain and is related to received signal-to-noise ratio

Vod = avd Vsig + avc Vnoise

µ ¶µ ¶ µ ¶
Signal avd Vsig Vsig
⇒ = = CMRR
Noise avc Vnoise Vnoise
M.H. Perrott 13
 Another Useful Metric for Differential Amplifiers: PSRR
Vsup+

Vinput Vnoise Vid=Vsig Vod

Vsup-
 Power Supply Rejection Ratio (PSRR)
-a vd: differential gain
-a vp+: positive power supply gain
-a vp-: negative power supply gain
µ ¶ µ ¶
+ avd − avd
PSRR = PSRR =
avp+ avp−

M.H. Perrott 14
 Example: Calculate CMRR and PSRR

RL RL RL RL

Vo- Vo+ Vo- Vo+

Vin+ Vin-
M1 M2 M1 M2
Vid -Vid
2 2

ro4 Vic ro4

 First determine avd, avc, avp+, and avp-

 Then calculate CMRR and PSRR
- Note that CMRR and PSRR are often expressed in dB
 Example: CMRR = 20log(avd/avc)

M.H. Perrott 15
 Common Mode Voltage Range of Differential Amplifier

RL RL

Id1 Vo- Vo+ Id2

M1 M2
Ibias
Vin+ ΔV1 ΔV2 Vin-

VTH+ΔV1 VTH+ΔV2
Iss

ΔV4
M3 M4

 While keeping all devices in saturation:

- What is the maximum common mode output range?
 Assume V = 0 id
- What is the maximum common mode input range?
 Assume Vod = 0

M.H. Perrott 16
 Large Signal Behavior of Differential Mode Operation

Vid = Vin+-Vin-= (VTH+ΔV1) - (VTH+ΔV2) = ΔV1-ΔV2

RL RL
Id1 Id2 μnCoxW
Vo- Vo+ Vid = where k =
k k 2L
Id1 Id2
Ibias Vin+ Vin- Iss+Iod/2 Iss-Iod/2
M1 M2 Vid = where Iod = Id1-Id2
k k
VTH+ΔV1 VTH+ΔV2 square and solve for Iod
Iss
2Iss 2 Iss
Iod = KVid -Vid for Vid <
M3 M4 k k

Iod = Id1-Id2

Iss
Iss
k
Vid = Vin+-Vin-
Iss
k
-Iss

 Note: above analysis assumes strong inversion

M.H. Perrott 17
 Analysis and Design of Analog Integrated Circuits
Lecture 8

Cascode Techniques

Michael H. Perrott
February 15, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Review of Large Signal Analysis of Current Mirrors

Vdd

ΔV2
I1 I2 1 μ C W2 2
n ox (VGS2-VTH) (1+λ2Vds2)
I2 2 L2
=
I1 1 μ C W1
n ox (VGS1-VTH)2(1+λ1Vds1)
M2 2 L1
M1 Vds2 > Vdsat2 ΔV1
Vss=0 VTH+ΔV1 VTH+ΔV2 But, VTH+ΔV1=VTH+ΔV2 ΔV1 = ΔV2

I2 W2 L1 (1+λ2Vds2)
I2 =
M2 in I1 W1 L2 (1+λ1Vds1)
Saturation Current Mismatch
setting due to Vds
M2 in based on difference
Triode geometry
Note: for accurate ratio, set L1 = L2
Vds2
Vdsat2

M.H. Perrott 2
 The Issue of Vds Mismatch in Current Mirrors

Vdd I2 W2 (1+λ2Vds2)
=
I1 W1 (1+λ1Vds1)
I1 I2
Current Mismatch
setting due to Vds
based on difference
geometry
Vds1 Vds2
M1 M2 Note: we are assuming L1 = L2

 Issue: Current I2 can vary significantly as a function

of the drain voltage of M2
- We often want a tightly controlled current set only by I 1
and transistor sizes
 How do we improve the current mirror matching
performance?

M.H. Perrott 3
 Cascoded Current Source

Iref Rthd3 Rthd3

Ibias Vbias Vbias
M3 M3

M2 ro1
M1

 Offers increased output resistance

- Reduces small signal dependence of output current on
the output voltage of the current source
- From Lecture 6, we derived:
 Output resistance boosted by intrinsic gain of M3, gm3ro3
 But how do we reduce the influence of large signal Vds
mismatch between M1 and M2?

M.H. Perrott 4
 Match Vds of Current Mirror Devices With Proper Bias
Vdd

I1
I2 I2 W1 L4 (1+λ1Vds1)
Recall: =
M3 M2 Vo I1 W4 L1 (1+λ4Vds4)
W/L W/L Vds2 > ΔV Current Mismatch
VTH+ΔV VTH+ΔV setting due to Vds
based on difference
M4 M1 geometry
W/L W/L Vds1 = VTH+ΔV
Vss=0 VTH+ΔV VTH+ΔV

 Key transistor for determining I2 is M1

- Why is M 2 less important?
 Above biasing approach provides a much closer
match between Vds1 and Vds4
W1 1 + λVds1 W1
I2 = I1 ≈ I1
W4 1 + λVds4 W4
M.H. Perrott 5
 The Drawback of Basic Cascode Bias Approach
Vdd
I2
I1 M1 and M2
M1 in saturation in saturation
I2
M2 in triode
M3 M2 Vo
W/L W/L Vds2 > ΔV M1 and M2
VTH+ΔV VTH+ΔV in triode

M4 M1 Vo
V1 VTH+2ΔV
W/L W/L Vds1 = VTH+ΔV
VTH+ΔV VTH+ΔV calculation of V1 is nontrivial
Vss=0

 Output voltage range is reduced

- Now V must be > V + 2V
o TH
- What will happen to the output impedance of the current
source if the output voltage is too low?
- Can we improve the voltage range?
M.H. Perrott 6
 Improved Swing Cascode
I2 M1 and M2
in saturation
Vdd
M1 and M2
in triode no wasted voltage region
I1

2VTH+3ΔV
Vo
I2 Vdsat1+Vdsat2
M3 M5
αW/L W/L Vo
VTH+2ΔV M2
VTH+2ΔV VTH+ΔV W/L Vds2 > ΔV
VTH+ΔV

M4 M6 M1
W/L W/L Vds1 = ΔV
W/L
Vss=0 VTH+ΔV VTH+ΔV VTH+ΔV

 Key idea: set size of M3 such that Vds1 = V

- Assuming strong inversion for M 1 and M3:

M.H. Perrott 7
 Alternative Implementation of Improved Swing Cascode
I2 M1 and M2
in saturation

Vdd
M5 M6 M7 M1 and M2
Wp/Lp in triode no wasted voltage region
Wp/Lp Wp/Lp
I1 I1
I2 Vo
2ΔV
Vo
M3 M2
αW/L W/L Vds2 > ΔV
I1
VTH+2ΔV VTH+ΔV

M4 M1
W/L W/L Vds1 = ΔV
Vss=0 VTH+ΔV VTH+ΔV

 Set  as on previous slide

 Note: both implementations share a common problem

M.H. Perrott 8
 The Issue of Current Mismatch

I1 I2

VTH+2ΔV M2
I2 W2 (1+λ2Vds2)
Recall: =
I1 W1 (1+λ1Vds1)
VTH+ΔV
Mismatch
M4 M1 due to Vds
Vds4 = VTH+ΔV Vds1 = ΔV difference
W/L W/L

 The improved swing approach causes a systematic

mismatch between I2 and I1
- Key issue: V ds1  Vds4

 Can we fix this problem?

M.H. Perrott 9
 Techniques to Reduce Current Mismatch
I1 I2

M3 VTH+2ΔV M2
W/L W/L
VTH+ΔV VTH+ΔV

M4 M1
Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Systematic mismatch between I1 and I2 is greatly

reduced by using the above circuit (now Vds1 ≈ Vds4)
- Note that gate bias on M and M3 may be provided by
2
previously discussed circuits
 Additional techniques for accurately matching I1 and I2
- Set L = L >> L
1 4 min
 Note: set L = L ≈ L for lower area and capacitance
2 3 min
- Set W /W = I /I so that V = V
M.H. Perrott
2 3 2 1 2 3 10
 Another Common Cascode Bias Topology
Vdd
M5 M6 M7
Wp/Lp
Wp/Lp Wp/Lp
I1 I1

M8
W/L
M9
VTH+2ΔV
W/L
M10
I2
W/L
M11 M3 M2
W/L W/L W/L
I1
M12 VTH+ΔV VTH+ΔV
W/L
M13 M4 M1
W/L Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Key issue: needs two bias current branches

M.H. Perrott 11
 Utilizing a Simple Resistor to Achieve One Bias Branch

M5 M7
Wp/Lp
Wp/Lp
I1

VTH+2ΔV

ΔV RB
I2

M3 M2
W/L W/L
I1
VTH+ΔV VTH+ΔV

M4 M1
Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Issue: poly resistor is large and won’t track NMOS

devices across temperature and process variations 12
M.H. Perrott
 Better Approach: Use PMOS Device In Triode Region

M5 M7
Wp/Lp
Wp/Lp
I1

VTH+2ΔV

M6
Wp/Lp ΔV
I2

M3 M2
W/L W/L
I1
VTH+ΔV VTH+ΔV

M4 M1
Vds4 = ΔV Vds1 = ΔV
W/L W/L

 Much smaller, better tracking with NMOS devices than

resistor 13
M.H. Perrott
 Wilson Current Mirror

I2
I1 Rthd2

M2

M3 M1

 Relies on feedback in its operation

 Using Hybrid- analysis

- Output resistance comparable to cascode current source

 This circuit is rarely used these days

M.H. Perrott 14
 Enhanced Cascode Current Source

Ibias Ibias2 Iref

M4

M3

M2 M1

 Offers output resistance comparable to double

cascode current source
 As with Wilson mirror, analysis is tricky due to
source/gate coupling
- Using results shown in the following slide:
M.H. Perrott 15
 Thevenin Resistances for CMOS Transistor Feedback Pair

RA RC RA RC
Rthd
D Rthd M4 D

M4

M3 vgs4 gm4vgs4 -gmb4vs4 ro4

S Rths M3
RB

S
ro3 -gmb3vs3 gm3vgs3 vgs3 Rths
vs4 RB
vs3=0

M.H. Perrott 16
 Basic Cascode Amplifier

RD
Vout M2
M2
Rths2 is2 d2
RG
M1

Vin α 2is2 Rthd2 RD vout

RS

s2
M1
Common Gate
RG g1 Rths1 is1 d1

vin Rthg1 vg1 Av1vg1 α 1is1 Rthd1

s1

General Model RS

 Allows improved frequency response (discussed later)

 Reduction to two-port will be done in several steps
17
M.H. Perrott
 Eliminate Middle Sections

RD
Vout M2
M2
Rths2 is2 d2
RG
M1

Vin α 2is2 Rthd2 RD vout

RS

s2
M1

RG g1 d1

vin Rthg1 vg1 Gm1vg1 Rthd1

 Calculation of Gm1 same as for common source amp

 To reduce further, note that

M.H. Perrott 18
 Resulting Two-Port Similar to Common Source Amp

RD
Vout M2
M2
d2
RG
M1

Vin Gm1vg1 Rthd2 RD vout

RS

M1

RG g1

vin Rthg1 vg1

 Key difference: drain impedance much larger

M.H. Perrott 19
 Slight Twist to Cascode Amplifier

Vdd
RL
Vout
RL
Vout
Ibias
1 is1 ro1
gm1+gmb1
Vbias
Iin is1
M1

Vin iin ro4 ro2

M4 M2 M3 Vss=0

 What is the difference between this amplifier and

basic cascode amplifier?
 What are the constraints in setting Vbias?
 What is the maximum output voltage swing?

M.H. Perrott 20
 Constraints on Vbias and Output Range
Vdd

RL
Vout
Ibias
M1
>ΔV1 Vbias
Iin
VTH+ΔV1

Vin >ΔV4 >ΔV2

M4 M2 M3 Vss=0

 To keep M2 and M4 in saturation

 To keep M1 in saturation

M.H. Perrott 21
 Calculation of Maximum Output Range
Vdd

RL
Vout
Ibias
M1
>ΔV1 Vbias
Iin
VTH+ΔV1

Vin >ΔV4 >ΔV2

M4 M2 M3 Vss=0

 Minimum Vbias allows the maximum output range

 Resulting output range

M.H. Perrott 22
 Variation on a Theme: Enhanced Cascode Amplifiers

Ibias1 Ibias2 R1
Vout
M4
Input Source
M3

Iin Rs
M2 M1

 We can turn the enhanced cascode current source

into an amplifier
- Inject a current input at the source of M 4
 Key aspects of small signal analysis can be done
using Thevenin method
- Simply leverage Thevenin resistance formulas shown on
Slide 16
M.H. Perrott 23
 Small-Signal Analysis of Enhanced Cascode Amp

Ibias1 Ibias2 R1 R1 Rout

Vout Vout
M4 M4
Input Source Input Source
M3 M3

Iin Rs 1 Rthd1 Rin Iin Rs

M2 M1 gm2

 From Thevenin resistance calculations on Slide 16:

- Input impedance is quite low
- Output impedance is probably determined by R 1

 This amplifier is useful for extracting a current signal

while keeping the source voltage nearly constant
M.H. Perrott 24
 Analysis and Design of Analog Integrated Circuits
Lecture 9

Open Circuit Time Constant Technique

Michael H. Perrott
February 26, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Review of Our Analysis Techniques
Block 1 Block 2 Block 3
Linear Network Linear Network Linear Network

Vin Va Vb Vc ZL

No Independent No Independent No Independent

Sources Sources Sources

Vin Zin GmVin Zout Va Zin GmVa Zout Vb Zin GmVb Zout Vc ZL

Zout,effective

Vth,effective Vb Zin,effective

 Two port analysis allows us to quickly calculate small

signal gain from cascaded network stages
- So far, only purely resistive impedances have been considered
M.H. Perrott 2
 The Problem with Complex Impedances
Block 1 Block 2 Block 3
Linear Network Linear Network Linear Network

Vin Va Vb Vc ZL

No Independent No Independent No Independent

Sources Sources Sources

Vin Zin GmVin Zout Va Zin GmVa Zout Vb Zin GmVb Zout Vc ZL

 When complex impedances are considered (i.e., capacitors,

inductors, and resistors), things get much more messy
- Complex impedance calculations are time consuming
- Capacitance between drain and gate of transistors
complicates calculation effort further

Can we determine a faster analysis path to gain intuition?

M.H. Perrott 3
 General Frequency Response for Amplifiers
Block 1 Block 2 Block 3
Linear Network Linear Network Linear Network

Vin Va Vb Vout ZL

No Independent No Independent No Independent

Sources Sources Sources

Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
wac2 wac1 wac0 w0 w1 w2

 Midband gain can be calculated by assuming purely

resistive impedances (as we have done so far)
- Large valued capacitors used for AC coupling will be shorts in
this analysis
 For DC coupled circuits, typically DC gain = Midband Gain
- Small valued capacitors will be opens in this analysis
M.H. Perrott 4
 Our Focus Will Be on High Frequency Poles
Block 1 Block 2 Block 3
Linear Network Linear Network Linear Network

Vin Va Vb Vout ZL

No Independent No Independent No Independent

Sources Sources Sources

Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
wac2 wac1 wac0 w0 w1 w2

 We are particularly interested in knowing the bandwidth of

our amplifier circuit
- Bandwidth is primarily set by the lowest frequency pole, w
- Additional attenuation occurs at frequencies beyond the
0

amplifier bandwidth by higher frequency poles w1, w2, etc.

M.H. Perrott 5
 Open Circuit Time Constant Technique
Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
wac2 wac1 wac0 w0 w1 w2

 The Open Circuit Time Constant (OCT) technique allows us

to quickly estimate the bandwidth of an amplifier circuit
- We will see that it is most accurate when there is one dominant
pole, w0
 This means that w1, w2, and higher poles are not close in
frequency to w0
 This will hold for opamps and other circuits that operate in
feedback
 There is still considerable value to the OCT method in providing
design intuition even when there is not just one dominant pole
M.H. Perrott 6
 Short Circuit Time Constant Technique
Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
wac2 wac1 wac0 w0 w1 w2

 The Short Circuit Time Constant (SCT) technique allows us

to quickly estimate the AC-coupled cutoff frequency, wac0
- This has many similarities to the OCT method, but we will not
discuss in this class since
 AC coupling is not used very often in integrated circuits due to
the high cost of large valued capacitors
 When AC coupling is applied in integrated circuits, it is often
quite easy to estimate the AC-coupled cutoff frequency since
there are relatively few poles in the circuit related to AC-coupling

M.H. Perrott 7
 Key Assumptions for the OCT Technique
Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
w0 w1 w2

 Let us assume that the transfer function from Vin to Vout is

Vout (s) K
=
Vin (s) (τ0 s + 1)(τ1 s + 1) · · · (τn−1 s + 1)
- Note that we are ignoring any AC-coupling poles/zeros
 This implies that are approximating DC gain = Midband gain
 The OCT method does not require this assumption – it just
simplifies the analysis to follow
- Note also that DC gain equals K in the above transfer function
 We see this by setting s = 0
M.H. Perrott 8
 Key Idea of the OCT Technique
Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
w0 w1 w2

 Assuming the transfer function from Vin to Vout is:

Vout (s) K
=
Vin (s) (τ0 s + 1)(τ1 s + 1) · · · (τn−1 s + 1)
 We can achieve a reasonable approximation of the
bandwidth of the system by instead considering:
Vout (s) K
= ³P ´
Vin (s) n−1
τ s+1
i
- Here  are the “time constants” corresponding to the poles
i=0

i
of the circuit network
M.H. Perrott 9
 Bandwidth Estimate from OCT Technique
Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
w0 w1 w2

 The OCT technique approximates the transfer function as:

Vout (s) K
= ³P ´
Vin (s) n−1
τ s+1
i=0 i

 The estimated bandwidth is found by substituting s = jw0

and solving for w0 such that the magnitude is /
¯ ¯ ¯ ¯
1 ¯ Vout (w0 ) ¯ ¯ K ¯¯
¯ ¯ K
w0 = Pn−1 ¯
⇒ ¯ =¯ =√
Vin (w0 ) ¯ j1 + 1 ¯ 2
i=0 τi

Bandwidth estimate found by inversing the sum of time constants!

M.H. Perrott 10
 Why Is This Approximation Reasonable?

 Consider a second order example:

Vout (w0 ) K
=
Vin (w0 ) (jτ0 w0 + 1)(jτ1 w0 + 1)
 Expanding:
Vout (w0 ) K
=
Vin (w0 ) −τ0 τ1 w02 + j(τ0 + τ1 )w0 + 1
- But notice (since the time constant values are > 0):
j(τ0 + τ1 )w0 = j1 ⇒ τ0 w0 < 1, τ1 w0 < 1

 In fact: τ0 τ1 w02 ≤ 0.25

 The worse case of 01o2 = 0.25 occurs when 0 = 1:
¯ ¯ ¯ ¯
¯ Vout (w0 ) ¯ ¯ K ¯
¯ ¯=¯ ¯ = √K ≈ √K
¯ Vin (w0 ) ¯ ¯ j1 + 1 − 0.25 ¯ 1.56 2
 The approximation will be better for o ≠ 1
M.H. Perrott 11
 Key Issues For the OCT Approximation
 For the higher order transfer function
Vout (s) K
=
Vin (s) (τ0 s + 1)(τ1 s + 1) · · · (τn−1 s + 1)
 The OCT approximation for bandwidth is
1
BW ≈ Pn−1 rad /s
i=0 τi
 As hinted at by our second order example:
- The OCT approximation will have much better accuracy if the
time constants are different, and particularly if there is one
dominant time constant
- The bandwidth estimate by the OCT method is typically
conservative (i.e., actual bandwidth > OCT estimate)
 Complex poles can lead to actual bandwidth < OCT estimate

But how do we compute ∑ ?

M.H. Perrott 12
 OCT Method of Calculating the Sum of Time Constants

 OCT method calculates by the following steps:

- Compute the effective resistance R seen by each
thj
capacitor, Cj, with other caps as open circuits
 AC coupling caps are not included – considered as shorts
- Form the “open circuit” time constant Tj = RthjCj for each
capacitor Cj
- Sum all of the “open circuit” time constants
 As proved by Richard Adler at MIT
n−1
X m
X
τi = Rthj Cj
i=0 j=1
- This implies that the sum of the transfer function pole
time constants is the same as the sum of the open circuit
time constants
1
⇒ BW ≈ Pm rad /s
j=1 Rthj Cj
M.H. Perrott 13
 How Do You Tell if a Cap is for AC coupling or OCT?

 In general, capacitors associated with AC coupling

have the property that the amplifier gain increases as
the capacitor goes from open to short
- These capacitors are simply assumed to be shorts for
the OCT analysis
 In general, capacitors used in the OCT calculation
have the property that the amplifier gain decreases as
the capacitor goes from open to short
- These capacitors must all be considered in the OCT
analysis

M.H. Perrott 14
 Example: Second Order RC Network
R1 R2

Vin C1 C2 Vout

 Transfer function of the above network:

Vout (s) 1
=
Vin (s) R1 R2 C1 C2 s2 + (R1 C1 + R1 C2 + R2 C2 )s + 1
 The sum of the time constants from the poles of the
above network are obtained by inspection of the first
order coefficient in the above transfer function
1 1
⇒ BW ≈ Pn−1 = rad /s
i=0 τi
R1 C 1 + R1 C 2 + R 2 C 2
 For more complex networks, the direct approach of
explicitly calculating the transfer function is quite tedious
M.H. Perrott 15
 OCT Method Applied to Second Order RC Network
R1 R2 R1 R2

Vin C1 C2 Vout
Rth1 Rth2

 Obtain the Thevenin resistance values seen by each

capacitor with other capacitors as opens
Rth1 = R1 ⇒ Rth1 C1 = R1 C1
Rth2 = R1 + R2 ⇒ Rth2 C2 = (R1 + R2 )C2

 Bandwidth estimate from OCT method:

1 1
⇒ BW ≈ Pm = rad /s
j=1 Rthj Cj R1 C1 + (R1 + R2 )C2
- Note that OCT method agrees with estimate based on direct
calculation of the transfer function, but is much faster!
M.H. Perrott 16
 Example: Common Source Amplifier

ID RL
Vout

Rin

Vin

 Estimate the bandwidth of the above amplifier using

the OCT method
- What capacitances should be considered?
- What Thevenin resistances must be calculated?

M.H. Perrott 17
 Key Capacitances for CMOS Devices
Top View Side View
ID

VGS E
G
Cov Cov
VD>ΔV
S D W S Cgc D
Cjsb Ccb Cjdb
LD LD
L
B
E E
L junction bottom wall junction sidewall
cap (per area) cap (per length)

Cj(0) Cjsw(0)
source to bulk cap: Cjsb = WE + (W + 2E)
1 + VSB ΦB 1 + VSB ΦB (make 2W for "4 sided"
perimeter in some cases)
Cj(0) Cjsw(0)
drain to bulk cap: Cjsd = WE + (W + 2E)
1 + VDB ΦB 1 + VDB ΦB
2
overlap cap: Cov = WLDCox + WCfringe gate to channel cap: Cgc = C W(L-2LD)
3 ox

channel to bulk cap: Ccb - ignore in this class

M.H. Perrott 18
 CMOS Hybrid- Model with Caps (Device in Saturation)

RD
RG

ID RD
Cgd
Cdb
vgs Cgs gmvgs -gmbvs ro
RG

Csb
RS

vs RS

2
Cgs = Cgc + Cov = C W(L-2LD) + Cov
3 ox
Cgd = Cov
Csb = Cjsb (area + perimeter junction capacitance)
Cdb = Cjdb (area + perimeter junction capacitance)

M.H. Perrott 19
 Back to Common Source Amplifier

ID RL

Cgd Vout
Cdb
Rin

Vin Cgs
Csb

 Of the above capacitors, only Cgs, Cgd, and Cdb must

be considered
-C sb is grounded on both sides
 Thevenin resistance calculations
-C db: Rthd || Rd
-C gs and Cgd: these involve new Thevenin resistance
calculations
M.H. Perrott 20
 OCT Thevenin Resistance Calculations
Rthgd
ID RD RD
Rthgd RG
RG
Cgd
Rthgs vgs Cgs gmvgs -gmbvs ro
Rthgs

RS

vs RS

 Cgs: Thevenin resistance between gate and source

RS (1 + RD /ro ) + RG (1 + (gmb + 1/ro )RS + RD /ro )
Rth gs =
1 + (gm + gmb )RS + (RS + RD )/ro
 Cgd: Thevenin resistance between gate and drain
Rth gd = (RD + RG )(1 − rods /ro ) + rods gm RG
RD
where rods = ro ||
1 + (gm + gmb )RS
M.H. Perrott 21
 OCT Calculations for Common Source Amplifier

ID RL

Cgd Vout
Cdb
Rin

Vin Cgs
Csb

 Estimated bandwidth from OCT method:

1 1
BW ≈ Pm = rad/s
j=1 Rthj Cj (Rth d ||Rd ) Cdb + Rth gd Cgd + Rth gs Cgs

- The above calculations are straightforward given the

Thevenin resistance formulas for Rthd, Rthgd, and Rthgs
M.H. Perrott 22
 Analysis and Design of Analog Integrated Circuits
Lecture 10

Frequency Response of Amplifiers

Michael H. Perrott
February 29, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Open Loop Versus Closed Loop Amplifier Topologies
Open Loop Closed Loop
Zf
Source Source
Zsrc Amp Vout Zsrc Amp Vout
Vin Vin
Vsrc Vsrc

Vout/Vin Vout/Vin

(dB) (dB)

w (rad/s) w (rad/s)
w0 w1 w2 w0 w1 w2

 Open loop – want all bandwidth limiting poles to be as

high in frequency as possible
 Closed loop – want one pole to be dominant and all other
parasitic poles to be as high in frequency as possible
M.H. Perrott 2
 OCT Method of Estimating Amplifier Bandwidth
Note:
MidBand Gain w (rad/s)
f (Hz) =
2π
20log(Vout/Vin)
(dB)

w (rad/s)
w0 w1 w2

࢔ି૚
 OCT method calculates ࢏ୀ૙ ࢏ by the following steps:
- Compute the effective resistance R thjseen by each
capacitor, Cj, with other caps as open circuits
 AC coupling caps are not included – considered as shorts
- Form the “open circuit” time constant Tj = RthjCj for each
capacitor Cj
- Sum all of the “open circuit” time constants

1
⇒ BW ≈ Pm rad /s
j=1 Rthj Cj
M.H. Perrott 3
 Another Useful Analysis Tool: Miller Effect
Zf

iin
Vin A Vout
Zin
 Derive input impedance (assume gain of amplifier = A):
Vin Vin Vin Zf Zf
Zin = = = =
iin (Vin − Vout )/Zf Vin − AVin 1−A
 Consider the case where Zf is a capacitor
1 1
Zf = ⇒ Zin =
sC s(1 − A)C
- For negative A, input impedance sees increased cap value
- For A = 1, input impedance sees no influence from cap
- For A > 1, input impedance sees negative capacitance!
 Can be used to create active inductor for a specific frequency 4
M.H. Perrott
 Key Capacitances for CMOS Devices
Top View Side View
ID

VGS E
G
Cov Cov
VD>ΔV
S D W S Cgc D
Cjsb Ccb Cjdb
LD LD
L
B
E E
L junction bottom wall junction sidewall
cap (per area) cap (per length)

Cj(0) Cjsw(0)
source to bulk cap: Cjsb = WE + (W + 2E)
1 + VSB ΦB 1 + VSB ΦB (make 2W for "4 sided"
perimeter in some cases)
Cj(0) Cjsw(0)
drain to bulk cap: Cjsd = WE + (W + 2E)
1 + VDB ΦB 1 + VDB ΦB
2
overlap cap: Cov = WLDCox + WCfringe gate to channel cap: Cgc = C W(L-2LD)
3 ox

channel to bulk cap: Ccb - ignore in this class

M.H. Perrott 5
 CMOS Hybrid- Model with Caps (Device in Saturation)

RD
RG

ID RD
Cgd
Cdb
vgs Cgs gmvgs -gmbvs ro
RG

Csb
RS

vs RS

2
Cgs = Cgc + Cov = C W(L-2LD) + Cov
3 ox
Cgd = Cov
Csb = Cjsb (area + perimeter junction capacitance)
Cdb = Cjdb (area + perimeter junction capacitance)

M.H. Perrott 6
 OCT Thevenin Resistance Calculations
Rthgd
ID RD RD
Rthgd RG
RG
Cgd
Rthgs vgs Cgs gmvgs -gmbvs ro
Rthgs

RS

vs RS

 Cgs: Thevenin resistance between gate and source

RS (1 + RD /ro ) + RG (1 + (gmb + 1/ro )RS + RD /ro )
Rth gs =
1 + (gm + gmb )RS + (RS + RD )/ro
 Cgd: Thevenin resistance between gate and drain
Rth gd = (RD + RG )(1 − rods /ro ) + rods gm RG
RD
where rods = ro ||
1 + (gm + gmb )RS
M.H. Perrott 7
 OCT Example: Design Wide Bandwidth Amplifier

Assumptions:
RL
ID gm = 1/(100),  = 0,  = 0
Vout
Cgs = 10fF, Cgd = 3fF
Csb = 5fF, Cdb = 4fF
Rin
Rin = 4k
CL
RL = 1k
Vin CL = 100fF

 Step 1: identify AC coupling versus OCT capacitors

- AC coupling caps will be regarded as shorts
 Step 2: calculate individual OCT time constants
 Step 3: identify long OCT time constants and modify
circuit to improve its bandwidth

M.H. Perrott 8
 Step 1: Identify OCT Capacitors

Assumptions:
RL
Rth3 (Cgd) gm = 1/(100),  = 0,  = 0
Vout
Cgs = 10fF, Cgd = 3fF
Csb = 5fF, Cdb = 4fF
Rin
Rin = 4k
RL = 1k
Vin
Rth1 (CL+Cdb) CL = 100fF
Rth2 (Cgs)

 Which time constants are easy to calculate?

 How do we efficiently calculate the more difficult
cases?

M.H. Perrott 9
 Step 2: OCT Time Constant Calculations

Assumptions:
RL
Rth3 (Cgd) gm = 1/(100),  = 0,  = 0
Vout
Cgs = 10fF, Cgd = 3fF
Csb = 5fF, Cdb = 4fF
Rin
Rin = 4k
RL = 1k
Vin
Rth1 (CL+Cdb) CL = 100fF
Rth2 (Cgs)
 Easy ones:
Rth1 = RL ||Rth d = RL ||∞ = RL = 1kΩ ⇒ τ1 = 1kΩ · 104f F = 104ps
Rth2 = Rin ||Rth g = Rin ||∞ = Rin = 4kΩ ⇒ τ2 = 4kΩ · 10fF = 40ps
 Use formula for 3: Rth gd = (RD + RG )(1 − rods /ro ) + rods gm RG
RD
where rods = ro || = RD = RL
1 + (gm + gmb )RS
⇒ Rth3 = (RL + Rin )(1 − 0) + RL gm Rin = 5.5kΩ + 40kΩ = 45.5kΩ
⇒ τ3 = 45.5kΩ · 3f F = 136.5ps
M.H. Perrott 10
 Step 3: Identify Largest OCT Time Constant

Assumptions:
RL
Rth3 (Cgd) gm = 1/(100),  = 0,  = 0
Vout
Cgs = 10fF, Cgd = 3fF
Csb = 5fF, Cdb = 4fF
Rin
Rin = 4k
RL = 1k
Vin
Rth1 (CL+Cdb) CL = 100fF
Rth2 (Cgs)

 Time constant associated with Cgd is the longest:

τ3 = 45.5kΩ · 3f F = 136.5ps

 Why is this time constant so large given that it is

associated with the lowest value capacitor?
 How do we change the amplifier topology to reduce
this time constant value?
M.H. Perrott 11
 The Miller Effect Analysis Provides Helpful Intuition

RL Cgd
Cgd Vout
Rin
A
Vin
Cin Cin

 Notice that Cgd is in the feedback path of the common

source amplifier
- Recall Miller effect calculation: Cin = (1 − A)Cgd
- For this amplifier:
A = −gm RL ⇒ Cin = (1 + gm RL )Cgd = 11 · Cgd = 33f F
⇒ τ3 = Rin Cin = 4kΩ · 33f F = 132ps
 This analysis agrees well with OCT calculation of 136.5ps
Can we change the amplifier topology to lower this time constant?
M.H. Perrott 12
 Consider Adding a Cascode Device

RL
Vout
Vbias
M2
Cgd1

Rin
M1
Vin
Cin

 Examine the impact of this topological change using

the Miller Effect analysis
1
A = −gm1 ≈ −1 ⇒ Cin = (1 + 1)Cgd1 = 2 · Cgd1 = 6f F
gm2
⇒ τ3 = Rin Cin = 4kΩ · 6fF = 24ps

Cascode device dramatically reduces the Cgd1 time constant!

M.H. Perrott 13
 Does the Miller Effect Impact the Cascode Device?

RL
Cgd2 Vout
Vbias
M2

Rin
M1
Vin

 Observe that the capacitance seen by Vbias is not of

concern since this voltage is not part of the signal path
 The signal path sees the time constant:
τ4 = RL ||Rth d2 · Cgd2 ≈ RL · Cgd2 = 1kΩ · 3f F = 3ps

- This time constant is much smaller than the other time

constants of the amplifier 14
M.H. Perrott
 Perform OCT Calculations for Updated Amplifier

Rth4 (Cgd2) RL
Vout Assumptions for all devices:
Vbias gm = 1/(100),  = 0,  = 0
M2 Cgs = 10fF, Cgd = 3fF
Rth5 (Cgs2) Csb = 5fF, Cdb = 4fF
Rth1 (CL+Cdb2)
Rth3 (Cgd1)
Rin = 4k
RL = 1k
M1
Rin CL = 100fF
Vin Rth6 (Cds1+Csb2)

Rth2 (Cgs1)

Rth1 = RL ||Rth d2 = RL = 1kΩ ⇒ τ1 = 1kΩ · 104f F = 104ps

Rth2 = Rin ||Rth g1 = Rin = 4kΩ ⇒ τ2 = 4kΩ · 10f F = 40ps
Rth4 = RL ||Rth d2 ≈ RL = 1kΩ ⇒ τ3 = 1kΩ · 3f F = 3ps
Rth5 = Rth s2 ||Rth d1 ≈ 1/gm2 ||∞ = 100Ω ⇒ τ5 = 100Ω · 10f F = 1ps
Rth6 = Rth d1 ||Rth s2 = ∞||1/gm2 = 100Ω ⇒ τ6 = 100Ω · 9f F = 0.9ps
M.H. Perrott 15
 Perform OCT Calculations for Updated Amplifier

Rth4 (Cgd2) RL
Vout Assumptions for all devices:
Vbias gm = 1/(100),  = 0,  = 0
M2 Cgs = 10fF, Cgd = 3fF
Rth5 (Cgs2) Csb = 5fF, Cdb = 4fF
Rth1 (CL+Cdb2)
Rth3 (Cgd1)
Rin = 4k
RL = 1k
M1
Rin CL = 100fF
Vin Rth6 (Cds1+Csb2)

Rth2 (Cgs1)
 Use Thevenin formula for Cgd calculation:
Rth3 = (RD1 + RG1 )(1 − rods /ro1 ) + rods gm1 RG1
RD1
where rods = ro1 ||
1 + (gm1 + gmb1 )RS1
1 1
⇒ Rth3 = ( + Rin )(1 − 0) + gm1 Rin = 4.1kΩ + 4kΩ = 8.1kΩ
gm2 gm2
⇒ τ3 = 8.1kΩ · 3f F = 24.3ps 16
M.H. Perrott
 Identify Longest OCT Time Constant

Rth4 (Cgd2) RL
Vout Assumptions for all devices:
Vbias gm = 1/(100),  = 0,  = 0
M2 Cgs = 10fF, Cgd = 3fF
Rth5 (Cgs2) Csb = 5fF, Cdb = 4fF
Rth1 (CL+Cdb2)
Rth3 (Cgd1)
Rin = 4k
RL = 1k
M1
Rin CL = 100fF
Vin Rth6 (Cds1+Csb2)

Rth2 (Cgs1)

 The load capacitance now presents the largest time

constant:
Rth1 = RL ||Rth d2 = RL = 1kΩ ⇒ τ1 = 1kΩ · 104f F = 104ps

Can we change the amplifier topology to lower this time constant?

M.H. Perrott 17
 Add a Source Follower to the Output

RL For all devices:

gm = 1/(100),  = 0,  = 0
M3 Cgs = 10fF, Cgd = 3fF
Vbias Csb = 5fF, Cdb = 4fF
M2 Vout
Rin = 4k
RL = 1k
CL = 100fF
Ibias CL
M1
Rin
Vin

 Key idea: reduce the time constant associated with

CL by decreasing the Thevenin resistance that it sees
- Previous design presented R L = 1K to CL
- Source follower presents R ths3 = 1/gm3 = 100 to CL

Source follower should reduce CL time constant by a factor of ten!

M.H. Perrott 18
 Calculation of New CL Time Constant
Rth8 (Cgd3)

RL For all devices:

Rth4 (Cgd2)
gm = 1/(100),  = 0,  = 0
M3 Cgs = 10fF, Cgd = 3fF
Vbias Csb = 5fF, Cdb = 4fF
M2 Vout
Rin = 4k
Rth5 (Cgs2) Rth7 (Cgs3)
RL = 1k
Rth3 (Cgd1) CL = 100fF
Ibias
M1
Rin Rth1 (CL+Csb2)
Vin Rth6
(Cds1+Csb2)
Rth2 (Cgs1)

 Formal calculation:
Rth1 = Rth s3 = 1/gm3 = 100Ω ⇒ τ1 = 100Ω · 104f F = 10.4ps

How large are the additional time constants created by M3?

M.H. Perrott 19
 Calculation of Additional Time Constants from M3
Rth8 (Cgd3)

RL For all devices:

Rth4 (Cgd2)
gm = 1/(100),  = 0,  = 0
M3 Cgs = 10fF, Cgd = 3fF
Vbias Csb = 5fF, Cdb = 4fF
M2 Vout
Rin = 4k
Rth5 (Cgs2) Rth7 (Cgs3)
RL = 1k
Rth3 (Cgd1) CL = 100fF
Ibias
M1
Rin Rth1 (CL+Csb2)
Vin Rth6
(Cds1+Csb2)
Rth2 (Cgs1)

Rth8 = RL ||Rth d2 ≈ RL = 1kΩ ⇒ τ8 = 1kΩ · 3f F = 3ps

RS3 (1 + RD3 /ro3 ) + RG3 (1 + (gmb3 + 1/ro3 )RS3 + RD3 /ro3 )
Rth7 =
1 + (gm3 + gmb3 )RS3 + (RS3 + RD3 )/ro3
1 + RD3 /ro3 + RG3 (gmb3 + 1/ro3 ) 1+0+0
⇒ Rth7 = = = 100Ω
gm3 + gmb3 + 1/ro3 gm3 + 0 + 0
⇒ τ7 = 100Ω · 10f F = 1ps
M.H. Perrott 20
 Estimate Bandwidth Based on OCT Calculations
Rth8 (Cgd3)

RL
τ1 = 10.4ps
Rth4 (Cgd2)
τ2 = 40ps
M3
Vbias τ3 = 24.3ps
M2 Vout
τ4 = 3ps
Rth5 (Cgs2) Rth7 (Cgs3)
τ5 = 1ps
Rth3 (Cgd1)
Ibias τ6 = 0.9ps
M1
Rin Rth1 (CL+Csb2)
τ7 = 1ps
Vin Rth6
(Cds1+Csb2) τ8 = 3ps
Rth2 (Cgs1)

1 1
BW ≈ Pm = = 11.96 Grad /s
j=1 Rthj Cj 83.6ps
11.96
⇒ BW ≈ = 1.9GHz
2π

M.H. Perrott 21
 Summary

 Two techniques prove very useful when designing

amplifiers for desired frequency response behavior
- Open Circuit Time Constant method
- Miller Effect analysis
 Thevenin resistance analysis in combination with the
above offers tremendous insight for designing
amplifier topologies
- OCT method allows quick discovery of large time
constants
- Miller effect provides intuition of the impact of placing
capacitors within feedback
- Awareness of impedances presented by various
amplifier stages allows intuitive approach to achieve
reduction of large time constants

M.H. Perrott 22
 MIC511
Analysis and Design of Analog Integrated Circuits
Lecture 11

Examples

Michael H. Perrott
Masdar Institute of Science and Technology
March 4, 2012

Copyright 
c 2012 by Michael H. Perrott
All rights reserved
 Example Analysis Circuit

M15 M17
M3 M4 M7 M22

M9 M16

M18
Ibias1 M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin M14
M19
50 Ω M10 Vout
M13
Cbig M21
(external)
M24
M5 M6 M11 M12 M20

• Assumptions
1. Intrinsic gain of each device  1

gmro  1 =⇒ 1/gm  ro

2. Intrinsic gain of devices similar in value

3. Output resistances of devices similar in value

ro1 ≈ ro2

• Note:
– Assumption 1 is reasonable in practice
– Assumptions 2 and 3 are invalid in practice
∗ Used here only for pedagogical reasons
 Replace Current Sources

current
current mirror current current
source bias source source

M15 M17
M3 M4 M7 M22

M9 M16 M18

Ibias1 M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin M14
Cbig M19
50 Ω M10 Vout
(external) M13
M21

M24
M5 M6 M11 M12 M20
cascode
current current current current current bias current
mirror source source source source source
bias
current
mirror
bias

M15
M3 M4 ro7 ro22

M9 M16 (gm18ro18)ro17

Ibias1 M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin

50 Ω Cbig Vout
(external) (gm10ro10)ro11 (gm19ro19)ro20
M21
ro6 ro24
M5 (gm13ro13)ro12
cascode
current bias
mirror
bias
 Remove Non-Signal-Path Biasing Circuitry

current
mirror
bias

1 M4 ro7 1 ro22
gm3 gm15
M9 (gm18ro18)ro17

M8
Q1

50 Ω M1 M2 M23 50 Ω

Vin

50 Ω Vout
(gm10ro10)ro11 (gm19ro19)ro20
1 ro6 1 ro24
gm5 gm21
(gm13ro13)ro12
current assume
mirror cascode
cap is short bias
bias

Stage 1 Stage 2 Stage 3

1 M4 ro7 ro22
gm3
M9

M8
Q1

M1 M2 M23

50 Ω
Vin 50 Ω Vout
(gm10ro10)ro11
vinput ro6 ro24 50 Ω
(gm13ro13)ro12

assume
cap is short
 Bipolar Modeling is similar to CMOS

MOSFET BIPOLAR

Key Small-Signal Parameters Key Small-Signal Parameters

Ic kT
gm = μnCox(W/L)(VGS - VTH) gm =
Vt
,Vt =
q
= 2μnCox(W/L)ID Vt ~
~ 25 mV at room temp
βo
gmb << gm rπ = , βo ~
~ 100 to 200
gm
1 V
ro = ro = A , VA ~ ~ 100 to 200 V
λID Ic

Thevenin Resistances Thevenin Resistances

ID RD RC
IC
Rthd Rthc
RG RB

Rthg Rthb
Rths Rthe
RS RE

Approximation Assumption Approximation Assumption

Rthd= ro (1+gmRS) gmb << gm Rthc= ro (1+gm(rπ||RE)) RB << rπ

Rthg= infinite Rthb= rπ + βoRE RC+RE << ro
1 + RD /ro
Rths= gmb << gm Rthe= 1/gm + RB/βo RC << βoro
gm

General Thevenin Model General Thevenin Model

g d b c
is ie
Rths Rthe
Rthg vg Avvg α is Rthd Rthb vb Avvb α ie Rthc

s e

Approximation Assumption Approximation Assumption

Av = 1 gmb << gm , gmro >> 1 Av = 1 RC+RE << ro, RB << rπ

α= 1 Rd << Rthd α= 1 RC+RE << βoro
 Compute 2-port for Stage 3

M23

ro22

vg vg 1 Q25 50||ro24 50
Vb gm23

1
gm25
vb25 rπ + βo50 vb25 50 vout

rπ + βo(50||ro24) ( g 1 ||ro22)
1 m23 1
rπ + βo50
Stage 3 gm25 βo gm25

ro22
1
(rπ + βo50)||ro22 gm25
vg vg 50 vout
1 (rπ + βo50)||ro22
output Vb gm23
resistance Q25
of Stage 2 Vb
M23

Vb
(gm10ro10)ro11
Vout 1
(rπ + βo50)||ro22 gm25
vg vg 50 vout
ro24 1 (rπ + βo50)||ro22
50 Ω gm23
 Compute 2-port for Stage 2

ro7
Va (ro7||ro4||ro2)(gm8ro8)(gm9(ro9||RA))
ia ro7/3(gm8ro8)(gm9ro9)

1
gm8
αis ro7/3(gm8ro8)(gm9ro9)

is

1 + RD /ro8 is Vb
gm8(gm9(ro9||RA))
Stage 2 1 + (gm10ro10)ro11 /ro8
gm8(gm9ro9) (gm10ro10)ro11
RD
(gm10ro10)ro11 /ro8
ro7 gm8(gm9ro9)
output
resistance ro11 /ro8 1
of Stage 1 Va M9 gm8 gm8

ro7
M8 input is = ia ia
ro2||ro4 resistance 1 +r
o7
of Stage 3 gm8
Vb
Va Vb
is

1 is (gm10ro10)ro11
(gm10ro10)ro11 gm8

RD RA
(gm13ro13)ro12 1 1
||r
gm8 o7 gm8
 Compute 2-port for Stage 1 (Step 1)

Stage 1

1 M4
gm3 input
resistance
Va of Stage 2

1
gm8
M1 M2

50 Ω
Vin 50 Ω

vinput ro6 Calculate Thevenin resistances

1 M4
gm3 input
resistance
ro4 of Stage 2
ro1(1+gm1 1 )
gm2 ro2(1+gm2 1 )
2ro1 gm1
2ro2 1
25 Ω gm8
M1 M2
vinput Vin
2
infinite
1 1 1 1
gm2 ||ro6 gm2 gm1 ||ro6 gm1
ro6
 Compute 2-port for Stage 1 (Step 2)

Calculate short circuit current at output

1 M4
gm3
M1 ro4
25 Ω is1 i2 = gm4 1 is1 is1
gm3
is1
vinput Vin 1
gm1
2 vg1 vg1 αis1 2ro1
is1 isc

M2
Vin
is1 =
1 1
gm1 gm2 is1
gm1 1
Vin gm2
2 ro6
isc 2is1 Vin gm1

Calculate output resistance

gm4vg4
1 vg4 ro4
gm3 vt M4
i1 ro4
it
ro1(1+gm1 1 )
gm2 vt
2ro1 i 1= 2ro2 vt
i1 2ro2
25 Ω
M1 M2
Vin
i1 i1

1
gm1
ro6 vt vt vt
it +2i1 = r +2
ro4 o4 2ro2
vt
= ro2||ro4
it
 Compute 2-port for Stage 1 (Final Step)

Stage 1

1 M4
gm3 input
resistance
Va of Stage 2

1
gm8
M1 M2

50 Ω
Vin 50 Ω

vinput ro6
25 Ω Va
Vin
vinput
vg1 gm1vg1 ro2||ro4
2
 Overall Cascade of 2-ports for Amplifier

Stage 1
25 Ω Va
Vin
vinput
vg1 gm1vg1 ro2||ro4
2

Stage 2
Vb
ib

1 ib (gm10ro10)ro11
gm8

Stage 3

1
(rπ + βo50)||ro22 gm25
vg vg 50 vout
1 (rπ + βo50)||ro22
gm23

• What is the overall input/output resistance of the amp?

• What is the overall gain?
• Which stage contributes the most gain?
• What is the function of each stage?
 Analysis and Design of Analog Integrated Circuits
Lecture 12

Feedback

Michael H. Perrott
March 11, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Open Loop Versus Closed Loop Amplifier Topologies
Open Loop Closed Loop
Zf
Source Source
Zsrc Amp Vout Zsrc Amp Vout
Vin Vin
Vsrc Vsrc

Vout/Vin Vout/Vin

(dB) (dB)

w (rad/s) w (rad/s)
wbw w1 w2 wbw w1 w2

 Open loop – want all bandwidth limiting poles to be as

high in frequency as possible
 Closed loop – want one pole to be dominant and all other
parasitic poles to be as high in frequency as possible
M.H. Perrott 2
 Consider an Open Loop Integrator

Vout/Vin
wunity (dB)
Vout
s
Vin

H(w)
Vin Vout 0 dB
H(s)
w (rad/s)
wunity

 Parameterize integrator in terms of its unity gain

frequency, wunity rad/s
- Define H(s) = w unity/s
- Note that |H(w unity)| =1

M.H. Perrott 3
 Now Surround the Integrator with a Feedback Path

20log Vout/(Vin-Vx)
Z2 (dB)

Vx
Z1 Vout
H(s)
H(w)

Vin 0 dB
w (rad/s)
wunity

 The feedforward path is H(s) = wunity/s

 The feedback path is formed by Z1 and Z2
 Derivation of closed loop transfer function:
Vout − Vx Vx − 0
= and Vout = H(s)(Vin − Vx )
Z2 Z1
Vout H(s)
⇒ =
Vin 1 + Z1 /(Z1 + Z2 )H(s)
M.H. Perrott 4
 Observations of Impact of Feedback

20log Vout/Vin
Z2

Vx 20log(1/β)
Z1 Vout
H(s)
H(w)

Vin 0 dB
w (rad/s)
wbw wunity

 Define  = Z1/(Z1+Z2) and rewrite transfer function as:

Vout H(s) H(s)
= =
Vin 1 + Z1 /(Z1 + Z2 )H(s) 1 + β · H(s)
 At low frequencies: At high frequencies:
¯ ¯ ¯ ¯
¯ Vout ¯ ∞ 1 ¯ Vout ¯
¯ ¯ = = ¯ ¯ = |H(w)|
¯ Vin ¯ 1+β·∞ β ¯ Vin ¯
s→0 s→∞
(since |β · H(w)| ¿ 1)
M.H. Perrott 5
 General View of Feedback

20log Vout/Vin
Z2

Vx 20log(1/β)
Z1 Vout
H(s)
H(w)

Vin 0 dB
w (rad/s)
wbw wunity

Vin
H(s)
Vout  Closed loop transfer function:
Vout H(s)
=
β Vin 1 + β · H(s)
- This is called Black’s formula
 ¯
At low frequencies:
¯
At high frequencies:
¯ ¯
¯ Vout ¯ 1 ¯ Vout ¯
¯ ¯ = ¯ ¯ = |H(w)|
¯ Vin ¯ β ¯ Vin ¯
s→0 s→∞ 6
M.H. Perrott
 General Observations of Feedback

20log Vout/Vin
Vin Vout
H(s)

20log(1/β)
β
H(w)
Vout H(s)
= 0 dB
Vin 1 + β · H(s) w (rad/s)
wbw wunity

 The feedback path sets the closed loop gain at low

frequencies
- Assumes the open loop gain is large at low frequencies
- Implies that accurate closed loop gain can be achieved
at low frequencies despite variations in open loop gain
 The feedback path also influences the closed loop
bandwidth
M.H. Perrott 7
 Gain Bandwidth Product for Closed Loop Systems

20log Vout/Vin
Vin Vout
H(s)

20log(1/β)
β
H(w)
Vout H(s)
= 0 dB
Vin 1 + β · H(s) w (rad/s)
wbw wunity
¯ ¯
 The low frequency gain is: ¯ Vout ¯
¯ ¯ 1
¯ Vin ¯ =
s→0 β
1
 The bandwidth roughly corresponds to: |H(wbw )| ≈
β
¯ ¯
wunity ¯ wunity ¯ 1 1
For H(s) = ⇒ ¯ ¯ ¯ ≈ ⇒ wunity = · wbw
s wbw ¯ β β
Closed loop systems exhibit constant gain-bandwidth product
set by the unity gain frequency of the open loop amplifier
M.H. Perrott 8
 Example: Unity Gain Amplifier

20log Vout/Vin
Vin Vout
H(s)

β=1
H(w)
Vout H(s)
= 0 dB
Vin 1 + H(s) w (rad/s)
wunity
¯ ¯
 The low frequency gain is: ¯ Vout ¯
¯ ¯
¯ Vin ¯ =1
s→0
 The bandwidth roughly corresponds to: |H(wbw )| ≈ wunity

 Gain bandwidth product is wunity: 1 · wunity = wunity

Unity gain closed loop amplifiers maximize the

closed loop bandwidth assuming closed loop gain ≥ 1
M.H. Perrott 9
 Issue: Open Loop Amplifiers have Finite DC Gain

20log Vout/Vin
Vin Vout
H(s)
20log(K)

β=1
H(w)
Vout H(s)
= 0 dB
Vin 1 + H(s) w (rad/s)
wdominant wunity
 Let us now model H(s) as:
K
H(s) =
1 + s/wdominant
 To first order, the closed loop bandwidth and gain are
relatively unchanged

What is the impact of having finite, open loop, DC gain?

M.H. Perrott 10
 Further Examination of Finite, Open Loop, DC Gain

20log Vout/Vin K
Vin Vout H(s) =
H(s)
20log(K)
1 + s/wdominant

β=1
H(w)
Vout H(s)
= 0 dB
Vin 1 + H(s) w (rad/s)
wdominant wunity

 For unity gain configuration of closed loop amplifier:

¯ ¯ ¯
¯ Vout ¯ H(s) ¯ K 1
¯ ¯ = ¯ = =
¯ Vin ¯ ¯
1 + H(s) s→0 1 + K 1 + 1/K
s→0
 We see that finite open loop DC gain leads to a slight
reduction of the closed loop DC gain
- We want K >> 1 for the unity gain closed loop amplifier
M.H. Perrott 11
 More General View of Finite, Open Loop, DC Gain

20log Vout/Vin K
Vin Vout H(s) =
H(s) 20log(K) 1 + s/wdominant
20log(1/β)
β
H(w)
Vout H(s)
= 0 dB
Vin 1 + β · H(s) w (rad/s)
wbw wunity

 For general configuration of closed loop amplifier:

¯ ¯ µ ¶
¯ Vout ¯ K 1 1
¯ ¯ = =
¯ Vin ¯ 1+β·K β 1 + (1/β)/K
s→0
 Finite open loop DC gain still leads to reduction of
closed loop DC gain
- We want K >> 1/ in this case
- We will see implications of this issue later in the class 12
M.H. Perrott
 The Issue of Parasitic Open Loop Poles

20log Vout/Vin
Vin Vout
H(s) 20log(K)
20log(1/β)
β
H(w)
Vout H(s)
=
Vin 1 + β · H(s) w (rad/s)
wbw wp

 Practical amplifiers have non-dominant poles, too:

µ ¶µ ¶
K 1
H(s) =
1 + s/wdominant 1 + s/wp
- Of course, there can be multiple parasitic poles and also
zeros
 A key issue of such parasitic poles is their influence
on the stability of the closed loop amplifier
M.H. Perrott 13
 Key Tool for Assessing Stability: Open Loop Response

20log Vout/Vin
Vin Vout
H(s) 20log(K)
20log(1/β)
β
H(w)
Vout H(s)
=
Vin 1 + β · H(s) wbw wp
w (rad/s)

 We define the open loop response, A(s), as:

A(s) = β · H(s)
 Note that the unity gain frequency, w0 , of A(w) is
approximately the same as the closed loop bandwidth, wbw
|A(w0 )| = 1 ⇒ β · |H(w0 )| = 1 ⇒ |H(w0 )| = 1/β
- Looking at the plot above, we can see that the intersection of
|H(w)| and 1/ corresponds to the closed loop bandwidth, wbw
M.H. Perrott 14
 Stability Analysis Based on Phase Margin of A(w)

 Phase margin is a key metric when examining the

stability of a system
- Phase margin is defined as 180° + phase{A(w )} 0
 w0 corresponds to the unity gain frequency of the open
loop response (i.e., |A(w0)| = 1)
 w0 is approximately the same as the closed loop
bandwidth, wbw
- Phase margin must be greater than 0 degrees for the
closed loop system to be stable
 Typically want phase margin to be greater than 45°

 Key skill: you must be able to plot Bode plots in both

magnitude and phase!

M.H. Perrott 15
 Review of Bode Plot Basics

 Example:
1 + jw/wz
A(w) =
(1 + jw/wp1 )(1 + jw/wp2 )
- Log of magnitude (dB): 20 log |A(w)|
= 20 log |1 + jw/wz | − 20 log |1 + jw/wp1 | − 20 log |1 + jw/wp2 |

 Taking the log allows the poles and zeros to be plotted

separately and then added together
- Phase: 6 A(w)

= 6 (1 + jw/wz ) − 6 (1 + jw/wp1 ) − 6 (1 + jw/wp2 )

 Phase of poles and zeros can also be plotted separately

and then added together

M.H. Perrott 16
 Review: Plotting the Magnitude of Poles

 Plot the magnitude response of pole wp1

¯ ¯
¯ 1 ¯
20 log |Ap1 (w)| = 20 log ¯¯ ¯ = −20 log |1 + jw/wp1 |
1 + jw/wp1 ¯
- For w << w p1: 20 log |Ap1 (w)| ≈ −20 log |1| = 0

- For w >> w p1: 20 log |Ap1 (w)| ≈ −20 log |w/wp1 |

20log|Ap1(ω)|

0 dB ω
ωp1
-20 dB/decade

M.H. Perrott 17
 Plotting the Phase of Poles

 Plot the phase response of pole wp1

6 Ap1 (w) = −6 (1 + jw/wp1 ) = − arctan (w/wp1 )

- For w << w : p1
6 Ap1 (w) ≈ − arctan (0) = 0◦

- For w = w : p1
6 Ap1 (w) ≈ − arctan (1) = −45◦

- For w >> w : p1
6 Ap1 (w) ≈ − arctan (∞) = −90◦
Ap1(ω)
ωp1/10 ωp1 ωp1∗10
0 o
ω

-45o
o
-90
M.H. Perrott 18
 Review: Plotting the Magnitude of Zeros

 Plot the magnitude response of zero wz

20 log |Az (w)| = 20 log |1 + jw/wz |

- For w << w :
z 20 log |Az (w)| ≈ 20 log |1| = 0

- For w >> w :
z 20 log |Az (w)| ≈ 20 log |w/wz |

20log|Az(ω)|

20 dB/decade

0 dB ω
ωz
M.H. Perrott 19
 Plotting the Phase of Zeros

 Plot the phase response of zero wz

6 Az (w) = 6 (1 + jw/wz ) = arctan (w/wz )

- For w << w : z
6 Az (w) ≈ arctan (0) = 0◦

- For w = w :z
6 Az (w) ≈ arctan (1) = 45◦

- For w >> w : z
6 Az (w) ≈ arctan (∞) = 90◦
Az(ω)
o
90

45o

0
o ω
ωz/10 ωz ωz∗10
M.H. Perrott 20
 Example of Closed Loop Stability Evaluation

20log Vout/Vin
Vin Vout
H(s)

20log(1/β)
β
H(w)
Vout H(s)
=
Vin 1 + β · H(s) wbw wp
w (rad/s)

 Consider the case where:

µ ¶µ ¶
K 1
H(s) =
s 1 + s/wp
- This implies that: µ ¶µ ¶
K 1
A(s) = β
s 1 + s/wp

M.H. Perrott 21
 Phase Margin Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations
Im{s}
Open loop 20log|A(f)| C
gain
increased
Dominant
pole pair B

0 dB f
fp
A
C
B
A Re{s}
angle(A(f)) 0
o
-90
A
-120o PM = 59o for A
PM = 45o for B
B
-150o PM = 33o for C

-180o C

 Note the closed loop pole locations versus open loop gain
- Is the closed loop system unstable for any case above?
M.H. Perrott 22
 Corresponding Closed Loop Behavior
Closed Loop Frequency Response Closed Loop Step Response
C
5 dB C 1.4
B
0 dB B
A
-5 dB A
1

0.6

f 0 t
fp

 Frequency response sees more peaking with higher open

loop gain
- How does this relate to the movement of the closed loop pole
locations?
 Step response see more ringing with higher open loop gain
- How does this relate to the closed loop frequency response?
M.H. Perrott 23
 Some Key Observations

20log Vout/Vin
Vin Vout
H(s)

20log(1/β)
β
H(w)
Vout H(s)
=
Vin 1 + β · H(s) w (rad/s)
wbw wp
A(s) = β · H(s)
 We have seen that increasing the open loop gain of A(w)
leads to higher closed loop bandwidth
- How is this consistent with the statement that increasing
closed loop gain leads to lower closed loop bandwidth?
 As an exercise, consider the impact of the following:
- Keep  unchanged and increase the open loop gain of H(w)
-
M.H. Perrott
Keep H(w) unchanged and increase 
24
 Example 2 of Closed Loop Stability Evaluation

20log Vout/Vin
Vin Vout
H(s)

20log(1/β)
β
H(w)
Vout H(s)
=
Vin 1 + β · H(s) wbw wp1,wp2,wp3
w (rad/s)

 Consider the case where:

µ ¶µ ¶
K 1 1 1
H(s) =
s 1 + s/wp1 1 + s/wp2 1 + s/wp3
- This implies
µ ¶µ
that:
¶
K 1 1 1
A(s) = β
s 1 + s/wp1 1 + s/wp2 1 + s/wp3

M.H. Perrott 25
 Phase Margin Versus Open Loop Gain
Evaluation of Closed Loop Pole
Phase Margin Locations
Im{s}
20log|A(f)|
Open loop C
gain
increased
Dominant
pole pair
0 dB f
fp1 fp2fp3
Non-dominant B
poles
C
B A Re{s}
angle(A(f)) A
-90
o
A 0
PM = 72o for A
PM = 51o for B
-165
o B
o
-180
PM = -12o for C
o
-240

o
-315 C

 Note the closed loop pole locations versus open loop gain
- Is the closed loop system unstable for any case above?
M.H. Perrott 26
 Corresponding Closed Loop Behavior

Closed Loop Frequency Response Closed Loop Step Response

C

0 dB B
A C

1 B

Frequency Time

 Frequency response again sees more peaking with higher

open loop gain
- How does this relate to the movement of the closed loop pole
locations?
 Step response ringing grows for high open loop gain
- How does this relate to the closed loop pole locations?
M.H. Perrott 27
 Open Loop Versus Closed Loop Amplifier Topologies
Open Loop Closed Loop
Zf
Source Source
Zsrc Amp Vout Zsrc Amp Vout
Vin Vin
Vsrc Vsrc

Vout/Vin Vout/Vin

(dB) (dB)

w (rad/s) w (rad/s)
wbw w1 w2 wbw w1 w2

 Now that we understand the phase margin criterion, can

you explain why amplifiers designed to be within a closed
loop system should have one dominant pole that is much
lower in frequency than the parasitic poles?
M.H. Perrott 28
 Summary

 Feedback systems offer the benefit of accurate gain at

low frequencies
- Assumes accurate feedback and high open loop DC gain
- Gain-bandwidth product of the closed loop system
equals wunity of the open loop amplifier
 Accuracy of the closed loop DC gain is reduced with
lower open loop DC gain
- Want the open loop DC gain to be much higher than the
desired closed loop DC gain for reasonable accuracy
 Stability of the closed loop system is often evaluated
using the phase margin criterion
- Examines the phase at unity gain frequency of the open
loop response, A(w0) =  · H(w0), where |A(w0)| = 1
 w0 is approximately the same as the closed loop
bandwidth, wbw
M.H. Perrott 29
 Analysis and Design of Analog Integrated Circuits
Lecture 13

Basics of Noise

Michael H. Perrott
March 14, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Continuous-Time Versus Discrete-Time Signals
Real World Signal Samples of Real World Signal
x(t) x[n]

t n
1
 Real world signals, such as acoustic signals from speakers
and RF signals from cell phones, are continuous-time in
nature
 Digital processing of signals requires samples of real world
signals, which yields discrete-time signals
 Analog circuits are used to sample and digitize real world
signals for use by digital processors
 It is useful to study discrete-time signals when examining
the issue of noise
- Many insights can be applied back to continuous-time signals
M.H. Perrott 2
 Definition of Mean, Power, and Energy
x[n]

n
1
 DC average or mean, x, is defined as

 Power, Px, and energy, Ex, are defined as

- For many systems, we often remove the mean since it is

often irrelevant in terms of information:

M.H. Perrott 3
 Definition of Signal-to-Noise Ratio

signal[n] rx[n]
A
n

noise[n]

 Signal-to-Noise ratio (SNR) indicates the relative impact

of noise on system performance

 We often like to use units of dB to express SNR:

M.H. Perrott 4
 SNR Example
SNR = 20.4 dB

signal[n] rx[n]
A n
n

noise[n]
SNR = 10.7 dB
n

 Scaling the gain factor A leads to SNR = 0.4 dB

different SNR values
- Lower A results in lower SNR
- Signal quality steadily degrades n
with lower SNR
M.H. Perrott 5
 Analysis of Random Processes


noise[n] (Trial 1)
Random processes, such as noise,
take on different sequences for
different trials n

- Think of trials as different

measurement intervals from the
same experimental setup
noise[n] (Trial 2)
 For a given trial, we can apply our
standard analysis tools and metrics n
- Fourier transform, mean and power
calculations, etc…
 When trying to analyze the noise[n] (Trial 3)

ensemble (i.e. all trials) of possible

outcomes, we find ourselves in
need of new tools and metrics n

M.H. Perrott 6
 Tools and Metrics for Random Processes

 Assume that random processes we will deal with have

the properties of being stationary and ergodic
- True for noise in many practical systems
- Greatly simplifies analysis
 Examine in both time and frequency domains
- Time domain
 Introduce the concept of a probability density function (PDF)
to characterize behavior of signals at a given sample time
 Use PDF to calculate mean and variance
 Similar to mean and power of non-random signals
- Frequency domain
 We will discuss a more proper framework in the next lecture
 For now, we will simply use Fourier analysis (i.e., Fast
Fourier Transform, FFT) on signals from individual trials

M.H. Perrott 7
 Stationary and Ergodic Random Processes


noise[n][trial=1]
Stationary
- Statistical behavior is
independent of shifts in n

time in a given trial:

 Implies noise[k] is
statistically
noise[n][trial=2]
indistinguishable noise[n=k][trial]

from noise[k+N]
 Ergodic
trial n

- Statistical sampling
can be performed at one noise[n][trial=3]
sample time (i.e., n=k)
across different trials, or
across different sample
times of the same trial n

with no change in the

statistical result n=k
8
M.H. Perrott
 Examples

 Non-Stationary  Stationary, but Non-Ergodic

noise[n] (Trial 1) noise[n] (Trial 1)

n
n

noise[n] (Trial 2)

noise[n] (Trial 3)

M.H. Perrott 9
 Experiment to see Statistical Distribution
noise[n] (Trial = 1)
Histogram of 100 samples

sample
value
Histogram of 1,000 samples

 Create histograms of
sample
sample values from trials Histogram of 10,000 samples
value

of increasing lengths
 Assumption of stationarity
implies histogram should sample
value
converge to a shape Histogram of 1,000,000 samples

known as a probability
density function (PDF)
sample
value
M.H. Perrott 10
 Formalizing the PDF Concept

 Define x as a Histogram
random variable
whose PDF has the
same shape as the sample
value
histogram we just
obtained
 Denote PDF of x as PDF
fX(x)

fX(x) Area = 1
- Scale f (x) such
X
that its overall
x
area is 1

This shape is referred

to as a Gaussian PDF
M.H. Perrott 11
 Formalizing Probability

 The probability that random variable x takes on a value in

the range of x1 to x2 is calculated from the PDF of x as:

fX(x)
PDF

x
x1 x2

- Note that probability values are always in the range of 0 to 1

- Higher probability values imply greater likelihood that the
event will occur

M.H. Perrott 12
 Example Probability Calculation

fX(x) This shape is

referred to as a
1/2 uniform PDF

x
0 0.5 1.0 2

 Verify that overall area is 1:

 Probability that x takes on a value between 0.5 and 1.0:

M.H. Perrott 13
 Examination of Sample Value Distribution
x

noise[n]

fX(x)
n

noise[k] = x

 Assumption of ergodicity implies the value occurring at a

given time sample, noise[k], across many different trials
has the same PDF as estimated in our previous
experiment of many time samples and one trial
 We can model noise[k] as the random variable x
M.H. Perrott 14
 Probability Calculation
x

x2
noise[n]

fX(x)
n
x1

noise[k] = x

 In a given trial, the probability that noise[k] takes on a

value in the range of x1 to x2 is computed as

M.H. Perrott 15
 Mean and Variance
fX(x)

x
μx
 The mean of random variable x, x, corresponds to its
average value
- Computed as
 The variance of random variable x, x2, gives an
indication of its variability
- Computed as

- Similar to power of a signal

M.H. Perrott 16
 Visualizing Mean and Variance from a PDF
Changes in mean of x Changes in variance of x
fX(x) fX(x)
Smaller Smaller
Mean Variance

x x
0 μx=A μx
fX(x) fX(x)
Larger Larger
Mean Variance

x x
0 μx=B μx

 Changes in mean shift the center of mass of PDF

 Changes in variance narrow or broaden the PDF
- Note that area of PDF must always remain equal to one 17
M.H. Perrott
 Example Mean and Variance Calculation

fX(x)
1/2

x
0 2

 Mean:

 Variance:

M.H. Perrott 18
 Frequency Domain View of Random Process
 It is valid to take noise[n] (Trial 1) Magnitude of fft of noise[n] (Trial 1)

the FFT of a
sequence from n
a given trial λ

 However, notice
-0.5 0 0.5

that the FFT noise[n] (Trial 2) Magnitude of fft of noise[n] (Trial 2)

result changes
across trials
- Fourier n

λ
Transform of a -0.5 0 0.5
random
process is noise[n] (Trial 3) Magnitude of fft of noise[n] (Trial 3)

undefined !
- We need a
new tool n
λ
called spectral -0.5 0 0.5

analysis 19
M.H. Perrott
 White Noise

White Noise

Magnitude of fft of noise[n]

λ
-0.5 0 0.5

 When the FFT result looks relatively flat, we refer to the

random process as being white
- Note: this type of noise source is often used for calibration
of advanced stereo systems

M.H. Perrott 20
 Shaped Noise

White Noise Shaped Noise

Magnitude of fft of noise[n] Magnitude of fft of filtered noise[n]

λ λ
-0.5 0 0.5 -0.5 0 0.5
Highpass
noise[n] filtered noise[n]
H(ej2πfλ)

 Shaped noise occurs when white noise is sent into a filter

- FFT of shaped noise will have frequency content according
to the type of filter
 Example: highpass filter yields shaped noise with only high
frequency content

M.H. Perrott 21
 Summary
 Discrete-time processes provide a useful context for
studying the properties of noise
- Analog circuits often convert real world (continuous-
time) signals into discrete-time signals
 Signal-to-noise ratio is a key metric when examining
the impact of noise on a system
 Noise is best characterized by using tools provided by
the study of random processes
- We will assume all noise processes we deal with are
stationary and ergodic
- Key metrics are mean and variance
- Frequency analysis using direct application of Fourier
Transforms is fine for one trial, but not valid when
considering the ensemble of a random process
We will consider spectral analysis for continuous-time signals
in the next lecture 22
M.H. Perrott
 Analysis and Design of Analog Integrated Circuits
Lecture 14

Noise Spectral Analysis for Circuit Elements

Michael H. Perrott
March 18, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Recall Frequency Domain View of Random Process
 It is valid to take noise[n] (Trial 1) Magnitude of fft of noise[n] (Trial 1)

the FFT of a
sequence from n
a given trial λ

 However, notice
-0.5 0 0.5

that the FFT noise[n] (Trial 2) Magnitude of fft of noise[n] (Trial 2)

result changes
across trials
- Fourier n

λ
Transform of a -0.5 0 0.5
random
process is noise[n] (Trial 3) Magnitude of fft of noise[n] (Trial 3)

undefined !
- We need a
new tool n
λ
called spectral -0.5 0 0.5

analysis 2
M.H. Perrott
 Expectation of a Random Variable

 The expectation of random variable y is defined as

Z ∞
E(y) = yfy (y)dy
−∞
- We see that: Z ∞
E(y) = yfy (y)dy = μy
−∞
Z ∞
E((y − μy )2 ) = (y − μy )2 fy (y)dy = σy2
−∞

- In the case where  y = 0 (i.e., the mean of y is 0)

E(y 2 ) = E((y − μy )2 ) = σy2

 E(y2) is called the second moment of random variable y

M.H. Perrott 3
 Independence of Random Variables

 Consider two random variables x and y

- x and y are said to be independent if and only if
f (x, y) = f (x)f (y)
 Where f(x,y) is the joint probability distribution of x and y
- which implies
Z ∞ Z ∞ Z ∞
E(xy) = xyf (x, y)dxdy = xf (x)dx yf (x)dy
−∞ −∞ −∞

⇒ E(xy) = E(x)E(y)

 The above relationship is also true under a less strict

condition called linear independence
 If x and y are zero mean, then E(xy) = 0 implies that x
and y are uncorrelated
M.H. Perrott 4
 Autocorrelation and Spectral Density (Discrete-Time)

 Assume a zero mean, stationary random process x[n]:

- The autocorrelation of x[n] is defined as:
Rxx [m] = E(x[n] · x[n + m])
 Note that:

Rxx [0] = E(x2 [n]) = σx2

- The power spectral density of random process x[n] is
defined as ∞
X
Sx (λ) = Rxx [m]e−j2πλm
m=−∞
 Note that  = fT, where f is frequency (in Hz) and T is the
sample period of the process (in units of seconds)
 Power spectral density of x[n] is essentially the (Discrete-
Time) Fourier Transform of the autocorrelation of x[n]
M.H. Perrott 5
 Implications of Independence (Discrete-Time)

 If the samples of a zero mean random process, x[n],

are independent of each other, this implies
Rxx [m] = E(x[n]x[n + m])
½
E(x2 [n]) = σx2 , m=0
=
6 0
E(x[n])E(x[n + m]) = 0, m =
 The corresponding power spectral density is then
calculated as
∞
X
⇒ Sx (λ) = Rxx [m]e−j2πλm = σx2
m=−∞

- This is a known as a white random process, whose

spectral density is flat across all frequencies

M.H. Perrott 6
 Understanding White Random Processes
noise[n] (Trial = 1)
Histogram of 100 samples

sample
value
Histogram of 1,000 samples

 Independence between
samples implies that previous
samples provide no benefit in sample
value
trying to predict the value of Histogram of 10,000 samples

the current sample

 For Gaussian white processes,
sample
the best we can do is use the Histogram of 1,000,000 samples
value

Gaussian PDF to determine the

probability of a sample being
within a given range sample
- Variance of the process is a value

key parameter
M.H. Perrott 7
 Spectral Density of a White Process (Discrete-Time)
noise[n] (Trial 1) Magnitude of fft of noise[n] (Trial 1)

n
λ
-0.5 0 0.5

Spectral Density of noise[n]

σx2

λ
-0.5 0 0.5

 The spectral density of a white process is well defined

- This is in contrast to the FFT of a white process, which varies
between different trials of the process
- Note that the spectral density is double-sided since it is
based on the Fourier Transform (which is defined for both
positive and negative frequencies)
M.H. Perrott 8
 Autocorrelation and Spectral Density (Continuous-Time)

 Assume a zero mean, stationary random process x(t):

- The autocorrelation of x(t) is defined as:
Rxx (τ ) = E(x(t) · x(t + τ ))
 Note that
Rxx (0) = E(x2 (t)) = σx2

- The power spectral density of random process x(t) is

defined as
Z ∞
Sx (f ) = Rxx (τ )e−j2πf τ dτ
τ =−∞

 Again, the power spectral density corresponds to the

Fourier Transform of the autocorrelation function of the
random process x(t)
M.H. Perrott 9
 White Random Process (Continuous-Time)

 Assume a zero mean, stationary random process x(t):

- Assuming that the samples of a random process, x(t), are
independent of each other, this implies
Rxx (τ ) = E(x(t)x(t + τ )) = No δ(t)

 Where (t) is known as the delta function with properties:

Z ∞
δ(t) = 0 for t 6= 0, δ(t)dt = 1
−∞
- The power spectral
Z
density of x(t) is then:
∞
Sx (f ) = Rxx (τ )e−j2πf τ dτ = No
τ =−∞
 As with a discrete-time white process, a continuous-time
white process has flat spectral density across all frequencies
 Note that the variance of a white process is actually infinite
 Practical “white noise” is bandlimited and has finite variance
M.H. Perrott 10
 Spectral Density of a White Process (Continuous-Time)

Noise(t) (Trial 1) Spectral Density of Noise(t)

0 t No

f
0

 As with a discrete-time, white process, the spectral

density of a continuous-time, white process is well
defined
- It is flat with frequency
- For analog circuits, units of N are V /Hz or A /Hz
o
2 2

- It is double-sided, meaning that it is defined for both

positive and negative frequencies

M.H. Perrott 11
 Spectral Density Calculations Involving Filtering
Sx(f) Sy(f)
x(t) y(t) 4No
H(s)
No

f H(f) f
0 -f2 -f1 0 f1 f2
2
f
-f2 -f1 0 f1 f2
 Assuming an input random process x(t) is fed into a linear,
time-invariant filter H(s), the resulting power spectral
density of the output random process y(t) is calculated as:

Sy (f ) = |H(f )|2 Sx (f )
- Note that filtering a white random process leads to a new
random process that is no longer white
 The output spectral density is no longer flat across frequency
 Different output samples in time are no longer independent 12
M.H. Perrott
 Spectral Density Calculations Involving Power
Sx(f) Sy(f)
x(t) y(t) 4No
H(s)
No

f H(f) f
0 -f2 -f1 0 f1 f2
2
f
-f2 -f1 0 f1 f2

 The power (i.e., variance) of a zero mean random process

corresponds to the integration of its power spectral density
Z ∞ Z −f1 Z f2
Py = σy2 = Ryy (0) = Sy (f )df = Sy (f ) + Sy (f )
−∞ −f2 f1
- Note that we can consider the power in certain frequency
bands by changing the value of f and f 1 2
- In the above example:
Py = 4No · 2(f2 − f1 )
M.H. Perrott 13
 Double-Sided Versus Single-Sided Spectral Densities
Sx(f) Sy(f)
x(t) y(t) 8No
H(s)
2No

f H(f) f
0 0 f1 f2
2
f
0 f1 f2

 It turns out that power spectral densities are always

symmetric about positive and negative frequencies
 Single-sided spectral densities offer a short cut in which
only the positive frequencies are drawn
- In order to conserve power, the spectral density magnitude
is doubled
- For the above example: ⇒ Py = 8No · (f2 − f1 )
We will use only single-sided spectral densities in this class
M.H. Perrott 14
 Noise in Resistors

 Corresponds to white noise (i.e., thermal noise) in

terms of either voltage or current

R
R in2
vn2

1
vn2 = 4kT R∆f 2
in = 4kT ∆f
R
- Circuit designers like to use the above notation in which
2vvnn2 and ini2n represent power in a given bandwidth f in
2
units of Volts2 or Amps2, respectively
- k is Boltzmann’s constant: k = 1.38 × 10−23J/K
- T is temperature (in Kelvins)
 Usually assume room temperature of 27 degrees Celsius
⇒ T = 300K 15
M.H. Perrott
 Noise In Inductors and Capacitors

 Ideal capacitors and inductors have no noise!

C L

 In practice, however, they will have parasitic resistance

- Induces noise
- Parameterized by adding resistances in parallel/series
with inductor/capacitor
 Include parasitic resistor noise sources

M.H. Perrott 16
 Noise in CMOS Transistors (Assumed in Saturation)

ID Transistor Noise Sources

D
G
Drain Noise (Thermal and 1/f)
S Gate Noise (Induced and Routing Parasitic)

 Modeling of noise in transistors includes several noise

sources
- Drain noise
 Thermal and 1/f – influenced by transistor size and bias
- Gate noise
 Induced from channel – influenced by transistor size and bias
 Caused by routing resistance to gate (including resistance of
polysilicon gate)
 Can be made negligible with proper layout such as fingering of
devices
We will ignore gate noise in this class
M.H. Perrott 17
 Drain Noise – Thermal (Assume Device in Saturation)

ind

VGS G
VD>ΔV

S D

 Thermally agitated carriers in the

channel cause a randomly varying 2
¯ ind
current ¯ Δf
2
ind¯¯ = 4kT γgdso∆f
th
-  is called excess noise factor
4kTγgdso
 = 2/3 in long channel
 = 2 to 3 (or higher!) in short f

channel MOS devices

- gdso will be discussed shortly (Note: gdso = gm /α)
M.H. Perrott 18
 Drain Noise – 1/f (Assume Device in Saturation)

ind

VGS G
VD>ΔV

S D

 Traps at channel/oxide interface

randomly capture/release carriers 2
ind
Δf
drain

- Parameterized by Kf 4kTγgdso
1/f noise
drain thermal noise

 Kf provided by fab
f
 Sometimes Kf of PMOS << Kf of 1/f noise
corner frequency
NMOS due to buried channel
- To minimize: want large area (high WL) 19
M.H. Perrott
 Drain-Source Conductance: gdso

 gdso is defined as channel resistance with Vds=0

- Transistor in triode, so that

¯
dId ¯¯ W
⇒ gdso = ¯ = μnCox (Vgs − VT )
¯
dVds V =0 L
ds

- Ideally equals g , but effects such as velocity saturation

m
can cause gdso to be different than gm

M.H. Perrott 20
 Plot of gm and gds versus Vgs for 0.18 NMOS Device
Transconductances gm and gdo versus Gate Voltage Vgs
4

Id 3.5

Transconductance (milliAmps/Volts)
Vgs 3
M1
ggdso
d0=μnCoxW/L(Vgs-VT)
2.5
W 1.8μ
=
L 0.18μ 2

1.5

gm (simulated in Hspice)
1

0.5

0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Gate Voltage Vgs (Volts)

gm 1
 For Vgs bias voltages around 1.2 V: α = ≈
gdso 2
M.H. Perrott 21
 Plot of gm and gds versus Idens for 0.18 NMOS Device
Transconductances g m and g do versus Current Density
4

Id 3.5

Transconductance (milliAmps/Volts)
Vgs 3
M1
2.5
W 1.8μ
= ggdso
d0=μnCoxW/L(Vgs-VT)
L 0.18μ 2

1.5

gm (simulated in Hspice)
1

0.5

0
0 100 200 300 400 500 600 700
Current Density (microAmps/micron)

M.H. Perrott 22
 Key Noise Sources for Noise Analysis

RD
2 = 4kT R ∆f 2 = 4kT R ∆f
vnD
vnG G 2
D
vnD
2
vnG
RG

vgs Cgs gmvgs gmbvs ro 2

ind
ID RD

Vout
RG
2
vnS
vs 2 = 4kT R ∆f
vnS S
Vin RS
RS

g 2 Kf
 Transistor drain noise: i2nd = 4kT γgdso∆f + m
2
∆f
f W LCox
Thermal noise 1/f noise 23
M.H. Perrott
 Useful References on MOSFET Noise

 B. Wang et. al., “MOSFET Thermal Noise Modeling for

Analog Integrated Circuits”, JSSC, July 1994
 Jung-Suk Goo, “High Frequency Noise in CMOS Low
Noise Amplifiers”, PhD Thesis, Stanford University,
August 2001
- http://www-tcad.stanford.edu/tcad/pubs/theses/goo.pdf
 Jung-Suk Goo et. al., “The Equivalence of van der Ziel
and BSIM4 Models in Modeling the Induced Gate Noise
of MOSFETS”, IEDM 2000, 35.2.1-35.2.4
 Todd Sepke, “Investigation of Noise Sources in Scaled
CMOS Field-Effect Transistors”, MS Thesis, MIT, June
2002
- http://www-mtl.mit.edu/wpmu/sodini/theses/
M.H. Perrott 24
 Input Referral of Noise

Vin K Vout Vin K Vout

2 1 2
vnS 2
vnS
K

 It is often convenient to input refer the impact of noise

when performing noise analysis in circuits
- To justify the above, recall that filtering a random process
x(t) leads to an output random process y(t) such that

Sy (f ) = |H(f )|2 Sx (f )
 For the case where H(f) = K (i.e., a simple gain factor):
2 1
⇒ Sy (f ) = |K| Sx (f ) ⇒ Sx (f ) = 2
Sy (f )
|K|
M.H. Perrott 25
 Example: Common Source Amplifier

Input-refer the
RD noise sources RD
(apply superposition)
2
vnD
Vout Vout

2
ind
Vin Vin 1 2 1 2
i v
gm2 nd ((RD||ro)gm)2 nD

Can directly add the

voltage noise sources
(in power, not voltage) RD
 Note that we will if they are uncorrelated
Vout
always assume that
different circuit
elements produce Vin 1 2 1 2
i v
gm2 nd ((RD||ro)gm)2 nD
uncorrelated noise
M.H. Perrott 26
 Summary
 Power spectral density provides a rigorous approach
to describing the frequency domain behavior of the
ensemble behavior of stationary, ergodic (zero mean)
random processes
- Key concepts: Expectation, Autocorrelation, Fourier
Transform, Correlation, Filtering
 Circuit designers like the following “notation”
- Single-sided rather than double-sided spectra
- Voltage and current noise power denoted as vn2 and i2n
 Key noise properties of circuit elements
- Resistor: thermal noise (white noise)
- MOS transistor: thermal + 1/f noise
 Useful analysis tool: input referral of noise sources
- Assumption of uncorrelated noise from different
elements allows their power (i.e., variance) to be added
M.H. Perrott 27
 Analysis and Design of Analog Integrated Circuits
Lecture 15

Mismatch and Nonlinearity

Michael H. Perrott
March 21, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 A Closer Look at Differential Pairs

Vin+ Vin-
Ibias M1 M2
Vin+
Vin-
M3 M4

Ibias
Vin+ Vin-
M1 M2

M3 M4

 Fabrication of devices comes with variation

- Width, length, and  C mismatch between devices
n ox
- Threshold voltage mismatch between devices
M.H. Perrott 2
 Modeling the Impact of Mismatch in MOS Devices
Vin+ W1 W2 Vin-
L1 L2
M1 M2

L1 L2

Vin+ Vin-
M1 M2
W1 W2

 Compare the drain current of devices in saturation:

- Assume M 1 has current:
μnCox W
ID1 ≈ (Vgs − VT H )2
2 L
- Assume that M µis mismatched
2
¶
to M : 1
μnCox W W
ID2 ≈ +∆ (Vgs−(VT H +∆VT H ))2
2 L L
 Note than nCox mismatch is lumped into (W/L)
M.H. Perrott 3
 Key Impact of Mismatch

Ibias/2+ΔI Ibias/2-ΔI
Vin+ W1 W2 Vin-
L1 L2
M1 M2

Vbias Ibias Vbias

 Ideally, a differential pair will yield identical output

currents assuming identical input voltages for Vin+
and Vin-
 In the case of mismatch, the output currents will NOT
be equal with equal input voltages

M.H. Perrott 4
 Mismatch-Induced Offset Voltage

Ibias/2 Ibias/2
Vin+ W1 W2 Vin-
L1 L2
Vos,in M1 M2

Vbias Ibias Vbias

 Define input offset voltage of the differential pair as

the input voltage difference required to achieve
identical output currents from the differential pair
- Higher mismatch leads to higher offset voltage

M.H. Perrott 5
 Mismatch Modeled as Random Variables
fΔVth(ΔVth) fΔ(W/L)(Δ(W/L))

ΔVth Δ(W/L)
σΔVth σΔ(W/L)

 We often assume a Gaussian PDF for the random

portion of mismatch
- The standard deviation of the PDF is the key metric that
we often use to approximate the impact of mismatch
W
∆VT H ≈ σ∆VT H ∆ ≈ σ∆ W
L L
 Note that there is also a deterministic portion of
mismatch called systematic mismatch
- Systematic mismatch can often be avoided with proper
design and layout techniques
M.H. Perrott 6
 Estimating Mismatch Parameters
fΔVth(ΔVth) fΔ(W/L)(Δ(W/L))

ΔVth Δ(W/L)
σΔVth σΔ(W/L)

 Mathematical and experimental investigation has

revealed
AV T H AK
σ∆VT H ≈ √ σ∆ W ≈ √
WL L WL
-A and AK are proportionality factors that are
VTH
sometimes provided by fabrication reports and
sometimes embedded within “Monte-Carlo” device
models

Key insight: better matching achieved with larger devices

M.H. Perrott 7
 More Information on Mismatch

 Marcel Pelgrom at NXP (formerly Philips) wrote the

seminal papers on this topic
- M.J.M. Pelgrom, A.C.J. Duinmaiger, A.P.G. Welbers,
“Matching Properties of MOS Transistors,” IEEE J.
Solid-State Circuits, vol. SC-24, pp. 1433-1439, Oct. 1989
- M.J.M. Pelgrom, H.P. Tuinhout, M. Vertregt, “Transistor
Matching in Analog CMOS Applications,” IEDM Dig. of
Tech. Papers, pp. 34.1.1-34.1.4, Dec. 1998

M.H. Perrott 8
 Nonlinearities in Amplifiers
 We can generally break up an amplifier into the
cascade of a memoryless nonlinearity and an input
and/or output transfer function
Vdd
Memoryless
RL Nonlinearity Lowpass
Vout Filter
Vin Id -RL Vout
Id 1+sRLCL
Vin CL
M1

 Impact of nonlinearities with sine wave input

- Causes harmonic distortion (i.e., creation of harmonics)
 Impact of nonlinearities with several sine wave inputs
- Causes harmonic distortion for each input AND
intermodulation products
Impact of nonlinearity often assessed based on issues
related to communication system design 9
M.H. Perrott
 Analysis of Amplifier Nonlinearities

 Focus on memoryless nonlinearity block

- The impact of filtering can be added later
Memoryless
Nonlinearity

x y

 Model nonlinearity as a Taylor series expansion up to

its third order term (assumes small signal variation)

- For harmonic distortion, consider

- For intermodulation, consider
M.H. Perrott 10
 Harmonic Distortion

 Substitute x(t) into polynomial expression

Fundamental Harmonics

 Notice that each harmonic term, cos(nwt), has an

amplitude that grows in proportion to An
- Very small for small A, very large for large A
M.H. Perrott 11
 Frequency Domain View of Harmonic Distortion
3c3A3
Afund = c1A +
4
Memoryless
A Nonlinearity

0 w
x y
0 w 2w 3w

 Harmonics cause “noise”

- Their impact depends highly on application
 Low noise amplifiers (LNA) for wireless systems – typically
not of consequence
 Power amplifiers for wireless systems – can degrade
spectral mask
 Audio amp – depends on your listening preference!
 Gain for fundamental component depends on input
amplitude!
M.H. Perrott 12
 1 dB Compression Point
3c3A3
Afund = c1A +
4
Memoryless
A Nonlinearity

0 w
x y
0 w 2w 3w

20log(Afund)
 Definition: input signal level 1 dB
such that the small-signal
gain drops by 1 dB
- Input signal level is high! A1-dB
20log(A)

 Typically calculated from simulation or measurement

rather than analytically
- Analytical model must include many more terms in Taylor
series to be accurate in this context
M.H. Perrott 13
 Harmonic Products with An Input of Two Sine Waves

 DC and fundamental components

 Second and third harmonic terms

 Similar result as having an input with one sine wave

- But, we haven’t yet considered cross terms!
M.H. Perrott 14
 Intermodulation Products

 Second-order intermodulation (IM2) products

 Third-order intermodulation (IM3) products

- These are the troublesome ones for narrowband

wireless systems

M.H. Perrott 15
 Corruption of Narrowband Signals by Interferers
Memoryless
Nonlinearity

X(w) Interferers Desired

Narrowband x y
Signal

W
0 w1 w 2

Corruption of desired signal

Y(w)

W
0 w2-w1 w1 w2 2w1 2w2 3w1 3w2
2w1-w2 2w2-w1 w1+w2 2w1+w2 2w2+w1

 Wireless receivers must select a desired signal that is

accompanied by interferers that are often much larger
- LNA nonlinearity causes the creation of harmonic and
intermodulation products
- Must remove interference and its products to retrieve
desired signal
M.H. Perrott 16
 Use Filtering to Remove Undesired Interference
Memoryless
Nonlinearity

X(w) Interferers Desired

Narrowband x y z
Signal Bandpass
Filter
W
0 w 1 w2

Corruption of desired signal

Y(w)

W
0 w2-w1 w1 w2 2w1 2w2 3w1 3w2
2w1-w2 2w2-w1 w1+w2 2w1+w2 2w2+w1

Corruption of desired signal

Z(w)

W
0 w2-w1 w1 w2 2w1 2w2 3w1 3w2
2w1-w2 2w2-w1 w1+w2 2w1+w2 2w2+w1

 Ineffective for IM3 term that falls in the desired signal

frequency band
M.H. Perrott 17
 Characterization of Intermodulation

 Magnitude of third order products is set by c3 and

input signal amplitude (for small A)

 Magnitude of first order term is set by c1 and A (for

small A)

 Relative impact of intermodulation products can be

calculated once we know A and the ratio of c3 to c1
- Problem: it’s often hard to extract the polynomial
coefficients through direct DC measurements
 Need an indirect way to measure the ratio of c3 to c1
M.H. Perrott 18
 Two Tone Test

 Input the sum of two equal amplitude sine waves into

the amplifier (assume Zin of amplifier = Rs of source)

Equal Amplitude Note: v (w) Amplifier

in
vin(w) Sine Waves vx(w) = Vx Vout
2A 2 Rs

W vin
0 w1 w 2
first-order output
Vbias Zin=Rs
Vout(w) third-order IM term
2 3
Vout=co+c1Vx+c2Vx+c3Vx
W
0 w2-w1 w1 w2 2w1 2w2 3w1 3w2
2w1-w2 2w2-w1 w1+w2 2w1+w2 2w2+w1

 On a spectrum analyzer, measure first order and third

order terms as A is varied (A must remain small)
- First order term will increase linearly
- Third order IM term will increase as the cube of A 19
M.H. Perrott
 Input-Referred Third Order Intercept Point (IIP3)

 Plot the results of the two-tone test over a range of A

(where A remains small) on a log scale (i.e., dB)
- Extrapolate the results to find the intersection of the
first and third order terms
20log(Afund)

1 dB

First-order
output = c1A Third-order 3 c A3
IM term = 4 3
20log(A)
A1-dB Aiip3
- IIP3 defined as the input power at which the
extrapolated lines intersect (higher value is better)
 Note that IIP3 is a small signal parameter based on
extrapolation, in contrast to the 1-dB compression point
M.H. Perrott 20
 Relationship between IIP3, c1 and c3
 Intersection point 20log(Afund)

 Solve for A (gives Aiip3) 1 dB

First-order
output = c1A Third-order 3 c A3
IM term = 4 3
20log(A)
A1-dB Aiip3

 Note that A corresponds to the peak value of the two

cosine waves coming into the amplifier input node (Vx)
- Would like to instead like to express IIP3 in terms of power

M.H. Perrott 21
 IIP3 Expressed in Terms of Power at Source

 IIP3 referenced to Equal Amplitude Note: v (w)

vx(w) =
in
vin(w) Sine Waves
Vx (peak voltage) 2A 2 Amplifier

Rs Vx Vout
W
0 w1 w2
vin
 IIP3 referenced to Vx Vbias Zin=Rs
(rms voltage)
2 3
Vout=co+c1Vx+c2Vx+c3Vx

 Power across Zin = Rs  Note: Power from vin

M.H. Perrott 22
 IIP3 as a Benchmark Specification

 Since IIP3 is a convenient parameter to describe the level

of third order nonlinearity in an amplifier, it is often
quoted as a benchmark spec
 Measurement of IIP3 on a discrete amplifier would be
done using the two-tone method described earlier
- This is rarely done on integrated amplifiers due to poor
access to the key nodes
- Instead, for a radio receiver for instance, one would simply
put in interferers and see how the receiver does
 Note: performance in the presence of interferers is not just a
function of the amplifier nonlinearity
 Calculation of IIP3 is most easily done using a Spice
simulator
- Two-tone method is not necessary – simply curve fit to a
third order polynomial

M.H. Perrott 23
 Impact of Differential Amplifiers on Nonlinearity

I1 I2 Memoryless
Nonlinearity
vid -vid
M1 M2
2 2 vid Idiff = I2-I1
vx
2Ibias

 Assume vx is approximately incremental ground

 Second order term removed and IIP3 improved!

M.H. Perrott 24
 Summary

 Mismatch between devices in differential pair circuits

induces an effective offset voltage
- The value of the offset voltage is reduced by having large
device dimensions
- Fabrication reports or “Monte-Carlo” models provide the
best approach to assessing the impact of mismatch
 May not be available, which leads to guessing the impact
 Nonlinearity is typically modeled as a third order
polynomial
- Results in harmonic distortion and intermodulation
- Third order component is often focused on in classical
communication systems
- Second order component is important for modern
communication systems based on “direct conversion”
- Differential pair offers some linearity advantages over
single ended amplifiers 25
M.H. Perrott
 Analysis and Design of Analog Integrated Circuits
Lecture 16

Subthreshold Operation and gm/Id Design

Michael H. Perrott
April 1, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 A Closer Look at Transconductance
Id Vds > ΔV
d
Id
g
M1
ΔId
Vgs s Id_op gm =
ΔVgs
Vgs_op
Vgs
NMOS VTH Vgs_op

ΔV
 Assuming device is in strong inversion and in saturation:
μnCox W
ID = (Vgs − VT H )2(1 + λVds)
2 L s
δId W W
⇒ gm = ≈ μnCox (Vgs −VT H ) ≈ 2μnCox Id
δVgs L L
q
Id 2μnCox W/L 2Id
⇒ gm ≈ √ ≈
Id (Vgs − VT H )
M.H. Perrott 2
 Unity Gain Frequency for Current Gain, ft

|Id/Iin|
d
Id
g
M1
Iin s Vds
0dB f
NMOS ft

 Under fairly general conditions, we calculate:

 ft is a key parameter for characterizing the achievable

gain·bandwidth product with circuits that use the device
M.H. Perrott 3
 Current Density as a Key Parameter

Id W

Id
W
L
M1 Id
W

 Current density is defined as the ratio Id/W:

- We’ll assume that current density is altered by keeping
Id fixed such that only W varies
 Maintains constant power
 ro (i.e., 1/gds = 1/(Id)) will remain somewhat constant

M.H. Perrott 4
 Investigating Impact of Current Density

 For simplicity, let us assume that the CMOS device

follows the square law relationship
μnCox W
ID ≈ (Vgs − VT H )2
2 L
- This will lead to the formulations:
s µ ¶
2L Id 2Id
Vgs − VT H ≈ gm ≈
μnCox W Vgs − VT H

- These formulations are only accurate over a narrow

region of strong inversion (with the device in saturation)
- However, the general trends observed from the above
expressions as a function of current density will provide
useful insight

M.H. Perrott 5
 Investigate the Impact of Increasing Current Density
−6 Gate Overdrive versus Current Density
x 10
1.5
Vgs−Vth (Volts)

1
s µ ¶
Gate overdrive increases
0.5 2L Id
Vgs − VT H ≈
0
−7 −6 −5 −4 −3
μnCox W
10 10 10 10 10
−3 Transconductance versus Current Density
x 10
8

6
gm (1/Ohms)

4 gm decreases 2Id
2 gm ≈
Vgs − VT H
0
−7 −6 −5 −4 −3
10 10 10 10 10
11 ft versus Current Density
x 10
4

3
√
ft (Hz)

2
ft increases 1 gm W
1 ft = ∝
0
2π Cgs W
−7 −6 −5 −4 −3
10 10 10 10 10
Current Density Id/W (Amps/micron)

W decreased with fixed Id

M.H. Perrott 6
 Transconductance Efficiency Versus ft
−6 Gate Overdrive versus Current Density
x 10
1.5
Vgs−Vth (Volts)

1
s µ ¶
Gate overdrive increases
0.5 2L Id
Vgs − VT H ≈
0
−7 −6 −5 −4 −3
μnCox W
10 10 10 10 10
−3 Transconductance versus Current Density
x 10
8

6
gm (1/Ohms)

4 gm decreases 2Id
2 gm ≈
Vgs − VT H
0
−7 −6 −5 −4 −3
10 10 10 10 10
11 ft versus Current Density
x 10
4

3
√
ft (Hz)

2
ft increases 1 gm W
1 ft = ∝
0
2π Cgs W
−7 −6 −5 −4 −3
10 10 10 10 10
Current Density Id/W (Amps/micron)

Higher gm (more gain) Higher ft (faster speed)

M.H. Perrott 7
 Transistor “Inversion” Operating Regions
−6 Gate Overdrive versus Current Density
x 10
1.5
Vgs−Vth (Volts)

1
s µ ¶
Gate overdrive increases
0.5 2L Id
Vgs − VT H ≈
0
−7 −6 −5 −4 −3
μnCox W
10 10 10 10 10
−3 Transconductance versus Current Density
x 10
8

6
gm (1/Ohms)

4 gm decreases 2Id
2 gm ≈
Vgs − VT H
0
−7 −6 −5 −4 −3
10 10 10 10 10
11 ft versus Current Density
x 10
4

3
√
ft (Hz)

2
ft increases 1 gm W
1 ft = ∝
0
2π Cgs W
−7 −6 −5 −4 −3
10 10 10 10 10
Current Density Id/W (Amps/micron)

Weak Moderate Strong

M.H. Perrott 8
 Key Insights Related to Current Density

 Current density sets the device operating mode

- Weak inversion (subthreshold): highest g efficiency
m
 Achieves highest g for a given amount of current, I
m d
- Strong inversion: highest f t
 Achieves highest speed for a given amount of current, I d
- Moderate inversion: compromise between the two
 Often the best choice for circuits that do not demand the
highest speed but cannot afford the low speed of weak
inversion (subthreshold operation)
 Key issue: validity of square law current assumption
μnCox W
ID = (Vgs − VT H )2(1 + λVds)
2 L
- The above is only accurate over a narrow range of strong
inversion (i.e., the previous plots are inaccurate)
 General observations above are still true, though
M.H. Perrott 9
 A Proper Model for Subthreshold Operation
ID

VGS<VTH
G
VDS
S D

 Drain current:
W Vgs/(nVt) ³ −Vds/Vt
´
ID = ID0 e 1−e
L
- Where: Vt =
kT
≈ 26mV at T = 300K
q
Cox + Cdepl
n= ≈ 1.5
Cox
ID0 = μnCox (n − 1)Vt2e−VT H /(nVt)
- Note: channel length modulation, i.e., , is ignored here
M.H. Perrott 10
 Saturation Region for Subthreshold Operation
Drain current Versus Vds and Vgs
140
Vgs = 0.44V
120

100

80 Vgs = 0.42V
I (nA)
d

60
Vgs = 0.4V
40

20

0
0 0.1 0.2 0.3 0.4 0.5
Vds (Volts)

 Saturation occurs at roughly Vds > 100 mV

W Vgs/(nVt ) ³ −Vds/Vt
´ W Vgs/(nVt)
⇒ ID = ID0 e 1−e ≈ ID0 e
L L 11
M.H. Perrott
 Transconductance in Subthreshold Region

Id Vds > 100mV

d
Id
g
M1
ΔId
Vgs s Id_op gm =
ΔVgs
Vgs_op
Vgs
Vgs_op
NMOS
 Assuming device is in subthreshold and in saturation:
W Vgs/(nVt) gm purely a
ID ≈ ID0 e
L function of Id!
δId W Vgs/(nVt) 1 Id
⇒ gm = ≈ ID0 e =
δVgs L nVt nVt

2Id
Recall for strong inversion : gm ≈
(Vgs − VT H )
M.H. Perrott 12
 Comparison of Strong and Weak Inversion for gm

 Assumption: Id is constant with only W varying

 Strong inversion formulation predicts ever increasing
gm with reduced overdrive voltage
2Id
gm ≈
(Vgs − VT H )
- Reduced current density leads to reduced overdrive
voltage and therefore higher gm
 Weak inversion formulation predicts that gm will hit a
maximum value as current density is reduced
Id
gm =≈
nVt
- Note that the area of the device no longer influences g m
when operating in weak inversion (i.e., subthreshold)

M.H. Perrott 13
 Hybrid- Model in Subthreshold Region (In Saturation)
d
g

d
g
vgs Cgs gmvgs gmbvs ro
s

 Looks the same in form as for strong inversion, but

different expressions for the various parameters
µ ¶ µ ¶
1 Id n − 1 Id 1
gm ≈ gmb ≈ ro ≈
n Vt n Vt λId

- We can use the very same Thevenin modeling

approach as in strong inversion
 We just need to calculate gm and gmb differently
M.H. Perrott 14
 Noise for Subthreshold Operation (In Saturation)
d
g

d
g
vgs Cgs gmvgs gmbvs ro 2
ind
s

 Recall transistor drain noise in strong inversion:

K g 2
f m
i2
nd = 4kT γg dso ∆f + 2
∆f
f W LCox
Thermal noise 1/f noise
 In weak inversion (i.e., subthreshold):
Kf gm 2
2
ind = 2kT ngm∆f + ∆f
f W LCox2

Thermal noise 1/f noise

M.H. Perrott 15
 Strong Inversion Versus Weak Inversion

 Strong inversion (Vgs > VTH)

- Poor g efficiency (i.e., g /I is low) but fast speed
m m d
- Need V > (V – V ) = V to be in saturation
ds gs TH
- Key device parameters are calculated as:
2Id γgm 1
gm ≈ gmb ≈ q ro ≈
(Vgs − VT H ) 2 2|ΦF | + VSB λId
 Weak inversion (Vgs < VTH)
- Good g efficiency (i.e., g /I is high) but slow speed
m m d
- Need V > 100mV to be in saturation
ds
- Key device
µ ¶
parameters are calculated as:
µ ¶
1 Id n − 1 Id 1
gm ≈ gmb ≈ ro ≈
n Vt n Vt λId
 Moderate inversion: compromise between the two
Thevenin Modeling Techniques Can Be Applied to All Cases
M.H. Perrott 16
 gm/Id Design

 gm/Id design is completely SPICE based

- Hand calculations of g , r , etc. are not performed
m o
 Various transistor parameters are plotted in terms of
gm/Id
- Low g /I corresponds to strong inversion
m d
- High g /I corresponds to weak inversion
m d
 Once a given value of gm/Id is chosen, it constrains
the relationship between W, L, ft, etc. such that the
sizing of devices becomes a straightforward exercise

M.H. Perrott 17
 Useful References Related to gm/Id Design

 Prof. Bernhard Boser’s Lecture:

- B. E. Boser, "Analog Circuit Design with Submicron
Transistors," IEEE SSCS Meeting, Santa Clara Valley, May
19, 2005,
http://www.ewh.ieee.org/r6/scv/ssc/May1905.htm
 Prof. Boris Murmann’s Course Notes:
- https://ccnet.stanford.edu/cgi-
bin/course.cgi?cc=ee214&action=handout_view&V_sect
ion=general
 See Slides 45 to 67 in particular
 Prof. Reid Harrison’s paper on a low noise instrument
amplifier:
- http://www.ece.utah.edu/~harrison/JSSC_Jun_03.pdf

M.H. Perrott 18
 Summary

 CMOS devices in saturation can be utilized in weak,

moderate, or strong inversion
- Each region of operation involves different expressions
for drain current as a function of V and V
gs ds
- It is best to use SPICE to calculate parameters such as
gm, gmb, ro due to the complexity of the device model in
encompassing these three operating regions
 gm/Id methodology is one such approach
- Weak inversion offers large gm/Id but slow speed, and
strong inversion offers fast speed but lower gm/Id
- Moderate inversion offers the best compromise between
achieving reasonable gm/Id and reasonable speed
 Thevenin modeling approach is valid for all operating
regions once gm, gmb, and ro are known

M.H. Perrott 19
 Analysis and Design of Analog Integrated Circuits
Lecture 17

Basic Two Stage CMOS Opamp

Michael H. Perrott
April 4, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Opamps Are Basic Analog Building Blocks
Analog Filters Current References Switched Capacitor Circuits
C1 C2
Iref
R1
Vin Vref Vin
Vout Vout
Vref C1 Vref

Rref

 Enable active filters

- Can achieve arbitrary pole/zero placement using only
capacitor/resistor networks around the opamp
 Allow accurate voltage to current translation
 Provide accurate charge transfer between capacitors
- Extremely useful for switched capacitor circuits used in
analog-to-digital converters and discrete-time analog
filters
M.H. Perrott 2
 Key Specifications of Opamps (Open Loop)
Rhuge
For Open Loop Characterization
Chuge Vdd
Set Rhuge >> |Zout|
Vout
and 1/(RhugeChuge) << wdom
Vss CL
Vin Zout
20log(K)

Vdd 20log Vout/Vin

Vout 0dB
Vss CL
Vin w (rad/s)
wdom w0 wp

 DC small signal gain: K

 Unity gain frequency: w0
 Dominant pole frequency: wdom
 Parasitic pole frequencies: wp (and higher order poles)
 Output swing (max output range for DC gain > Kmin) 3
M.H. Perrott
 Key Specifications of Opamps (Closed Loop)

Vdd
Voffset Vout

Vss CL
Vin

 Offset voltage
 Settling time (closed loop bandwidth)
 Input common mode range
 Equivalent Input-Referred Noise
 Common-Mode Rejection Ratio (CMRR)
à !−1
δVoffset
CMRR =
δVin
 Power Supply Rejection Ratio (PSRR)
à !−1 à !−1
+ δVoffset − δVoffset
PSRR = PSRR =
δVdd δVss
M.H. Perrott 4
 Slew Rate Issues for Opamps

Vdd Vin

Vout
ideal
Vss CL
Vin Vout
slew-rate limited

 Output currents of practical opamps have max limits

- Impacts maximum rate of charging or discharging load
capacitance, C L
- For large step response, this leads to the output lagging
behind the ideal response based on linear modeling
 We refer to this condition as being slew-rate limited
 Where slew-rate is of concern, the output stage of the
opamp can be designed to help mitigate this issue
- Will lead to extra complexity and perhaps other issues
M.H. Perrott 5
 Basic Two Stage CMOS Op Amp

M8 M7
M5

Iref Vin- Vin+ Vout

M1 M2
CL

Rc Cc

M3 M4 M6

 This is a common “workhorse” opamp for medium

performance applications
 Provides a nice starting point to discuss various
CMOS opamp design issues
 Starting assumptions: W1/L1 = W2/L2, W3/L3 = W4/L4

M.H. Perrott 6
 First Stage Analysis

M5 Ibias1
First Stage Two-Port Model
-vid/2 vid/2
M1 M2
Rout1 vid V1 Zin Gm1V1 Rout1 Zin2 vout1

vout1

M3 M4

 Derive two port model assuming differential input:

1 1
Zin1 = =
s(Cgs1/2) s(Cgs2/2)
Gm1 = gm1 = gm2

Rout1 = ro2 ||ro4

M.H. Perrott 7
 Derivation of Rout1 (Incorrect Approach)

ro5

-vid/2 vid/2
M1 M2

ro2 (1+gm2 1 ) 2ro2

gm1
ro4
1
gm3 M4

 Application of Thevenin analysis seems to imply that

Rout1 = 2ro2||ro4

- Why is this incorrect?

M.H. Perrott 8
 Derivation of Rout1 (Correct Approach)

ro5

i1
M1 M2
vtest itest = i1 + i2
i 1= 2ro2
i1 2ro2
i2 ro4
vtest
1
gm3 M4

vtest
i2 i1 + r
o4

 Correct approach includes the impact of the current

mirror feedback
vtest vtest vtest
itest = i1 + i2 = i1 + i1 + =2 +
ro4 2ro2 ro4
⇒ Rout1 = ro2||ro4
M.H. Perrott 9
 Derivation of Gm1
incremental ground

-vid/2 vid/2
M1 M2
i1 i2 iout = i1 + i2

i1
1
gm3 M4

 For differential input, we can approximate the source

of M1 and M2 as being at incremental ground
gm1
i1 = −gm1(−vid /2) = vid
2
gm2 gm1
i2 = gm2(vid/2) = vid = vid
2 2
⇒ iout = gm1vid ⇒ Gm1 = gm1 = gm2
M.H. Perrott 10
 Derivation of Zin
incremental ground
Cgs1 Cgs2

-vid/2 M1 M2 vid/2 -vid/2 vid/2

Cgs1 Cgs2

-vid/2 vid/2
1
gm3 M4 Cgs1 Cgs2

 For differential input, we can -vid/2 vid/2

simplify the input capacitance Cgs1/2
calculation through the steps
shown at the right
vid
1 1 Cgs1/2
⇒ Zin1 = =
sCgs1/2 sCgs2/2
M.H. Perrott 11
 Second Stage Analysis

M7
Second Stage Two-Port Model
Ibias2

Vout
vin2 V2 Zin2 Gm2V2 Rout2 CL vout
CL

Vin2
M6

 Two port model derivation is straightforward

- This is a common source amplifier
1
Zin2 =
sCgs6
Gm2 = gm6
Rout2 = ro6 ||ro7
M.H. Perrott 12
 Overall Opamp Model
First Stage Two-Port Model Second Stage Two-Port Model

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

 Overall transfer function

vout (s) K
H(s) = =
vid(s) (1 + s/wp1)(1 + s/wp2)
- DC gain
K = gm1(ro2||ro4 )gm6(ro6||ro7 )
- Poles
1 1
wp1 = wp2 =
(ro2||ro4 )Cgs6 (ro6||ro7 )CL
 In general, wp2 << wp1 since CL >> Cgs6
M.H. Perrott 13
 Consider The Dominant Pole To Be wp2

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB

w (rad/s)
1 w0
wp2 =
(ro6||ro7)CL

K gm1(ro2||ro4 )gm6(ro6||ro7 )
H(s) = =
1 + s/wp2 1 + s(ro6||ro7 )CL
 At frequencies >> wp2
gm1(ro2||ro4 )gm6 gm1(ro2||ro4 )gm6
H(s) ≈ ⇒ wo ≈
sCL CL

We want wp1 > w0 for good phase margin with unity gain feedback
M.H. Perrott 14
 Key Issue for Achieving Adequate Phase Margin

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB

w (rad/s)
1 w0 1
wp2 = wp1 =
(ro6||ro7)CL (ro2||ro4)Cgs6

gm1(ro2||ro4 )gm6
wo ≈
CL
 To achieve wp1 > w0
1
wp1 = > wo ⇒ CL > gm1gm6(ro2 ||ro4 )2Cgs6
(ro2||ro4 )Cgs6
- We need a very large value of C relative to Cgs6
L
 This will generally be impractical!
M.H. Perrott 15
 Pole Splitting Using a Compensation Capacitor
CM Cc

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

 Consider placing capacitor Cc across the second stage

- Load capacitance seen by stage 1 becomes roughly
CM = (1 + gm6(ro6||ro7 ))Cc ≈ gm6(ro6||ro7 )Cc

 This large Miller capacitance now causes wp1 to become

dramatically lower such that it forms the dominant pole
1 1
wp1 ≈ ≈
(ro2 ||ro4 )CM (ro2||ro4 )gm6(ro6||ro7 )Cc
 We will see that wp2 actually increases in frequency!
M.H. Perrott 16
 Pole Splitting Using a Compensation Capacitor (Part 2)
CM Cc Rth_C
L

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

 Assuming wp1 forms the dominant pole, we can

approximate Cc as a short when calculating wp2
1
Rth CL ≈
gm6
1 gm6
⇒ wp2 ≈ =
(1/gm6)(Cgs6 + CL) Cgs6 + CL
- Note: we must have C c >> Cgs6 for this to be accurate
 The inclusion of capacitor Cc has led to wp2
increasing in frequency
M.H. Perrott 17
 Impact of Pole Splitting using Compensation Cap

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

w (rad/s)

1 gm6
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6+CL
1 1
wp2 = wp1 =
(ro6||ro7)CL (ro2||ro4)Cgs6

 Pole splitting allows the dominant pole frequency to

be dramatically decreased and the main parasitic pole
to be dramatically increased
- We can achieve higher unity gain frequency with
improved phase margin and with reasonable area
M.H. Perrott 18
 Unity Gain Frequency with Compensation Cap

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB
w (rad/s)
1 w0 gm6
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6+CL

K gm1(ro2 ||ro4 )gm6(ro6 ||ro7 )

H(s) = =
1 + s/wp1 1 + s(ro2||ro4)gm6(ro6||ro7 )Cc
 At frequencies >> wp1
gm1(ro2||ro4 )gm6(ro6||ro7 ) gm1
H(s) ≈ ⇒ wo ≈
s(ro2 ||ro4)gm6(ro6||ro7 )Cc Cc

We want wp2 > w0 for good phase margin with unity gain feedback
M.H. Perrott 19
 Key Constraints for Achieving Adequate Phase Margin

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB
w (rad/s)
1 w0 gm6
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6+CL

gm1
wo ≈
Cc
 To achieve wp2 > w0
gm6 gm1
wp2 = > wo ⇒ Cc > (Cgs6 + CL)
Cgs6 + CL gm6
- Note: we must have C c >> Cgs6 for this to be accurate
M.H. Perrott 20
 More Accurate Calculations Related to Phase Margin

20log(gm1(ro2||ro4)gm6(ro6||ro7))

20log Vout/Vid

0dB
w (rad/s)
1 w0 gm6Cc
wp1 = wp2 =
(ro2||ro4)gm6(ro6||ro7)Cc Cgs6CL+Cc(Cgs6+CL)

gm1
wo ≈
Cc
 To achieve wp2 > w0
à !
gm1 Cgs6CL
wp2 > wo ⇒ Cc > + Cgs6 + CL
gm6 Cc

M.H. Perrott 21
 A More Accurate Transfer Function Model
Cc

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

vout (s) K(1 + s/wz )

H(s) = =
vid(s) (1 + s/wp1)(1 + s/wp2)
K = gm1(ro2||ro4 )gm6(ro6||ro7 )
1
wp1 =
(ro2||ro4 )gm6(ro6||ro7 )Cc
gm6Cc
wp2 =
Cgs6CL + Cc(Cgs6 + CL)
µ ¶
wz = −
gm6  Right half plane (RHP) zero
Cc causes potential stability issues 22
M.H. Perrott
 Plotting the Magnitude of a RHP Zero

 Plot the magnitude response of right half plane wz

20 log |Az (w)| = 20 log |1 − jw/wz |

- For w << |w |: z 20 log |Az (w)| ≈ 20 log |1| = 0

- For w >> |w |: z 20 log |Az (w)| ≈ 20 log |w/wz |

20log|Az(ω)|

20 dB/decade

0 dB ω
ωz

Magnitude response is the same as for left half plane zero

M.H. Perrott 23
 Plotting the Phase of a RHP Zero

 Plot the phase response of right half plane wz

6 Az (w) = 6 (1 − jw/wz ) = arctan (−w/wz )

- For w << |w |: z
6 Az (w) ≈ arctan (0) = 0◦

- For w = |w |:z
6 Az (w) ≈ arctan (−1) = −45◦

- For w >> |w |: z
6 Az (w) ≈ arctan (−∞) = −90◦
ωz/10 ωz ωz∗10
0o ω

Az(ω) -45o

o
-90

Phase response is negative rather than positive (similar to pole)

M.H. Perrott 24
 Phase Margin Degradation Due to RHP Zero

20log Vout/Vid

0dB
w (rad/s)
gm1 gm6
w0 = |wz| =
Cc Cc
gm6
wp2 =
Cgs6+CL
 Since the RHP zero adds negative phase (similar to
pole), it reduces phase margin
- We want: |wz | À wo ⇒ gm6 À gm1
 This is not a desirable constraint
M.H. Perrott 25
 Adding a Compensation Resistor
Rc Cc

Cgs1
vid V1 gm1V1 ro2||ro4 V2 Cgs6 gm6V2 ro6||ro7 vout CL
2

vout (s) K(1 + s/wz )

H(s) = =
vid(s) (1 + s/wp1)(1 + s/wp2)
K = gm1(ro2||ro4 )gm6(ro6||ro7 )
 RHP zero effectively
1
wp1 = removed if Rc = 1/gm6
(ro2||ro4 )gm6(ro6||ro7 )Cc
 Improved phase
gm6Cc margin possible with
wp2 =
Cgs6CL + Cc(Cgs6 + CL) Rc > 1/gm6

wz = −
gm6
µ
1
¶
- See Johns&Martin,
Cc 1 − gm6Rc pp. 242-244
M.H. Perrott 26
 Implementing Rc with a Triode Device

M8 M7
M5

Iref Vin- Vin+ Vout

M1 M2
CL
M9
Cc

M3 M4 M6

 More compact implementation than a poly resistor

 Triode channel resistance can somewhat track 1/gm6
across process and temperature variations
 Key issue: supply sensitivity
- See pp. 246-248 of Johns&Martin for solutions to this issue
M.H. Perrott 27
 Calculations for Triode Compensation Resistor
Vdd

M9
Cc

M4 M6

 Triode resistance calculated as

1
Rc =
μnCox(W9/L9)(Vgs9 − VT H )
1
=
μn Cox(W9/L9)(Vdd − Vgs6 − VT H )
 Assuming square law, 1/gm6 is calculated as
1 1
=
gm6 μnCox(W6/L6)(Vgs6 − VT H )

Depending on Vdd, Rc can track 1/gm6 across process/temp

M.H. Perrott 28
 Summary

 Basic two-stage CMOS opamp is a workhorse for many

moderate performance analog applications
- Relatively simple structure with reasonable performance
 Key issue: two-stages lead to two poles that are
relatively close to each other
- This leads to very poor phase margin unless very large
CL is used
 Inclusion of a compensation capacitor across the
second stage leads to pole splitting such that stable
performance can be achieved with reasonable area
- A compensation resistor is also desirable to help
eliminate the impact of a RHP zero that occurs due to
compensation

We will use the basic two stage CMOS opamp structure

to explore various opamp specifications in the next lecture
M.H. Perrott 29
 Analysis and Design of Analog Integrated Circuits
Lecture 18

Key Opamp Specifications

Michael H. Perrott
April 8, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Recall: Key Specifications of Opamps (Open Loop)
Rhuge
For Open Loop Characterization
Chuge Vdd
Set Rhuge >> |Zout|
Vout
and 1/(RhugeChuge) << wdom
Vss CL
Vin Zout
20log(K)

Vdd 20log Vout/Vin

Vout 0dB
Vss CL
Vin w (rad/s)
wdom w0 wp

 DC small signal gain: K

 Unity gain frequency: w0
 Dominant pole frequency: wdom
 Parasitic pole frequencies: wp (and higher order poles)
 Output swing (max output range for DC gain > Kmin) 2
M.H. Perrott
 Recall: Key Specifications of Opamps (Closed Loop)

Vdd
Voffset Vout

Vss CL
Vin

 Offset voltage
 Settling time (closed loop bandwidth)
 Input common mode range
 Equivalent Input-Referred Noise
 Common-Mode Rejection Ratio (CMRR)
à !−1
δVoffset
CMRR =
δVin
 Power Supply Rejection Ratio (PSRR)
à !−1 à !−1
+ δVoffset − δVoffset
PSRR = PSRR =
δVdd δVss
M.H. Perrott 3
 Basic Two Stage CMOS Op Amp

M8 M7
M5

Iref Vin- Vin+ Vout

M1 M2
CL

Rc Cc

M3 M4 M6

 This is a common “workhorse” opamp for medium

performance applications
 Provides a nice starting point to discuss various
CMOS opamp design issues
 Starting assumptions: W1/L1 = W2/L2, W3/L3 = W4/L4

M.H. Perrott 4
 Key Specifications Discussed In This Lecture

 Systematic offset voltage

 CMRR
 PSRR+ and PSRR-
 Input-referred voltage noise
 Slew rate

M.H. Perrott 5
 A Closer Look at Offset Voltage
Vdd
Vin- ³ ´
Vout Vout = H(s) Vin+ − Vin− − Voff
Vin+
Vss CL
Voff

 Assume:
Vin- Vdd - Input to opamp is a DC signal
Voff Vin+ Vout - Amplifier is not saturated
Voff CL - DC gain of amplifier is large
Vin ³ ´
Vout = K Vin+ − Vin− − Voff

⇒ Vin+ − Vin− = Voff + Vout /K ≈ Voff

Two sources of offset: systematic and random

M.H. Perrott 6
 Systematic Offset: First Stage Analysis

M8 M7
M5 Ibias1

Iref Vin- Vin+ Vout

M1 M2

Ibias1 Ibias1 CL
2 2 Rc Cc

Vgs3 M6
M3 M4

 For zero systematic offset we want Vout to be at

roughly mid-rail assuming Vin+ = Vin-
- V = V leads to equal currents in M /M
in+ in- 3 4
- Equal currents and equal V for M /M leads to: gs 3 4

Vds4 = Vds3 = Vgs3

M.H. Perrott 7
 Key Constraints To Achieve Zero Systematic Offset

M8 M7
M5 Ibias1 Ibias2

Iref Vin- Vin+ Vout

M1 M2

Ibias1 Ibias1 CL
2 2 Rc Cc Id6

assume L6 = L3 = L4 Vgs3 M6
M3 M4

 For mid-rail Vout, we need Id6 = Ibias2

1 W6 ³ ´2
⇒ Id6 = μnCox Vgs3 − VT H = Ibias2
2 L6
1 W3 ³ ´2 Ibias1 W6 Ibias2 W7
Also: μn Cox Vgs3 − VT H = ⇒ = =
2 L3 2 2W3 Ibias1 W5
M.H. Perrott 8
 Key Common-Mode Rejection (CMRR) Observations

M8 M7
M5 Ibias1

Iref Vin- Vin+ Vout

M1 M2
CL

Rc Cc

M6
M3 M4
 CMRR defined as avd/avc, where
avd = avd1avd2 avc = avc1avd2
 Inspection of the above reveals that CMRR is
determined by the first stage
avd1avd2 avd1
CMRR = = = CMRR 1
avc1avd2 avc1
M.H. Perrott 9
 Common Mode Gain and Resulting CMRR

ro5 2ro5 2ro5 2ro5 2ro5

Vin- Vin+ vic vic vic vic

M1 M2 M1 M2 M1 M2

V2 V2 V2

1 1 1 1
gm3 M4 gm3 M4 gm3 gm4

 Differential gain was derived in Lecture 17

avd1 = gm1 (ro2||ro4 )
 Common-mode gain is calculated from the above as
1/gm4 1
avc1 = ≈
1/gm2 + 2ro5 2gm4ro5
avd1
⇒ CMRR = = 2gm1(ro2||ro4 )gm4ro5
avc1 10
M.H. Perrott
 Characterizing CMRR with Changes in Offset Voltage

Vdd
Voffset Vout

Vss CL
Vin

 Consider Vin as a common-mode signal which has an

open loop impact on Vout as
∆Vout = avc∆Vin
 However, the closed loop configuration above tries to
keep Vin+ = Vin- subject to finite differential gain avd
Vout = avd(Vin − Vout ) = avdVoffset
1 avc
⇒ ∆Voffset = ∆Vout = ∆Vin
avd avd
∆Voffset avc
⇒ = = (CMRR )−1
∆Vin avd 11
M.H. Perrott
 Power Supply Rejection Ratio (PSRR)

M8 M7
M5 Ibias1

Iref Vic Vic Vout

M1 M2
CL

Rc Cc

M6
M3 M4
 We now consider the impact of positive and negative
supply variation on the output of the amplifier
- Key assumption: V in+ = Vin- = Vic
 Definitions:
+ avd − avd
PSRR = + PSRR = −
a a
M.H. Perrott 12
 Simplification of Current Mirror

1 M7
gm8
M5 Ibias1

Vic Vic Vout

M1 M2
CL

Rc Cc

M6
M3 M4

 Replace current reference and diode connected

device M8 with their small signal models
- We see that positive and negative supply variations
have no impact on Vgs of M5 and M7
 We can ignore M8 and current reference in our PSRR
analysis
M.H. Perrott 13
 Further Simplifications for PSRR Calculations

M7 2ro5 2ro5 ro7

M5 Ibias1

Vic Vic Vout Vic Vic Vout

M1 M2 M1 M2
CL CL

Rc Cc Rc Cc
1 1
M6 gm3 gm4 M6
M 3 M4

 Observe that positive and negative supply variations

have equal impact on both sides of the differential pair
- We can use common-mode analysis for the first stage

M.H. Perrott 14
 Calculation of PSRR+ At Low Frequencies

2ro5 ro7
vs+

Vic Vout
M2
CL
V2 Rc Cc
1
gm4 M6

 Calculation of impact of Vs+ on Vout à !

ro6 1
Vout = Vs+ + gm6(ro6||ro7 ) Vs+
ro6 + ro7 2gm4ro5
Vout
⇒ a+ = ≈1
Vs+
+ avd
⇒ PSRR = ≈ avd = gm1(ro2||ro4 )gm6(ro6||ro7 )
av+ 15
M.H. Perrott
 Calculation of PSRR- At Low Frequencies

2ro5 ro7

Vic Vout
M2
CL
V2 Rc Cc
vs- 1
gm4 M6

 Calculation of impact of Vs- on Vout

à !
ro7 1
Vout ≈ Vs− + gm6(ro6||ro7 ) Vs−
ro6 + ro7 gm4(gm2ro2)2ro5
Vout
⇒ a− = ≈1
Vs−
− avd
⇒ PSRR = ≈ avd = gm1(ro2||ro4 )gm6(ro6||ro7 )
av− 16
M.H. Perrott
 Characterizing PSRR with Changes in Offset Voltage

Vdd
Voffset Vout

Vss CL
Vin

 Consider Vdd as a common-mode signal which has an

open loop impact on Vout as
∆Vout = a+∆Vdd
 However, the closed loop configuration above tries to
keep Vin+ = Vin- subject to finite differential gain avd
Vout = avd(Vin − Vout ) = avdVoffset
1 a+
⇒ ∆Voffset = ∆Vout = ∆Vdd
avd avd
∆Voffset a+ ³ ´−1
⇒ = = PSRR +
(Similar for PSRR-)
∆Vdd avd 17
M.H. Perrott
 Noise Analysis for a Two Stage Opamp

vid vout vin vout

avd1 avd2 avd1avd2

2 2 1 2 1 2
vn1 vn2 vn1 + vn2
avd12 (avd1avd2)
2

 Each opamp stage will contribute noise

- Typically the spectral density of the noise will be of the
same order at each stage
 Input referral of the noise reveals that the second
stage noise will have much less impact than the first
stage noise
- Input-referred noise calculations of an opamp need only
focus on the first stage

M.H. Perrott 18
 Input-Referral of MOS Device Noise

2
ind
Vin Vin 1 2
i
gm2 nd

 Transistor drain current noise: Note:

γ K g 2 gm
f m
i2
nd = 4kT gm ∆f + 2
∆f gds0 =
α f W LCox α
Thermal noise 1/f noise
 Input-referred voltage noise:
2 γ 1 Kf 1
vni = 4kT ∆f + 2
∆f
α gm f W LCox
Thermal noise 1/f noise

Impact of thermal versus 1/f noise depends on gm

M.H. Perrott 19
 Analysis of Op Amp Output Noise (First Stage)
2
vni5
Note that impact of M5 noise is minor since
M5 it corresponds to common-mode noise

2 2
vni1 vni2
M1 M2

isc2
2
vni3 2
vni4
Assume:
gm1 = gm2
M3 M4 gm3 = gm4

µ ¶ µ ¶
i2
sc = g 2
m1 v 2
ni1 + v 2
ni2 + g 2
m3 v 2
ni3 + v 2
ni4

⇒ i2
sc = 2g 2 v 2 + 2g 2 v 2
m1 ni1 m3 ni3

M.H. Perrott 20
 Determining Input-Referred Noise

M5
Output noise due to equivalent
input-referred noise:
2
vneq
M1 M2
i2
sc = g 2 v2
m1 neq
isc2
Assume:
M3 M4
gm1 = gm2
gm3 = gm4

 Output noise due to individual devices (Slide 20):

i2
sc = 2g 2 v 2 + 2g 2 v 2 = g 2 v 2
m1 ni1 m3 ni3 m1 neq
à !2
2 = 2v 2 + 2 gm3 2 Want gm1 > gm3
vneq ni1 vni3 for low noise
gm1
M.H. Perrott 21
 Characterizing Input-Referred Noise

Vdd
Voffset Vout

Vss CL
Vin

 Placing the amplifier within unity gain feedback

configuration causes the overall output noise of the
amplifier to become referred to the input
- We can now examine the low frequency content of the
input-referred noise by simply probing the noise of Vout

M.H. Perrott 22
 Recall: Slew Rate Issues for Opamps

Vdd Vin

Vout
ideal
Vss CL
Vin Vout
slew-rate limited

 Output currents of practical opamps have max limits

- Impacts maximum rate of charging or discharging load
capacitance, C L
- For large step response, this leads to the output lagging
behind the ideal response based on linear modeling
 We refer to this condition as being slew-rate limited
 Where slew-rate is of concern, the output stage of the
opamp can be designed to help mitigate this issue
- Will lead to extra complexity and perhaps other issues
M.H. Perrott 23
 Key Observations for Slew Rate Calculations
Ibias1 Ibias2

-Vid/2 Vid/2 Vout

M1 M2
CL
Rc Cc

M3 M4 M6
Current Limits

Cc  First stage
- Max I = I
1 bias1

Vid
I1 I2 Vout - Min I = -I
1 bias1
avd1 avd2
 Second stage
CL
- Max I = I
2 bias2
- Min I = Large
2

M.H. Perrott 24
 Slew Rate Analysis (First Stage Limits)
Cc

I1 I2
Vid Vout
avd1 avd2
CL
max I1 = Ibias1 max I2 = Ibias2
min I1 = -Ibias1 min I2 = Large

 Slew rate refers to maximum voltage slope at output

- Impact of current limits in first stage:
Z ¯ ¯
1 dVout ¯¯ I1 ¯¯ Ibias1
Vout = − I1dt ⇒ ¯ =− ¯ =
Cc dt max Cc max Cc
¯ ¯
dVout ¯¯ I1 ¯¯ Ibias1
¯ =− ¯ =−
dt min Cc min Cc

M.H. Perrott 25
 Slew Rate Analysis (Second Stage Limits)
Cc

I1 I2
Vid Vout
avd1 avd2
CL
max I1 = Ibias1 max I2 = Ibias2
min I1 = -Ibias1 min I2 = Large

 Impact of current limits in second stage

- Maximum slope at the output:
¯
dVout ¯¯ Ibias2
¯ =
dt max Cc + CL
- Minimum slope at the output:
¯
dVout ¯¯
¯ = Large
dt min
M.H. Perrott 26
 Slew Rate Analysis (Overall)
Cc

I1 I2
Vid Vout
avd1 avd2
CL
max I1 = Ibias1 max I2 = Ibias2
min I1 = -Ibias1 min I2 = Large

 Maximum slope at the output:

¯ Ã !
dVout ¯¯ Ibias1 Ibias2
¯ = min ,
dt max Cc C c + CL
 Minimum slope at the output:
¯
dVout ¯¯ −Ibias1
¯ =
dt min Cc

M.H. Perrott 27
 Impact of Slew Rate

Vdd

Vout

Vss CL
Vin

 Consider the closed loop, unity gain configuration

above with a sine wave input

Vin = A sin(wt)

 Note: the max slope of the input depends on A and w

¯
dVin dVout ¯¯
= Aw cos(wt) ⇒ ¯ = Aw
dt dt max

Slew rate limits the maximum frequency that the amplifier can track
M.H. Perrott 28
 Summary

 Opamp design must take into consideration many

different specifcations
 Today we covered
- Systematic offset voltage
- CMRR
- PSRR and PSRR
+ -

- Input-referred voltage noise

- Slew rate

M.H. Perrott 29
 Analysis and Design of Analog Integrated Circuits
Lecture 19

Advanced Opamp Topologies

Michael H. Perrott
April 11, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Opamps Are Utilized in a Wide Range of Applications
Analog Filters Current References Switched Capacitor Circuits
C1 C2
Iref
R1
Vin Vref Vin
Vout Vout
Vref C1 Vref

Analog Buffers
Rref

Vout
Vin

 Each application comes with different opamp requirements

- How are the input common-mode range requirements
different among the above applications?
- How are the output range requirements different?
- How are the bandwidth requirements different?
Integrated opamps are typically custom designed
for their specific application
M.H. Perrott 2
 Single-Ended Versus Fully Differential Topologies
Single-Ended Fully Differential
C1 C1a

R1 R1a
Vin Vin+
Vout+
Vout
Vref Vin- Vout-
R1b

C1b

 Analog circuits are sensitive to noise from the power

supply and other coupling mechanisms
 Fully differential topologies can offer rejection of
common-mode noise (such as from supplies)
- Information is encoded as the difference between two
signals
- More complex implementation than single-ended
designs
M.H. Perrott 3
 Key Focus of Lecture

 Examine fully differential version of basic two stage

opamp
 Examine more advanced opamp topologies and the
advantages/disadvantages they present

M.H. Perrott 4
 Fully Differential Version of Basic Two Stage Opamp

M8
M7b M5 M7a

Iref Vout- Vin- Vin+ Vout+

M1 M2
CLb CLa

Ccb Rcb Vbias Rca Cca

M6b M3 M4 M6a

 We can separate this into differential and common

mode circuits, similar to a single differential amplifier
- Differential behavior same as the single-ended opamp
 Note that we have twice the effective range in
input/output swing due to the differential signaling
- Common mode setting needs to be dealt with
5
M.H. Perrott
 Illustration of Common Mode Influence
C1a

R1a
Vin+
Vout+
Vin- Vout-
R1b

C1b

Common-Mode Too High Common-Mode Too Low Common-Mode Just Right

Vdd Vdd Vdd
Vcm Vcm
Vcm
Vout+ Vout- Vout+ Vout- Vout+ Vout-
Gnd Gnd Gnd

 Maximum swing for fully differential signals requires

- Accurate setting of the common mode value
- Suppression of common mode noise
M.H. Perrott 6
 Common-Mode Gain From Input
Common-Mode Half Circuit

M8
M7b 2ro5 2ro5 M7a

Iref Vout- vic vic Vout+

M1 M2
CLb CLa

Ccb Rcb Rca Cca

M6b ro3 ro4 M6a

 Analysis is same as for single-ended design

- Can be simplified to common-mode “half-circuit”
ro4
avc = gm6a (ro6a||ro7a )
1/gm2 + 2ro5
- Common-mode output is sensitive to common-mode input
M.H. Perrott 7
 Common-Mode Gain From Input Bias
Common-Mode Half Circuit

M8
M7b 2ro5 2ro5 M7a

Iref Vout- vic vic Vout+

M1 M2
CLb CLa
Vbias
Ccb Rcb Rca Cca

M6b M3 M4 M6a

 Common mode “half circuit can still be used

avbias ≈ (gm4ro4) gm6a (ro6a||ro7a )
- Common-mode output is extremely sensitive to V bias!

M.H. Perrott 8
 Common Mode Feedback Biasing (CMFB)

Common-Mode Half Circuit

M8
M9 Rlarge M7b 2ro5 2ro5 M7a

Iref Vref Rlarge Vout- vic vic Vout+

M10 M11 M1 M2
CLb CLa
Vbias Ccb Rcb Rca Cca

M12 M13 M6b M3 M4 M6a

 Use an auxiliary circuit to accurately set the common

mode output value to a controlled value Vref
- Need to be careful not to load the outputs with the
common mode sensing circuit (R in this case) large
- Need to design CMFB to be stable
M.H. Perrott 9
 Parasitic Pole/Zero Pair of Current Mirrors
Single-Ended Fully-Differential

M5 M5

Vin- Vin+ Vin- Vin+

M1 M2 M1 M2

isc isc- isc+

Vbias

M3 M4 M3 M4

 Single-ended signal travels through current mirror

- Introduces an extra parasitic pole/zero
gm3
wp par = wz par = 2wp par
Cgs3 + Cgs4
 Fully differential signal does not see this pole/zero pair
M.H. Perrott 10
 Closer Examination of Pole/Zero Relationship
Single-Ended

M5

-Vid/2 Vid/2
M1 M2 isc (a)+(b)
(a) (b)
vid
isc (b)
(a)
M3 M4 w
wp_par wz_par

 Note that signal at V2 is composed of the sum of

paths (a) and (b) shown above
µ ¶
isc(s) gm gm 1
= +
vid(s) 2 2 1 + s/wp par
µ ¶
gm 2 + s/wp par 1 + s/(2wp par )
= = gm
2 1 + s/wp par 1 + s/wp par
M.H. Perrott 11
 Summary of Single-Ended Versus Fully Differential
Single-Ended Fully Differential
C1 C1a

R1 R1a
Vin Vin+
Vout+
Vout
Vref Vin- Vout-
R1b

 Advantages of fully differential topologies

C1b

- Improved CMRR and PSRR across a wide frequency range

- Twice the effective signal swing
- Removal of pole/zero pair due to current mirror
 Potentially improved phase margin
 Disadvantages of fully differential topologies
- Power and complexity
Most opamp topologies can be modified to support
either single-ended or fully differential signaling
M.H. Perrott 12
 Telescopic Opamp (Fully Differential Version)
Controlled Vbias3
by CMFB
M7 M8
Vbias2

Vout- M5 M6 Vout+

CL Vbias1 CL
M4

Vin+ M3 M4 Vin-
Iref M1 M2

M10 M9

 Popular for high frequency applications

- Single stage design
- Limitation: input and output swing quite limited
M.H. Perrott 13
 Open Loop Response of Telescopic Opamp

Controlled Vbias3 20log(K)

by CMFB
M7 M8 20log (Vout+-Vout-)/Vid
Vbias2

Vout- M5 M6 Vout+ 0dB

CL Vbias1 CL
M4 w (rad/s)
M3 M4 wdom w0 wp
-Vid/2 Vid/2
Iref M1 M2

M10 M9  Determine K, wdom, wo, wp

 Why is this topology good for high bandwidth

applications?
M.H. Perrott 14
 Open Loop Response of Telescopic Opamp

Controlled Vbias3 20log(K)

by CMFB
M7 M8 20log (Vout+-Vout-)/Vid
Vbias2

Vout- M5 M6 Vout+ 0dB

CL Vbias1 CL
M4 w (rad/s)
M3 M4 wdom w0 wp
-Vid/2 Vid/2
Iref M1 M2

K = gm2Rout wdom = 1/(Rout CL)

M10 M9
gm2 gm4
wo = wp ≈
CL Cgs4 + Cs4,d2
where Rout = ((gm4ro4)ro2)||((gm6 ro6)ro8)

 Notice that parasitic pole is much higher than for two

stage opamp, yielding higher potential unity gain BW
M.H. Perrott 15
 Telescopic Opamp (Single-Ended Version)

M7 M8
Vbias2

M5 M6 Vout

Vbias1 CL
M4

Vin+ M3 M4 Vin-
Iref M1 M2

M10 M9

 Issue: parasitic pole lower than fully differential

version
gm7 gm4
wp2 ≈ < wp1 ≈
Cgs7 + Cgs8 + Cd3,d5 Cgs4 + Cs4,d2
- Singled-ended version not as useful for wide bandwidth
M.H. Perrott 16
 Folded Cascode Opamp

Must set Ibias2 > Ibias1/2 Vbias4

Ibias2 M9 M10 Ibias2

Vbias3
Ibias1/2 Ibias1/2
Vout- M7 M8 Vout+
Vin+ Vin-
Iref M1 M2 CL Vbias2 CL

Ibias2-Ibias1/2 M5 M6 Ibias2-Ibias1/2
M11 M12 Controlled Vbias1
by CMFB M3 M4

 Modified version of telescopic opamp

- Significantly improved input/output swing
- High BW (better than two stage, worse than telescopic)
- Single stage of gain (lower than telescopic)
M.H. Perrott 17
 Open Loop Response of Folded Cascode Opamp
Vbias4 More capacitive
20log(K)
20log (Vout+-Vout-)/Vid M9 M10 loading than
for telescopic
0dB

w (rad/s) Vbias3
wdom w0 wp
Vout- M7 M8 Vout+
Vid/2 -Vid/2
Iref M1 M2 CL Vbias2 CL

M5 M6
Controlled Vbias1
M11 M12
by CMFB
M3 M4

K = gm2Rout wdom = 1/(RoutCL)

Ro10 is lower than for
gm2 gm8 telescopic due to higher
wo = wp ≈
CL Cgs8 + Cd2,d10,s8 drain current in M10

where Rout = ((gm6ro6)ro4)||((gm8 ro8)ro10 )

M.H. Perrott 18
 Two Stage with Cascoded Output Stage

M10
M5 M9
Vbias2
Iref Vin- Vin+
M1 M2 M8
Vout

Rc Cc Vbias1 CL

M7
M3 M4
M6

 Higher DC gain than with two stage or folded cascode

- Two gain stages with boosted gain on the output stage
 Same output swing as folded cascode
- Lower than for basic two stage
M.H. Perrott 19
 Open Loop Response Calculations

M10
M5 M9
Vbias2
Iref -Vid/2 Vid/2
M1 M2 M8
Vout

Rc Cc Vbias1 CL
20log(K)
20log Vout/Vid
M7
0dB M3 M4
w M6
wdom w0 wp

K = gm2(ro2||ro4 )gm6Rout wdom = 1/((ro2||ro4 )CM )

gm2 gm6
wo = wp ≈
Cc CL
where Rout = ((gm7ro7)ro6)||((gm8 ro8)ro9)
CM ≈ (gm6Rout) Cc
M.H. Perrott 20
 Two Stage with Cascoded Input Stage

M8
M5 M7
3Ibias

Iref Vin- Vin+

M13
M1 M2
M11 M12 Vout

Rc Cc CL
Ibias

Vbias1

M9 M10

M3 M4 M6

 Compared to two stage with cascoded output

- Similar DC gain
- Improved output swing
- Reduced input swing
M.H. Perrott 21
 Open Loop Response Calculations

M8
M5 M7
3Ibias

Iref -Vid/2 Vid/2

M13
M1 M2
M11 M12 Vout
20log(K)
20log Vout/Vid Rc Cc
Ibias CL
0dB
Vbias1
w
wdom w0 wp M9 M10

M3 M4 M6
K = gm2Rout1 gm6(ro6||ro7 )
gm2 gm6
wdom = 1/(Rout1 CM ) wo = wp ≈
Cc CL
where Rout1 = ((gm12ro12)ro2)||((gm10 ro10)ro4)
CM ≈ (gm6(ro6 ||ro7)) Cc 22
M.H. Perrott
 Summary

 Opamp topologies can be configured to process fully

differential signals
- Provides improved immunity to noise from common-mode
perturbations such as power supply noise
- Increases effective signal swing by a factor of two
- Carries additional complexity for CMFB and increased
power consumption
 Integrated opamps are often custom designed for a
given application
- Each application places different demands on DC gain,
bandwidth, signal swing, etc.
- Opamp topologies considered today include telescopic,
folded cascode, and modified two stage
 Each carries different tradeoffs on the above specifications

M.H. Perrott 23
 Analysis and Design of Analog Integrated Circuits
Lecture 20

Advanced Opamp Topologies (Part II)

Michael H. Perrott
April 15, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Outline of Lecture

 Gain boosting technique

 Nested Miller technique
 Replica bias technique
 Improved slew rate opamp example

M.H. Perrott 2
 Recall the Folded Cascode Opamp

Must set Ibias2 > Ibias1/2 Vbias4

Ibias2 M9 M10 Ibias2

Vbias3
Ibias1/2 Ibias1/2
Vout- M7 M8 Vout+
Vin- Vin+
Iref M1 M2 CL Vbias2 CL

Ibias2-Ibias1/2 M5 M6 Ibias2-Ibias1/2
M11 M12 Controlled Vbias1
by CMFB M3 M4
 Modified version of telescopic opamp
- Significantly improved input/output swing
- High BW (better than two stage, worse than telescopic)
- Single stage of gain (lower than telescopic)
Can we further boost the DC gain?
M.H. Perrott 3
 Gain Boosting of Current Sources
Iout

DC Gain = K Rout
Iout Vref
DC Gain = K Rout
Vref
M1 vgs gm1vgs -gmb1vs ro1

Rref
vs Rref

 We can achieve increased output impedance of a

current source with an amplifier
- The amplifier essentially increases g m1 by factor K

Rout = (Kgm1ro1) Rref

 Key issue: what is a convenient implementation of

the above circuit? 4
M.H. Perrott
 A Simple Gain Boosting Amplifier
Iout Iout
DC Gain = K Rout Ibias Rout
Vref
M1 Iref M1 Iref

M4

M2 M3 M2 M3

 Common source amplifier utilized

K = gm4ro4, Rref = ro2

⇒ Rout = (gm4ro4) (gm1ro1) ro2 ≈ (gmro)2 ro2

 Issue: current source requires significant headroom

due to the fact that Vds2 = Vgs4
M.H. Perrott 5
 Folded Cascode Gain Boosting Amplifier
Vbias4

M8 Iout
Vbias3
Rout
M7
M1 Iref
Vbias5
Vbias2

M6 M4
Vbias1 M2 M3

M5
 Folded cascode yields
K = gm4 (((gm6ro6)ro5)||((gm7 ro7)ro8))
⇒ Rout ≈ (gmro)3ro2
- Improved headroom and higher gain!
Is there a convenient way to set Vbias5?
M.H. Perrott 6
 Differential Version of Gain Boosting Amplifier
Iout Iout
Vbias4 Rout Rout Vbias4

M13 Ibias M14

Vbias3 Vbias3

M11 M12
M1 M2
Vbias2 Vbias0 Vbias2

M9 M5 M6 M10
Vbias1 M3 M4 Vbias1

M7 M8

 Leverage fully differential nature of current sources

within the opamp
- PMOS gain devices are now part of a differential pair
- Need CMFB to set common-mode gate voltages of M 1
and M2
M.H. Perrott 7
 Symbolic View of Folded Cascode Gain Boosting Amp
Iout Iout
Rout Rout

M1

Vbias0

M3 M4

 We can apply this to the overall folded cascode

opamp

M.H. Perrott 8
 Folded Cascode with Gain Boosting

Vbias4

M9 M10

Vout- Vout+
M7 M8
Vin- Vin+ CL CL
Iref M1 M2
M5 M6

M11 M12 Controlled Vbias1

by CMFB M3 M4

 Gain boosting provides substantial increase of DC

gain while maintaining good input and output swing
- Gain is on the order of (g r ) m o
4

 Issue – very complex!

M.H. Perrott 9
 Recall Pole Splitting for Two Stage Compensation

20log Vout/Vid

gm -gm

w (rad/s)

wp1 wp2
wp2 wp1

 Moves the dominant pole of the second stage to higher

frequencies such that it becomes a parasitic pole
 Places the first stage pole as the dominant pole
- Leverages the gain of the second stage to achieve
capacitor multiplication using the Miller effect

Can we extend the pole splitting technique

to more than 2 gain stages?
M.H. Perrott 10
 Nested Miller Compensation

20log Vout/Vid

gm gm -gm

w (rad/s)
Eschauzier, JSSC
Dec 1992 wp1 wp2,wp3
wp3 wp2 wp1

 Advantage: increased DC gain with high input and

output swing
 Issue: more parasitic poles to deal with
- Leads to lower unity gain bandwidth for reasonable
phase margin

Proving to be a useful technique in advanced CMOS processes

which offer fast speed (high gm/C) but low intrinsic gain (low gmro)
M.H. Perrott 11
 Nested Miller Example

M8 M7
M5 M9

Iref Vin- Vin+ Vbias Vout

M1 M2 M10 M11 Cc2
CL

Cc

M3 M4 M12 M13 M6

 Intermediate gain stages must be non-inverting in

order to achieve stable feedback
 Compensation resistors should also be included to
eliminate the impact of RHP zeros
- Not shown for simplicity
M.H. Perrott 12
 Recall the Telescopic Opamp

Controlled Vbias3
by CMFB
M7 M8
Vbias2

Vout- M5 M6 Vout+

CL Vbias1 CL
M4

Vin+ M3 M4 Vin-
Iref M1 M2

M10 M9

 Key issue is input swing

- Can we improve this?
M.H. Perrott 13
 Replica Bias Technique

Controlled Vbias3
by CMFB
M7 M8
Vbias2

Vout- M5 M6 Vout+
Iref
CL Vbias1 CL
K M4

Vin+ M3 M4 Vin-
Vin+ Vin-
M1 M2

M11 M12
Gulati, JSSC
M10 M9 Dec, 1998

 Allows current source to maintain its output current

even for low Vds using dynamic bias of Vgs
- Allows extended input common-mode range
M.H. Perrott 14
 Recall: Slew Rate Issues for Opamps

Vdd Vin

Vout
ideal
Vss CL
Vin Vout
slew-rate limited

 Output currents of practical opamps have max limits

- Impacts maximum rate of charging or discharging load
capacitance, C L
- For large step response, this leads to the output lagging
behind the ideal response based on linear modeling
 We refer to this condition as being slew-rate limited
 Where slew-rate is of concern, the output stage of the
opamp can be designed to help mitigate this issue
- Will lead to extra complexity and perhaps other issues
M.H. Perrott 15
 Key Observations for Slew Rate Calculations
Ibias1 Ibias2

-Vid/2 Vid/2 Vout

M1 M2
CL
Rc Cc

M3 M4 M6
Current Limits
 First stage
Cc - Max I = I
1 bias1

I1 I2
- Min I = -I
1 bias1
Vid
avd1 avd2
Vout  Second stage
CL
- Max I = I
2 bias2
- Min I = Large
2

How can we improve opamp slew rate?

M.H. Perrott 16
 Class A and AB Amplifiers/Buffers
Class A Amplifier Class AB Amplifier/Buffer

Vbias

M2 Ibias M2 Ibias
M1 Ibias
Vout Vout
Vin
Vbias Vout
Vin
Vin
M1 M1
M2

 Class A
- Maximum slew rate in one direction is set by the
nominal bias current
 Class AB
- Maximum slew rate is not set by the nominal bias
current
 Goal: low nominal bias current
M.H. Perrott 17
 Class AB Opamp
M9 M5 M6 M10

Ibias Ibias

Vin- Vin+

Vout- M1 M2 Vout+
Vbias Vbias
CL CL

M3 M4
Costello, JSSC
Dec 1985
M11 M7 M8 M12

 Low bias current can be achieved for Vin+ = Vin-

- Must properly set V bias
 Much higher current when Vin+ ≠ Vin-
 DC gain can be increased through cascoding of
output stage
M.H. Perrott 18
 Biasing Network for Class AB Opamp
M9 M5 M6 M10

Ibias Ibias

Vin- Vin+

Vout- M13 M1 M2 M15 Vout+

CL M14 M16 CL

Iref M3 M4 Iref

M11 M7 M8 M12

 Bias current set by

- Ratio of device sizes of M -M 1 4 versus M13-M16
- I current
ref

M.H. Perrott 19
 Summary

 Opamps invite a wide variety of techniques to address

different application requirements
- Cleverness can substantially improve performance and
robustness
- Changing of CMOS processes over time leads to new
techniques which were previously unnecessary or
unpractical
 Four techniques discussed today
- Gain boosting
- Nested Miller
- Replica bias
- Class AB stages

M.H. Perrott 20
 Analysis and Design of Analog Integrated Circuits
Lecture 21

Sampling

Michael H. Perrott
April 18, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Outline of Lecture

 Basic CMOS sampling structure

 Feedback sampling
 Noise of CMOS sampling structure

M.H. Perrott 2
 The Need for Sample and Hold Circuits

Vin(t) Vout(t) Analog-to-Digital Digital

S/H
Converter Processing

Vout(t)
Vin(t)

 Analog-to-digital converters (ADC) are key elements in

allowing digital processors to interact with “real world”
signals in the acoustic, RF, and optical domains
 Sample and hold circuits are often utilized to keep the
input signal into the ADC constant while it is
performing its conversion
- Key metrics: sampling accuracy, sampling speed, hold
time (while maintaining accuracy)
M.H. Perrott 3
 Track and Hold Versus Sample and Hold
Track and Hold

Volts Vout(t)
Vin(t) Vout(t) Vin(t)
t
Vclk(t)
CL
Sample and Hold

Volts Vout(t)
Vin(t)
t

 Track and hold alternates between following and

holding the input value
 Sample and hold can be created by cascading two
track and hold circuits
- Similar to digital registers which are created by
cascading two latches
M.H. Perrott 4
 Track and Hold Based on a CMOS Switch
Track and Hold

Vclk(t)
Volts
Vin(t) Vout(t) Vclk(t)

CL Vout(t)
Vin(t)
t

 CMOS transistors make nice switches

- Much better than bipolar devices since they do not have
the issue of base charge storage
 Key performance issues
- Switch resistance
- Charge injection
- Leakage
M.H. Perrott 5
 Impact of Switch Resistance
Track and Hold

Vclk(t)
Volts
Vin(t) Vout(t) Vclk(t)

Rch CL Vout(t)
Vin(t)
t

 Accurately following the input by the end of the

tracking period is important in order to achieve an
accurate hold value
- Switch resistance, R ch,
and load capacitance, CL, form a
lowpass filter with limited bandwidth
 Low Rch is desirable for better tracking behavior
 The cutoff frequency of the RC lowpass must be
significantly higher than the frequency of Vclk(t)
M.H. Perrott 6
 Calculation of Switch Resistance
Track and Hold

Vclk(t)
Volts
Vin(t) Vout(t) Vclk(t)

Rch CL Vout(t)
Vin(t)
t

 Assuming that the input and output of the switch are

reasonably close in value (i.e., Vds is small), we can
assume triode operation of the transistor
1
⇒ Rch ≈
μnCox W/L(Vgs − VT H )
- For low R ch,
we want:
 Large W, Small L, Large Vgs
 Issue: we need Vgs > VTH
M.H. Perrott 7
 Impact of Charge Injection
Track and Hold
Vclk(t)
Cov Cov Volts
Vin(t) Vout(t) Vclk(t)

Channel CL
Charge Vout(t)
Vin(t)
t
Ideal behavior
 Charge injection disturbs the tracked value due to
charge transfer that occurs from two key sources
- Overlap capacitance
 Caused by capacitive coupling of clock edge onto load
capacitor, CL
- Channel charge
 Caused by expelling the channel charge as device is
abruptly turned off
M.H. Perrott 8
 Calculation of Charge Injection Impact
Track and Hold
Vclk(t) VHI
Cov Cov Vclk(t)
Volts
Vin(t) Vout(t)
VLO
Channel Vin(t)
CL
Charge Vout(t) (desired)
ΔV V (t) (actual)
out
t

 Change in voltage due to overlap capacitance and

charge injection (for fast fall time on Vclk(t))
Cov qch 1
∆V ≈ − (VHI − VLO ) +
Cov + CL 2 CL
- where
qch = −Cox W L(Vgs − VT H )
= −CoxW L(VHI − Vin − VT H )
M.H. Perrott 9
 Signal Dependence Versus Offset for Charge Injection
Track and Hold
Vclk(t) VHI
Cov Cov Vclk(t)
Volts
Vin(t) Vout(t)
VLO
Channel Vin(t)
CL
Charge Vout(t) (desired)
ΔV V (t) (actual)
out
t

 Overall charge injection impact (from previous slide)

Cov Cox
∆V ≈ − (VHI −VLO )− W L(VHI −Vin −VT H )
Cov + CL 2CL
Overlap Capacitance Channel Charge

Cox Cov Cox

∆V ≈ W LVin − (VHI −VLO )− W L(VHI −VT H )
2CL Cov + CL 2CL
Signal Dependent Offset
M.H. Perrott 10
 Minimizing Charge Injection
Track and Hold
Vclk(t) VHI
Cov Cov Vclk(t)
Volts
Vin(t) Vout(t)
VLO
Channel Vin(t)
CL
Charge Vout(t) (desired)
ΔV V (t) (actual)
out
t
Cox Cov Cox
∆V ≈ W LVin − (VHI −VLO )− W L(VHI −VT H )
2CL Cov + CL 2CL
Signal Dependent Offset
 Signal dependent charge injection is reduced by
- Lowering the size of the device (WL)
- Increasing C L

Each of the above leads to an unacceptable increase in RchCL

(large L is especially problematic – it should be kept at minimum)
M.H. Perrott 11
 Adding a Dummy Device

Vclk(t) Vclk(t)
Cov Cov Cov Cov
Vin(t) 2 2 Vout(t)
M1 Mdummy
Channel CL
Charge

 Consider adding a dummy device, Mdummy, that has

half the width of the switching device, M1
- Use minimum length for both devices
 In theory, both overlap cap impact and charge
injection should be cancelled!
- In practice, this does not work so well due to poor clock
edge alignment, variable behavior of M1 charge injection
M.H. Perrott 12
 Using Complementary Switches

Vclk(t) Vclk(t)

Vin(t) Vout(t)

CL
Vclk(t)

 Cancels influence of overlap capacitance to some degree

 Worse for channel charge injection
- This leads to worse signal dependent charge injection
 Reduces switch resistance (this is very useful)
- Parallel combination of R and Rchn
chp
 Worst case: when Vin is in the middle of the supply range
M.H. Perrott 13
 Bootstrapped Switches
Vclk(t)
Bootstrap
Circuit Vclk(t)
Vin(t) Vout(t) Vin(t)

CL

 Bootstrapping offers several nice benefits

- Increased gate drive (often above the supply voltage)
 Reduces R while allowing a smaller switch size
ch
- Constant voltage between the input and clock during the
tracking phase
 Greatly reduces signal dependent charge injection issues
 Bootstrapping backgate is also becoming common with
deep N-well processes
- Recent example: Brunsilius et. al., ISSCC 2011
M.H. Perrott 14
 Buffered Track and Hold Circuit using Opamp

Vclk(t)
Vout(t) Analog-to-Digital
Vin(t)
Converter
CL
Cpar

 Provides several benefits

- Increases settling bandwidth to allow faster sampling
frequency
 Assuming parasitic cap, Cpar, is less than load cap, CL
 Issue: we will see that we need a reasonable large
sampling capacitor for noise reasons
- Isolation of sensitive switch output from any
perturbations from the ADC (such as kickback from its
internal switches)
 Issue: adds additional offset voltage of the opamp
M.H. Perrott 15
 Use Feedback Sampling to Mitigate Opamp Offset
Φ1d(t) Φ1(t)
Vin(t) Φ1(t)
Cs
Φ2(t) Vout(t) Φ1d(t)

Vref
CL Φ2(t)

 Uses different placement of the sampling capacitor,

Cs, between track and hold phases
- We will see how this can largely eliminate the impact of
opamp offset
 Such feedback sampling topologies often require
multi-phase clocks
- Key goal is to achieve non-overlapping ‘On’ times such
that current flow does not occur through multiple
switches at once
M.H. Perrott 16
 First Consider Tracking Phase on Sampling Cap C1

Vin Φ1d(t) VCs Φ1(t) Φ1(t)

Cs Voff
Φ1d(t)
Vout
K
Φ2(t) Vref
CL Φ2(t)

 First calculate Vout

Vout = K(Vref − (Vout + Voff ))
K
⇒ Vout = (Vref − Voff ) ≈ Vref − Voff
K+1
 We now calculate VCs as

VCs = Vin − Vout = Vin − (Vref − Voff )

M.H. Perrott 17
 Now Consider Hold Phase on Sampling Cap C1

Vin Φ1d(t) VCs Φ1(t) Φ1(t)

Cs Voff
Φ1d(t)
Vout
K
Φ2(t) Vref
CL Φ2(t)

 Calculate Vout as
Vout = K(Vref − (Vout − VCs + Voff ))
K
⇒ Vout = (Vref +VCs−Voff ) ≈ Vref +VCs−Voff
K+1
 Recall that VCs = Vin – Vref + Voff
⇒ Vout ≈ Vref + Vin − Vref + Voff − Voff = Vin

Impact of opamp offset is cancelled out!

M.H. Perrott 18
 Fully Differential Version of Feedback Sampler
Φ2(t)

Φ1(t)
Φ1d(t) Φ1(t)
Φ1d(t)
Vin+(t)
Cs
Vout+(t) Φ2(t)

Vout-(t)
CL
Cs CL
Vin-(t)

Φ1d(t) Φ1(t)

Φ2(t)

 Helps to cancel out the influence of charge injection

- Appears as common-mode noise source
M.H. Perrott 19
 Influence of Thermal Noise on Sampling
Tracking Phase Hold Phase
Vclk(t)
Vin(t) Vout(t) Vin(t) Vout(t)

Rch vn2 Cs Cs

 CMOS switch adds noise during the tracking phase

- This noise is sampled as the switch is turned off at the
beginning of the hold phase
 Calculation of the variance (i.e. power) of the sampled
noise
- First determine the spectral density of the noise during
the tracking phase
- Integrate the spectral density to obtain the variance of
then noise
M.H. Perrott 20
 Calculation of Noise Spectral Density (Double Sided)
Vclk(t)
Vin(t) Vout(t) Rch

Rch 2
vn Cs vn2 Cs Vout

 Spectral density at output (double sided):

2 2
SVout (f) = |H(f )| Svn (f ) = |H(f )| 2kT Rch
- Where
1 1
H(s) = ⇒ H(f ) =
1 + sRch Cs 1 + jf 2πRch Cs
 A useful fact Z
∞ ¯ ¯2
¯ 1 ¯
¯ ¯ df = πfo
¯ ¯
f =−∞ 1 + jf /fo
M.H. Perrott 21
 Calculation of Noise Variance
Vclk(t)
Vin(t) Vout(t) Rch

Rch 2
vn Cs vn2 Cs Vout

 Calculation of noise variance

¯ ¯2
Z ∞ Z ∞ ¯ 1 ¯
PVout = σV2 out = SVout (f )df = ¯ ¯ 2kT Rch df
¯ 1 + jf /fo ¯
−∞ −∞
- Where fo =
1
2πRch Cs
1 kT
⇒ σV2 out = πfo 2kT Rch = π 2kT Rch =
2πRch Cs Cs

Sampled noise variance depends only on the sample cap value!

M.H. Perrott 22
 Summary

 The CMOS sampling circuit is a key element for many

systems
- Analog to digital conversion
- Switched capacitor filters (to be discussed in MIC513)
 Key issues for sampling circuits are
- Accuracy (i.e., offset, noise)
 Key insight: noise set by sample cap value
- Speed (i.e., setting time)
- Leakage
 Opamp feedback circuits are often combined with CMOS
sampling circuits
- Provide buffering and isolation of kickback from the circuit
that follows
- Introduce extra offset and noise
 Clever circuit topologies can largely eliminate opamp offset
M.H. Perrott 23
 Analysis and Design of Analog Integrated Circuits
Lecture 22

Digital to Analog Conversion

Michael H. Perrott
April 22, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Outline of Lecture

 Basic DAC Specifications

 Types of DACs (Resistive, Current, Capacitive)
 Impact of dynamic operation (NRZ, RZ)
 Sigma-Delta operation for high resolution

M.H. Perrott 2
 Digital to Analog Conversion
Vout
4V
4 ref
3V
D0 4 ref
D1 2V
DAC Vout or Iout 4 ref
DN-1 1V 1 LSB
4 ref
D 2D 1 D 0
000 001 111
 Digital input consists of bits, Dk, with values 0 or 1
 Analog output is either voltage or current
Vref N−1 D N−2 D 1D +20D )
Vout = (2 N−1 +2 N −2 +· · · 2 1 0
2N
 Key characteristics
- Full scale = V ref

M.H. Perrott
- Resolution = V ref/2
N = 1 LSB 3
 Gain and Offset Errors
Offset Error Gain Error
Vout Vout

7V 7V
8 ref 8 ref

Voffset

D 2 D 1D 0 D 2 D 1D 0
000 111 000 111

 Offset is most easily characterized as

Voffset = Vout |Dk =0

 Gain error is characterized either as

- Error at full scale (in LSBs)
- Percentage of full scale
M.H. Perrott 4
 Nonlinearity
Nonlinearity
Vout

7V
8 ref
INL

D 2 D 1D 0
000 111

 Integral Non-Linearity (INL)

- Maximum deviation from the “ideal line” characterisitic
 Typically specified in units of LSBs
 Differential Non-Linearity (DNL)
- Maximum deviation of all codes from their ideal step
size of 1 LSB

M.H. Perrott 5
 Monotonicity
Non-Monotonic
Vout

7V
8 ref

D 2 D 1D 0
000 111

 Monotonic behavior requires that stepping any code

to the next code yields a step in the output that is
always the same sign
- Important in systems which utilize the D/A converter as
part of a feedback
 Non-monotonicity yields changes in the sign of the gain,
which can lead to small signal stability problems
M.H. Perrott 6
 Binary Resistor DAC
Vref

Gnd
D2 D1 D0
R
2R 4R 8R

Vout
Vref
CL

 Relies on accurate resistor ratios for good INL/DNL

 Issues
- Switches contribute resistance
 Can impact accuracy without clever design measures
- Resistors require significant area for a high resolution
DAC
M.H. Perrott 7
 Binary Current DAC

4Iref 2Iref Iref

D2 D1 D0 R

Vout
Vref
CL

 Advantages
- Switch resistance does not impact accuracy (to first
order)
- Scaled current sources are readily obtained using
current mirror techniques
 Issues
- Likely to have higher 1/f noise than resistor based DAC
- Opamp limits bandwidth, adds noise
M.H. Perrott 8
 Binary Current DAC with Resistive Load

4Iref 2Iref Iref

D2 D1 D0

Vout

R CL

 No opamp required
- Useful for high speed applications
 Issues
- Current sources must now bear the full output range
 Much harder to maintain constant current from them
 Cascoding takes up headroom
 Can lead to code dependent nonlinearity (i.e., poor INL,
distortion)
M.H. Perrott 9
 Binary Versus Thermometer Encoding
Binary Thermometer
Vref Vref
R
Vout
Gnd R
D2 D1 D0 CL
R
2R 4R 8R

Vout Binary-to-Thermometer
R
Decoder
Vref
CL R
D2 D1 D0

 Thermometer encoded resistor ladder provides

inherently monotonic behavior
 Issues for high resolution
- Decoding becomes very complex
- Area can be quite large
M.H. Perrott 10
 Capacitor DAC
Vref

DN-1 DN-2 D2 D1 D0

2N-1C 2N-2C 4C 2C C Φ0

Vout
C

 Uses charge re-distribution on a capacitor network to

realize output voltages
- Key advantage is that capacitor matching is quite good
in CMOS processes
- Has become the preferred approach for low to modest
speed discrete-time ADCs
M.H. Perrott 11
 Operational Details of Capacitor DAC
Vref

DN-1 DN-2 D2 D1 D0

2N-1C 2N-2C 4C 2C C Φ0

Vout
C

 First discharge all capacitors to zero (Dk = 0, 0 = 1)

 Set P0 = 0 and then set Dk values
Vref ³ ´
Vout = N DN −1 2N −1 C + DN−2 2N −2 C N −2 + · · · + D12C + D0C
2 C
Vref ³ ´
⇒ Vout = DN −1 2N −1 + DN−2 2N−2 + · · · + D12 + D0
2N
M.H. Perrott 12
 Seeking Higher Resolution
Vout

D0
D1
DAC Vout or Iout
DN-1 1 LSB

D 2D 1 D 0
000 001 111

 Increasing the number of levels in the DAC achieves

higher resolution at the cost of complexity and power
- At some point, improved resolution becomes
impractical with this approach
 An alternative approach is to consider dithering
between levels of a coarse DAC
- By averaging the output, we can obtain resolution finer
than the LSB of the coarse DAC
M.H. Perrott 13
 Sigma-Delta Modulation

Time Domain

M-bit Input 1-bit Analog Output

Digital Σ−Δ
D/A
Modulator

Frequency Domain
Digital Input Quantization Analog Output
Spectrum Noise Spectrum

Input

Σ−Δ
 Sigma-Delta dithers in a manner such that resulting
quantization noise is “shaped” to high frequencies
M.H. Perrott 14
 Linearized Model of Sigma-Delta Modulator

r[k] S r(ej2πfT)= 1
12

NTF Hn(z)
z=ej2πfT
1
STF q[k]
x[k] y[k] x[k] y[k]
Hs(z)
Σ−Δ
z=ej2πfT

S q(ej2πfT)= 1 |H n(ej2πfT)| 2
12

 Composed of two transfer functions relating input and

noise to output
- Signal transfer function (STF)
 Filters input (generally undesirable)
- Noise transfer function (NTF)
 Filters (i.e., shapes) noise that is assumed to be white
M.H. Perrott 15
 Example: Cutler Sigma-Delta Topology

x[k] u[k] y[k]

H(z) - 1 e[k]

 Output is quantized in a multi-level fashion

 Error signal, e[k], represents the quantization error
 Filtered version of quantization error is fed back to
input
- H(z) is typically a highpass filter whose first tap value is 1
 i.e., H(z) = 1 + a z + a z 
1
-1
2
-2

- H(z) – 1 therefore has a first tap value of 0

 Feedback needs to have delay to be realizable
M.H. Perrott 16
 Linearized Model of Cutler Topology
r[k]
x[k] u[k] y[k] x[k] u[k] y[k]

H(z) - 1 e[k] H(z) - 1 e[k]

 Represent quantizer block as a summing junction in

which r[k] represents quantization error
- Note:

 It is assumed that r[k] has statistics similar to white

noise
- This is a key assumption for modeling – often not true!
M.H. Perrott 17
 Calculation of Signal and Noise Transfer Functions
r[k]
x[k] u[k] y[k] x[k] u[k] y[k]

H(z) - 1 e[k] H(z) - 1 e[k]

 Calculate using Z-transform of signals in linearized

model

- NTF: Hn(z) = H(z)

- STF: Hs(z) = 1
M.H. Perrott 18
 A Common Choice for H(z)

7 m=3

5
Magnitude

4 m=2

m=1
2

0
0 1/(2T)
Frequency (Hz)
M.H. Perrott 19
 Example: First Order Sigma-Delta Modulator

 Choose NTF to be
x[k] u[k] y[k]

H(z) - 1 e[k]

 Plot of output in time and frequency domains with

input of

Magnitude (dB)
Amplitude

0
0 Sample Number 200 0 Frequency (Hz) 1/(2T)
M.H. Perrott 20
 Example: Second Order Sigma-Delta Modulator

 Choose NTF to be
x[k] u[k] y[k]

H(z) - 1 e[k]

 Plot of output in time and frequency domains with

input of

Magnitude (dB)
Amplitude

-1
0 Sample Number 200 0 Frequency (Hz) 1/(2T)
M.H. Perrott 21
 Example: Third Order Sigma-Delta Modulator

 Choose NTF to be
x[k] u[k] y[k]

H(z) - 1 e[k]

 Plot of output in time and frequency domains with

input of

4
3
2 Magnitude (dB)
Amplitude

1
0
-1
-2
-3
0 Sample Number 200 0 Frequency (Hz) 1/(2T)
M.H. Perrott 22
 Observations

 Low order Sigma-Delta modulators do not appear to

produce “shaped” noise very well
- Reason: low order feedback does not properly
“scramble” relationship between input and quantization
noise
 Quantization noise, r[k], fails to be white
 Higher order Sigma-Delta modulators provide much
better noise shaping with fewer spurs
- Reason: higher order feedback filter provides a much
more complex interaction between input and
quantization noise

M.H. Perrott 23
 Warning: Higher Order Modulators May Still Have Tones

 Quantization noise, r[k], is best whitened when a

“sufficiently exciting” input is applied to the modulator
- Varying input and high order helps to “scramble”
interaction between input and quantization noise
 Worst input for tone generation are DC signals that are
rational with a low valued denominator
- Examples (third order modulator with no dithering):
x[k] = 0.1 x[k] = 0.1 + 1/1024
Magnitude (dB)

Magnitude (dB)

0 Frequency (Hz) 1/(2T) 0 Frequency (Hz) 1/(2T)

M.H. Perrott 24
 Fractional Spurs Can Be Theoretically Eliminated

 See:
- M. Kozak, I. Kale, “Rigorous Analysis of Delta-Sigma
Modulators for Fractional-N PLL Frequency Synthesis”,
IEEE Transactions on Circuits and Systems I:
Fundamental Theory and Applications, vol. 51, no. 6, pp.
1148-1162

- S. Pamarti, I. Galton, "LSB Dithering in MASH Delta–

Sigma D/A Converters", IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 54, no. 4, pp. 779 –
790, April 2007.

M.H. Perrott 25
 MASH topology

x[k] r1[k] r2[k]

ΣΔM1[k] M
ΣΔM2[k] 1
ΣΔM3[k] 1

y1[k] y2[k] y3[k]

1-z-1 (1-z-1)2
u[k] y[k]

 Cascade first order sections

 Combine their outputs after they have passed through
digital differentiators

 Advantage over single loop approach

- Allows pipelining to be applied to implementation
 High speed or low power applications benefit

M.H. Perrott 26
 Calculation of STF and NTF for MASH topology (Step 1)

x[k] r1[k] r2[k]

ΣΔM1[k] M
ΣΔM2[k] 1
ΣΔM3[k] 1

y1[k] y2[k] y3[k]

1-z-1 (1-z-1)2
u[k] y[k]

 Individual output signals of each first order modulator

 Addition of filtered outputs

M.H. Perrott 27
 Calculation of STF and NTF for MASH topology (Step 1)

x[k] r1[k] r2[k]

ΣΔM1[k] M
ΣΔM2[k] 1
ΣΔM3[k] 1

y1[k] y2[k] y3[k]

1-z-1 (1-z-1)2
u[k] y[k]

 Overall modulator behavior

- STF: H (z) = 1
s
- NTF: H (z) = (1 – z )
n
-1 3

M.H. Perrott 28
 The Issue of Intersymbol Interference

Clk(t)
4Iref 2Iref Iref

D2 D1 D0 I0(t) (ideal) 0 1 1 1 0
I0
Vout
I0(t)
R CL

 Dynamic operation of a non-return-to-zero (NRZ) DAC

leads to inaccuracy due to transient effects
- Transients only occur when the previous data is
different
 We refer to this data dependent error as intersymbol
interference
 Intersymbol interference especially poses a problem
when using the DAC for data communication

M.H. Perrott 29
 Return-to-Zero (RZ) Signaling

Clk(t)
4Iref 2Iref Iref

D2 D1 D0 I0(t) (ideal) 0 1 1 1 0
I0
Vout

R CL
I0(t)

 Dynamic operation RZ DAC yields consistent results

regardless of the pattern
- Essentially, it inserts transients into every `1’ value
 Issue – half the signal swing is lost

M.H. Perrott 30
 Summary

 DAC structures can be implemented in a variety of ways

- Resistors, currents, capacitors are all possible elements
- Current-based DACS are the favorite for high frequency
operation
- Capacitor-based DACS are the favorite for low to modest
frequency operation
 Key DAC specifications include offset, gain error, and
non-linearity
- Monotonocity is an import specification for DACs used
within feedback loops
 Sigma-Delta modulators can be used to greatly increase
the effective resolution of a DAC
 Dynamic operation of the DAC can lead to error due to
intersymbol interference

M.H. Perrott 31
 Analysis and Design of Analog Integrated Circuits
Lecture 23

Analog to Digital Conversion

Michael H. Perrott
April 25, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Outline of Lecture

 ADC Topologies
- Flash
- SAR
- Pipeline
- Interleaved
- Sigma-Delta
 Special focus on the emerging area of VCO-based
ADCs

M.H. Perrott 2
 Analog to Digital Conversion
D 2 D 1D 0
111

D0
D1
Vin ADC
DN-1
1 LSB
001
000 Vin
1V 7V
0
8 ref 8 ref

 Analog input is typically voltage

 Digital output consists of bits, Dk, with values 0 or 1
 Key characteristics similar to DAC
- Full scale = V
ref
- Resolution = V /2 = 1 LSB
ref
N

- Nonlinearity measured with INL, DNL, Monotonicity

M.H. Perrott 3
 Flash ADC
N-Stage
Resistor
Ladder Pre-Amp Comparator

A 0

A 1
Vref
N
A 1

IN CLK
 Fastest ADC structure (> 1 GHz)
- Performs direct comparison of an input signal to a set of
voltage references using parallel comparators
- Typically limited to 8-bit resolution
- Relatively large area and power for higher resolution
M.H. Perrott 4
 SAR ADC
Vref

DN-1 DN-2 D2 D1 D0

D0
Vdac 2N-1C 2N-2C 4C 2C C Φ0
D1
DAC
DN-1
Vdac
Vin CLK C Vin CLK

 Leverages a DAC to sequentially compare its output

values to the input voltage
- Minimal analog complexity - requires only one
comparator and a capacitor DAC
- Successive Approximation Algorithm (SAR) is efficient
comparison algorithm for comparing DAC to input value
- Has recently become very attractive in advanced CMOS
for modest resolution (i.e., 8 to 10 bits) applications 5
M.H. Perrott
 SAR Algorithm
Vref

Vin

Gnd
D5=0 D4=1 D3=1 D2=0 D1=0 D0=0

 We can efficiently compare the DAC output to the

input voltage, Vin, by successively subdividing the
range from MSB to LSB
- Number of comparisons ≈ number of bits
 Example: 10-bit SAR ADC requires roughly 10
comparisons per sample
M.H. Perrott 6
 Pipeline ADC

Vin Vresidue1 Vresidue2

K K
D0 Vdac1 D0 Vdac2
ADC DAC ADC DAC
DJ-1 DJ-1
CLK

 Resolves ADC bits in several stages

- Earlier stages resolve MSB bits
- Calculate residue for later stages through subtraction of
MSB estimate
 Amplify residue so that all stages operate over similar
voltage ranges
 Pipeline trends
- 1-bit per stage in the past; now going to multi-bit per stage
- For advanced CMOS, interleaved SAR architectures are
starting to look more attractive than pipelines
M.H. Perrott 7
 Interleaved ADC

D0 CLK1
Vin D1
ADC
DN-1 CLK2
CLK1
D0
CLK3
D1
ADC
DN-1 CLK4
CLK2
D0
ADC
D1  Clocking several ADC structures
DN-1 at different clock phases allows
CLK3 much higher effective sample rate
D0
D1
- Can interleave Flash, SAR, or
ADC Pipeline ADCs

CLK4
DN-1
 Key challenges include clock
skew, mismatch between ADCs,
higher input capacitance
M.H. Perrott 8
 Sigma-Delta ADC (Discrete-Time)
Multi-Level
Quantizer
IN OUT
H(z)

clock
DAC

 Oversampled input
- Clock rate is much higher than bandwidth of input
signal
 Noise shaped quantization noise
- Uses similar concepts as Sigma-Delta DAC considered
in Lecture 22
 Leads to high effective precision despite having a coarse
quantizer
M.H. Perrott 9
 Sigma-Delta ADC (Continuous-Time)

Multi-Level
Quantizer
IN OUT
H(s)

clock
DAC

 Similar to Discrete-Time, but important differences

- Sampler occurs after the filtering
 Allows removal of high frequency noise before sampling
- Only the quantizer and DAC need to settle during each
sample
 Allows higher speed

M.H. Perrott 10
 Time-to-Digital Conversion

Delay Delay Delay

tin(t)

D Q D Q D Q

Reg Reg Reg

e[k]
clk(t)

Delay TDC
tin(t) Time e[k]
tin(t) 1 Characteristic
-to-
1 Digital
1 e[k]
0 e[k]
0 clk(t)
clk(t)
Δt Δt
 Quantization in time achieved with purely digital gates
- Easy implementation, resolution improving with Moore’s law
How can we leverage this for quantizing an analog voltage? 11
M.H. Perrott
 Adding Voltage-to-Time Conversion

in(t) Voltage tin(t) Time out[k]

-to- -to-
Time Digital

clk(t)
Naraghi, Courcy, Flynn, ISSCC 2009

 Analog voltage is converted into edge times

- Time-to-digital converter then turns the edge times into
digitized values
 Key issues
- Non-uniform sampling
- Noise, nonlinearity
Is there a simple implementation for
the Voltage-to-Time Converter?
M.H. Perrott 12
 A Highly Digital ADC Implementation
Ring Oscillator Delay Delay Delay
tin(t)
Vtune(t)
in(t)
tin(t)
D Q D Q D Q

Reg Reg Reg

out[k]
clk(t)

in(t) Voltage tin(t) Time out[k]

-to- -to-
Time Digital

clk(t)

 A voltage-controlled ring oscillator offers a simple

voltage-to-time structure
- Non-uniform sampling is still an issue
We can further simplify this implementation and
lower the impact of non-uniform sampling 13
M.H. Perrott
 Making Use of the Ring Oscillator Delay Cells
Ring Oscillator Delay Delay Delay
tin(t)
Vtune(t)
in(t)
tin(t)
D Q D Q D Q

Reg Reg Reg

out[k]
clk(t)

Ring Oscillator
tin1(t) tin2(t) tin3(t)
Vtune(t)
in(t)
D Q D Q D Q
tin3(t)
Reg Reg Reg
tin2(t) out[k]
tin1(t) clk(t)

 Utilize all ring oscillator outputs and remove TDC delays

- Simpler implementation
 TDC output now samples/quantizes phase state of oscillator
M.H. Perrott 14
 Improving Non-Uniform Sampling Behavior
Ring Oscillator Delay Delay Delay
tin(t)
Vtune(t)
in(t)
tin(t)
D Q D Q D Q

Reg Reg Reg

out[k]
clk(t)

Ring Oscillator
tin1(t) tin2(t) tin3(t)
Vtune(t)
in(t)
D Q D Q D Q
tin3(t)
Reg Reg Reg
tin2(t) out[k]
tin1(t) clk(t)

 Oscillator edges correspond to a sample window of the input

 Sampling the oscillator phase state yields sample windows
that are much more closely aligned to the TDC clk 15
M.H. Perrott
 Multi-Phase Ring Oscillator Based Quantizer
Vtune N-Stage Ring Oscillator
Vtune N-Stage Ring Oscillator

Ref N-bit Register

Sample 1

N-bit Register

Sample 2
N XOR Gates

Adder

Out Sample 3

 Adjustment of Vtune changes

how many delay cells are visited Sample 4
by edges per Ref clock period
- Quantizer output corresponds to the number of delay cells
that experience a transition in a given Ref clock period 16
M.H. Perrott
 More Details …
Vtune N-Stage Ring Oscillator Example: Progression of
9-Stage Ring Oscillator Values
Vtune

Ref
Ref N-bit Register
010110101 110101010 101010010
N-bit Register
101010101 010110101 110101010
N XOR Gates
111100000 100011111 011111000
Adder

Out Out = 4 Out = 6 Out = 5

 Choose large enough number of stages, N, such that

transitions never cycle through a given stage more than once
per Ref clock period
- Assume a high Ref clock frequency (i.e., 1 GHz)
 XOR operation on current and previous samples provides
transition count
M.H. Perrott 17
 A First Step Toward Modeling
Vtune N-Stage Ring Oscillator First Order
VCO Quantizer Difference
Vtune Out
Quantized 1- z-1
VCO Phase
Ref
Ref N-bit Register Sampler
T
Wismar, Wisland,
N-bit Register
Andreani, ESSCIRC 2006
First Order
N XOR Gates
Difference
100011111 011111000
Adder

Out Quantized Out = 6 Out = 5

VCO Frequency

 VCO provides quantization, register provides sampling

- Model as separate blocks for convenience
 XOR operation on current and previous samples
corresponds to a first order difference operation
- Extracts VCO frequency from the sampled VCO phase signal
M.H. Perrott 18
 Corresponding Frequency Domain Model
First Order
 VCO modeled as integrator
Vtune
VCO Quantizer Difference
and Kv nonlinearity Out
1- z-1
 Sampling of VCO phase Ref
modeled as scale factor of 1/T
 Quantizer modeled as
T

addition of quantization noise

 Key non-idealities:
- VCO K nonlinearity
v
- VCO noise VCO
Noise
Quantization
Noise
Output
Noise
- Quantization noise -20 dB/dec 20 dB/dec

f f f
Vtune Out
2πKv 1
1- z-1
s T
VCO Kv VCO Sampler First Order
Nonlinearity Difference
M.H. Perrott 19
 Example Design Point for Illustration
Simulated ADC Output Spectrum
60  Ref clk: 1/T = 1 GHz
40  31 stage ring oscillator
20
- Nominal delay per
stage: 65 ps
Amplitude (dB)

0
 KVCO = 500 MHz/V
-20 - 5% linearity
-40  VCO noise: -100 dBc/Hz
-60
at 10 MHz offset

-80
VCO Quantization Output
-100 5 6 7 8
Noise Noise Noise
10 10 10 10 -20 dB/dec 20 dB/dec
Frequency (Hz)
f f f
Vtune Out
2πKv 1
1- z-1
s T
VCO Kv VCO Sampler First Order
Nonlinearity Difference 20
M.H. Perrott
 SNR/SNDR Calculations with 20 MHz Bandwidth
Simulated ADC Output Spectrum
60 Conditions SNDR
40
Ideal 68.2 dB
20
VCO Thermal
Amplitude (dB)

0 65.4 dB
Noise
-20
VCO Thermal
-40 32.2 dB
+ Nonlinearity
-60

-80
VCO Quantization Output
-100 5 6 7 8
Noise Noise Noise
10 10 10 10 -20 dB/dec 20 dB/dec
Frequency (Hz)
f f f

VCO Kv nonlinearity is Vtune

2πKv 1 Out
1- z-1
the key performance s T
bottleneck VCO Kv VCO Sampler First Order
Nonlinearity Difference 21
M.H. Perrott
 Classical Analog Versus VCO-based Quantization
N-Stage N-Stage Ring Oscillator
Resistor IN
Ladder Pre-Amp Comparator

A 0
Vdd

A 1 Buffer
Vdd
N CLK
N-bit Register
A 1

IN CLK 0 1 1 1 0

 Much more digital implementation

 Offset and mismatch is not of critical concern
 Metastability behavior is potentially improved
 Improved SNR due to quantization noise shaping
Implementation is high speed, low power, low area
M.H. Perrott 22
 Key Performance Issues: Nonlinearity and Noise

 Very hard to build a Vtune N-Stage Ring Oscillator

simple ring oscillator

with linear Kv
Ref
N-bit Register
 Noise floor set by VCO
phase noise is typically N-bit Register

higher than for analog

amplifiers at same power N XOR Gates

dissipation
Adder

Out
Quantization Noise
20 dB/dec
VCO Noise
f
Vtune Out

VCO Kv Nonlinearity 23
M.H. Perrott
 Feedback Is Our Friend
Ref (1 GHz) Iwata, Sakimura, TCAS II, 1999
In
Naiknaware, Tang, Fiez, TCAS II, 2000
Gain and Vtune VCO-based Out
Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out
DAC

Ref
N-bit Register

 Combining feedback with

front end gain acts to N-bit Register

suppress impact of quantizer N XOR Gates

noise and nonlinearity
- Scale factor from input to Adder
output is also better controlled
- Structure is a continuous-time Sigma-Delta ADC Out

 Issue: must achieve a highly linear DAC structure

M.H. Perrott
- Otherwise, noise folding and other bad things happen … 24
 A Closer Look at the DAC Implementation
Ref (1 GHz)

In Gain and Vtune VCO-based Out

Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out
DAC

Ref
N-bit Register

N-bit Register

 Consider direct
N XOR Gates
connection of the
quantizer output to a 1-Bit DACs
series of 1-bit DACs
- Add the DAC outputs
together
DAC Out

What is so special about doing this?

M.H. Perrott 25
 Recall that Ring Oscillator Offers Implicit Barrel Shifting
Ref (1 GHz)

In Gain and Vtune VCO-based Out

Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out
DAC
Sample 1

Sample 2
 Barrel shifting
through delay
Sample 3
elements
- Mismatch between
delay elements is Sample 4
first order shaped

M.H. Perrott 26
 Implicit Barrel Shifting Applied to DAC Elements
Ref (1 GHz)
Miller, US Patent (2004)
In Gain and Vtune VCO-based Out
Filtering Quantizer
Vtune N-Stage Ring Oscillator

DAC Out Implicit

DAC Barrel-Shift
DEM
Ref
N-bit Register

N-bit Register
Ref
N XOR Gates
111100000 100011111 011111000
1-Bit DACs

 Barrel shifting action of

quantizer transferred to
1-bit DAC elements DAC Out

M.H. Perrott
- Acts to shape DAC mismatch and linearize its behavior 27
 First Generation Prototype
973 MHz

VIN
Vtune VCO-based D OUT Barrel-Shift
Quantizer & DEM
VA VB

Quantizer Element
Barrel-Shift
DEM

31
IDAC1 IDAC2

Sample
 Second order dynamics achieved with only one op-amp
- Op-amp forms one integrator
- I and passive network form the other (lossy) integrator
dac1
- Minor loop feedback compensates delay through quantizer
 Third order noise shaping is achieved!

M.H. Perrott
- VCO-based quantizer adds an extra order of noise shaping 28
 Custom IC Implementing the Prototype
973 MHz
Straayer, Perrott
VIN VLSI 2007
Vtune VCO-based D OUT
VA Quantizer &
VB Barrel-Shift
DEM

31
IDAC1 IDAC2

 0.13u CMOS
 Power: 40 mW
 Active area: 700u X 700u
 Peak SNDR: 67 dB (20 MHz BW)
 Efficiency: 0.5 pJ/conv. step
M.H. Perrott 29
 Measured Spectrum From Prototype
Normalized FFT, FIN = 1 MHz
60
20 MHz Input Bandwidth
40 SNR 66.4 dB
SNDR 65.7 dB
20
Amplitude (dB)

0
Distortion
-20

-40

-60

-80
0.1 1 10 100 1000
Frequency (MHz) 30
M.H. Perrott
 Measured SNR/SNDR Vs. Input Amplitude (20 MHz BW)
SNR/SNDR vs. Amplitude, FIN = 1 MHz
90
80
SNR
70 SNDR Kv nonlinearity
60
limits SNDR to
SNR/SNDR (dB)

67 dB
50

40
30
20

10
0

-10
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
Amplitude (dBFS) 31
M.H. Perrott
 Summary

 ADC design is an active area of research

- Many topologies possible
- Much innovation is still ongoing, especially as new CMOS
fabrication processes are introduced
 Key topologies
- Flash
- SAR
- Pipeline
- Sigma-Delta
 VCO-based ADCs are a new area of interest
- Take advantage of high speed of new CMOS processes
- Leverage digital circuits
- Can achieve good performance, but innovation still needed
M.H. Perrott 32
 Analysis and Design of Analog Integrated Circuits
Lecture 24

Bipolar Devices and Their Applications

Michael H. Perrott
April 29, 2012

Copyright © 2012 by Michael H. Perrott

All rights reserved.

M.H. Perrott
 Introducing Bipolar Devices (Within CMOS Processes)

CMOS IB Bipolar
ID
IC
VGS VBE
G
VD N+
S D C B E B C VCE
N+
P-
N+ N+ P+ P- P+ N+
N+

D C
Note: define Ae as
G B area of emitter
S E

 Modern CMOS processes often offer Deep NWELL

- Allows a buried N+ layer to be implanted
- Vertical NPN bipolar device can be achieved
This lecture will discuss modeling and applications
of such “parasitic” bipolar devices
M.H. Perrott 2
 Collector Current as a Function of Vbe

Ic Vce > 200mV

Ic
c
b
Q1
ΔIc
Vbe e Ic_op gm =
ΔVbe
Vbe_op
Vbe
Bipolar Vbe_op

 For 0 < Vce < 200mV, Vbe > 0, device is in saturation

- This region of operation is typically avoided
 For Vce > 200mV, Vbe > 0, device is in forward active mode
Ic = βIb
Ic = AeIs(eVbe/Vt − 1), where Vt = kT /q
δIc Ic
⇒ gm = ≈
δVbe VT
M.H. Perrott 3
 Thevenin Modeling of Bipolar Device

Hybrid-π Model Key Small-Signal Parameters

IC = βIB RC
RB IB IC Parameter Forward Active Definition
b c
IC kT
gm Vt = 26mV at 25oC
Rthb rπ gmvbe ro Rthc Vt q
vbe
β
rπ β is Current Gain
gm
e
Rthe
VA
RE ro VA is Early Voltage
IC

Thevenin Resistances Approximation Proposed Small Signal Transistor Model

b c
Rthc= ro (1+gm(rπ RE))
ie
(RB << rπ, RB << RE ) Rthe
IC RC
Rthb vb Avvb α ie Rthc
c Rthc
RB b Rthb= rπ + (β+1)RE
(RC << ro, RE << ro ) e
Rthb e
Rthe Exact Approximation
1 RB 1
RE Rthe= g + Av = Av = 1 (RC<<βro)
m 1+β 1+(1+RC)/(rπ+βro)
(RB+RC << βro ) β
α = (1+RC /Rthc) α = 1 (RC<<Rthc)
β+1

M.H. Perrott 4
 Bipolar Versus CMOS Devices

CMOS Bipolar
D C

G B

S E

 Bipolar has higher gm for a given amount of current

- Useful for high speed applications
 Bipolar has lower 1/f noise and lower offset issues
- Useful for high precision analog
 Bipolar has well defined behavior over a wide
operating range: Ic = AeIs(eVbe/Vt-1)
 Exponential behavior allows analog multipliers and
dividers to be realized using translinear principle
CMOS is the preferred device for low cost,
high density, and high complexity digital circuits
M.H. Perrott 5
 Consider Adding VBE Voltages
I1

Q1 I2
VBE1
Q2
VBE2
 In general
³ ´
Ic = AeIs eVBE /Vt − 1 ≈ AeIseVBE /Vt
µ ¶
Ic
⇒ VBE ≈ Vt ln
AeIs
 Addition of VBE voltages corresponds to multiplication
of collector currents à ! à !
I1 I2
VBE1 + VBE2 = Vt ln + Vt ln
Ae1Is Ae2Is
à !
I1I2
= Vt ln
Ae1Ae2Is2 6
M.H. Perrott
 Consider Subtracting VBE Voltages

I1 I2

Q1 Q2
VBE1 VBE2

 Subtraction of VBE voltages corresponds to division of

collector currents à ! à !
I1 I2
−VBE1 + VBE2 = −Vt ln + Vt ln
Ae1Is Ae2Is
à !
I2 Ae1
= Vt ln
I1 Ae2

Translinear circuits can be built which achieve

multiplication, division, and power-law relationships
(see: http://en.wikipedia.org/wiki/Translinear_circuit)
M.H. Perrott 7
 A Closer Look at Subtracting VBE Voltages

 Subtract VBE of bipolar devices

I2
1
I1 - Different emitter areas/currents
 I 2 Ae1 
Ae2 Ae1 VBE  VBE 2  VBE1  Vt ln  
 I1 Ae 2 
VBE2 VBE1
kT  I 2 Ae1 
R ΔVBE  ln  
q  I1 Ae 2 
 Assume VBE varies 0.18mV/°C
- True if (I / I )(A
 1 e1 /Ae2) ~ 10

 In general, we see that VBE is a PTAT voltage source

- PTAT : Proportional to Absolute Temperature
 The current through resistor R is also PTAT
- This ignores changes in the resistance due to temperature 8
M.H. Perrott
 Implementation Details of PTAT Current Source

 Let us walk through various issues and circuit

approaches for realizing our PTAT current source

I2 I1

Ae2 Ae1
Ib2 Ib1
R1 ΔVBE

 Simple diode connection leads to Ic2 ≠ I2

- This leads to I c2 = I2 - Ib2 - Ib1
- But, we want I c2 = I2 so that I2 ≈ Ae2Ise
Vbe2/Vt

M.H. Perrott 9
 NMOS Source Follower Mitigates Base Current Issue

I2 I1
M4
Ae2 Ae1

Ibias R1 ΔVBE

 Simple NMOS source follower allows us to supply

base current without corrupting I2
- If available in the fabrication process, use a Native
NMOS device which has VTH ≈ 0
 Leads to improved headroom (lower VDD possible)
M.H. Perrott 10
 Ratioed Currents Achieved with Current Mirror

W2 W1
L L
I2 I1
M4
Ae2 Ae1

Ibias R1

 We can scale I2 relative to I1 by proper choice of W2/W1

- Cascoding technique can be used to achieve better
current ratio accuracy

M.H. Perrott 11
 PTAT Current Output Is Simple Extension of Mirror

W2 W1 W3
L L L I3
I2 I1
M4
Ae2 Ae1

Ibias R1

à !
W3 W3 ∆VBE β
I3 = I1 =
W1 W1 R1 β+1

 Issue: temperature variability of R1 and 

-R 1 is biggest concern assuming  is large
12
M.H. Perrott
 PTAT Current Output Can Be Converted to Voltage

W2 W1 W3
L L L I3
I2 I1 Vo
M4 R3 ρ 0.18mV/oC
Ae2 Ae1

Temp (oC)
Ibias R1 ΔVBE

à !
W3 ∆VBE β W3 R3
Vo = I3R3 = R3 ≈ ∆VBE
W1 R1 β+1 W1 R1

 Output voltage set by ratio of resistor values R3/R1

- Greatly reduces impact of R variation with temperature 13
M.H. Perrott
 Consider Adding VBE to the PTAT Voltage

W2 W1 W3
L L L I3
I2 I1 Vbg
M4 R3
VR3
Ae2 Ae1

Ibias R1 Ae3
VBE3

W3 R3
Vbg = VR3 + VBE3 ≈ ∆VBE + VBE3
W1 R1

 It turns out that this corresponds to a bandgap circuit

- Proper design leads to stable V o across temperature
14
M.H. Perrott
 Temperature Sensitivity of VBE

W2 W1 W3
L L L I3
I2 I1 Vbg
M4 R3 VBE3
VR3
Ae2 Ae1
-2mV/oC
Ibias R1 Ae3
VBE3 Temp (oC)
W3 R3
Vbg = VR3 + VBE3 ≈ ∆VBE + VBE3
W1 R1

 VBE has opposite temperature sensitivity as VBE

- Recall that V BE is a PTAT voltage (≈ +0.18mV/ºC)
15
M.H. Perrott
 Bandgap Achieved Through Proper Scaling

W2 W1 W3 I3
L L L
(ρ 0.18-2)mV/oC
I2 I1 Vbg
M4 R3
VR3
Ae2 Ae1
Temp (oC)
Ibias R1 Ae3
VBE3

W3 R3
Vbg = VR3 + VBE3 ≈ ∆VBE + VBE3
W1 R1

 Set ratio as W3 R3 2mV /◦C

ρ= = ◦
= 11.11
W1 R1 0.18mV / C
M.H. Perrott 16
 The Brokaw Bandgap Circuit

Assume R3 = R4 ∆VBE
I2 = I1 ≈
R4 R3 I1 = I2 R2

Vbg
I2 I1

Ae2 Ae1
VBE2 Vbg = VR1 + VBE2
ΔVBE R2 Ã !
∆VBE
≈ I2 + R1 + VBE2
R2
VR1 R1 2R1
= ∆VBE + VBE2
R2
 Assuming VBE varies at 0.18mV/ºC, set ratio as
2R1 2mV /◦C
= ◦
= 11.11
R2 0.18mV / C 17
M.H. Perrott
 What if Deep NWELL Is Not Available?
IB NPN Bipolar PNP Bipolar
IC
VBE VEB IB IC
N+ N+ P+

C B E B C VCE B E C
N+ P+ P- P+ N+ N- P+
N+ -
P

C E
Note: define Ae as
B area of emitter B

E C

 Deep NWELL allows an NPN device

 A PNP device is possible without Deep NWELL
- A key constraint is that the collector must be grounded!

M.H. Perrott 18
 Grounded Collector PNP Bandgap Circuit

R1 R3 VR3

Vbg
I1 I2

R2 ΔVEB Vbg = VR3 + VEB1

VEB1
Ae1 Ae2 ∆VEB
= R3 + VEB1
R2
R3
= ∆VEB + VEB1
R2
 Assuming VEB varies at 0.18mV/ºC, set ratio as
R3 2mV /◦C
= ◦
= 11.11
R2 0.18mV / C 19
M.H. Perrott
 Voltage Regulation Using a Bandgap Reference

Vdd

Vbg 1.25V Voltage Vref Voltage Vreg

Bandgap
Scale Regulator

Gnd

 Commonly used in modern integrated circuits

- Rejection of power supply variation and noise
- Variable voltage operation of circuits

M.H. Perrott 20
 Temperature Sensing Using Bipolar Devices

Vbg Vref
Bandgap
ADC Out
Circuit
ΔVBE Vin

 Recall that VBE is a linear function of temperature

kT  I 2 Ae1 
VBE  VBE 2  VBE1  ln  
q  I1 Ae 2 
 We can create an accurate temperature sensor by
comparing VBE to a temperature stable bandgap
reference voltage
- Analog-to-digital converter is used to digitize the
temperature signal
M.H. Perrott 21
 Summary

 CMOS processes offer parasitic bipolar devices

- Deep NWELL option allows both NPN and PNP devices
 We can use the same analysis tools for both bipolar
and CMOS devices
- Hybrid  and Thevenin modeling techniques
 Bipolar devices have very useful properties
- Exponential characteristic over a wide operating range
- Higher g for a given current than CMOS devices
m
- Lower 1/f noise and offset issues than CMOS devices
 Bipolar devices are very useful for certain circuits
- Translinear circuits (for multiplication and division)
- Bandgap voltage references
- Temperature sensors
M.H. Perrott 22