Chameli Devi Group of Institutions

Department of Computer Science &

Information Technology
CSIT404 Computer Organization &
Architecture

Unit-2:

Computer Arithmetic: Addition and Subtraction, Two’s Compliment Representation,

Signed Addition and Subtraction, Multiplication and Division, Booths Algorithm, Division
Operation, Floating-Point Arithmetic Operation, Design of Arithmetic Unit

………………………………………………………………………………………………………………………………………...

INTRODUCTION:

Based on the number system two basic data types are implemented in the computer
system: fixed-point number and floating-point number. In a binary number system, a
number can be represented as an integer or a fraction.
Depending on the design, the hardware can interpret the number as an integer or fraction.
The radix point is never explicitly specified. It is implicited in the design and the hardware
interprets it accordingly.
In integer number, radix point is fixed and assumed to be to the right of the rightmost
digits. As radix point is fixed, the number system is referred to as fixed-point number
system. With fixed point number system we can represent positive or negative integer
numbers.
The floating point number system allows the representation of numbers having both
integer part and fractional part.

Fig.2.1:ALUOperationalUnit

ADDITIONANDSUBTRACTIONOFSIGNEDNUMBERS:

Wecanrelateadditionandsubtractionoperationsofnumbersbythefollowingrelationship:
(±A) - (+B)=(± A)+(-B)and(±A)-(-B)=(±A)+(+B)

Therefore, we can change the subtraction operation to an addition operation by changing

the sign of the subtrahend.
1'SCOMPLEMENTREPRESENTATION:

The1’scomplementofabinarynumberisthenumberthatresultswhenwechangeall ones to
zeros and the zeros to ones.
1’scomplementof (11000100)2.
11000100

00111011

2'SCOMPLEMENTREPRESENTATION:

The2’scomplementisthebinarynumberthatresultswhenweadd1tothe1's Complement. It is given

as
2’s complement = 1’s complement + 1
The2’scomplementformisusedtorepresentnegativenumbers.

1 1 0 0 0 1 0 0

0 0 1 1 1 0 1 1 1’sComplement

+ 1

0 0 1 1 1 1 0 0 2’sComplement

ADDITION/SUBTRACTIONLOGICUNIT:

Figure2.2showshardwaretoimplementintegeradditionandsubtraction.Itconsistsofn
-bit adder, 2’s complement circuit, overflow detector logic circuit, and AVF (overflow flag).
Number a and number b are the two inputs for n-bit adder. For subtraction, the
subtrahend(numberfromBregister)is convertedintoits2's complementformbymaking Add/
Subtract control signal to the logic one. When Add/Subtract control signal is one, all bits of
number b are complemented, and carry zero (C 0) is set to one. Therefore n-bitadder gives
result as R = a + b’ + 1, where b’ +1 represents 2's complement of number b.

Fig.2.2:HardwareforIntegerAdditionandSubtraction
ADDITIONANDSUBTRACTIONALGORITHM& FLOWCHART:

Therearethreewaysofrepresentingnegativefixed-pointbinarynumbers:

 Signedmagnitude
 Signed-1’scomplement
 Signed-2'scomplement

Most computers use the signed-2's complement representation when performing

arithmeticoperationswithintegers.Forfloating-pointoperations,mostcomputersusethe
signed-magnitude representation for the mantissa.

AdditionandSubtractionwithSignedMagnitudeData

The representation of numbers in signed-magnitude is familiar because it is used in

everyday arithmetic calculations. We designate the magnitude of the two numbers by A
and B. When the signed numbers are added or subtracted, we find that there are eight
different conditions to consider, depending on the sign of the numbers and the operation
performed. These conditions are listed in the first column of table 2.1. The other columns
in the table show the actual operation to be performed with the magnitude of thenumbers.
The last column is needed to prevent a negative zero. In other words, when two equal
numbers are subtracted, the result should be +0 not -0.

Table2.1:AdditionandSubtractionofSignedMagnitudeNumbers

SubtractMagnitudes

Operation AddMagnitudes WhenA>B WhenA<B WhenA=B

(+A)+(+B) +(A+B)
(+A)+(-B) +(A-B) -(B-A) +(A-B)
(-A)+(+B) -(A-B) +(B-A) +(A-B)
(-A)+(-B) -(A+B)
(+A)-(+B) +(A-B) -(B-A) +(A-B)
(+A)-(-B) +(A+B)
(-A)-(+B) -(A+B)
(-A)-(-B) -(A-B) +(B-A) +(A-B)

HardwareImplementation

To implement the two arithmetic operations with hardware, it is first necessary that the
two numbers be stored in registers. Let A and B be two registers that hold the magnitudes
of the numbers, and ASand BSbe two flip flops that hold the corresponding signs. The result
of the operation may be transferred to a third register. Consider now the hardware
implementation of the algorithms:

 First,aparalleladderis neededtoperformthe micro-operationA+B.

 Second,acomparatorcircuitisneededtoestablishifA>B,A=B,orA<B.
  Third,twoparallelsubtractorcircuitsareneededtoperformthemicro-operations A-B
and B-A.

The sign relationship can be determined from an exclusive-OR gate with A Sand BSas
inputs. Subtraction can be accomplished by means of complement and add. Second, the
result of a comparison can be determined from the end carry after the subtraction. Careful
investigation ofthe alternatives reveals that the use of2's complement forsubtraction and
comparison is an efficient procedure that requires only an adder and a complementor.

Fig.2.3:FlowchartofAdd&SubtractOperation

The twosigns ASandBSare comparedbyan exclusive-ORgate. Ifthe output ofthe gate is 0,

thesignsareidentical;ifitis1thensignsare different. Foranaddoperation,identicalsigns
indicate that the magnitudes be added. For a subtract operation, different signs indicate
thatthemagnitudesbeadded. Themagnitudesare addedwithamicro-operationEAA+B,
where EA is a register that combines E and A. The carry in E after the addition constitutes
an overflow if it is equal to1. The value of E is transferred into the add-overflow flip-flop
AVF.

The two magnitudes are subtracted if the signs are different for an add operation or
identical for a subtract operation. The magnitudes are subtracted by adding A to the 2’s
complementofB.NooverflowcanoccurifthenumbersaresubtractedsoAVFisclearedto
0. A=1in E indicates that A>=B and the number in A is the correct result. If this number is
zero,thesignAsmustbemadepositivetoavoidanegativezero.A=0inEindicatesthat
A<B. For this case, it is necessary to take the 2's complement of the value in A. This
operation can be done with one micro-operation A<-Ã + 1. Here, we assume that the A
register has circuit for micro-operations complement and increment, so the 2'scomplement
is obtained from these two micro-operations.

In other paths of the flowchart, the sign of the result is the same as the sign of A, so no
change in ASis required. However, when A<B, the sign of the result is the complement of the
original sign of A. It is then necessary to complement A Sto obtain the correct sign. The final
result is found in register A and its sign in AS.

AdditionandSubtractionwithSigned-2'sComplement Data

The signed 2’s complement representation ofnumbers together with arithmetic algorithms
for addition and subtraction. The leftmost bit of a binary number represents the sign bit: 0
for positive and 1 for negative. If the sign bit is 1 the entire number is represented in 2's
complement form. Thus +33 are represented as 00100001 and -33 as 11011111. Note that
11011111 is the 2’s complement of 00100001 and vice versa.

Fig.2.4:HardwareforSigned2’sComplementAdditionandSubtraction

The addition of two numbers in signed 2's complement form consists of adding the
numbers with the sign bits treated the same as the other bits of the number. A carry out of
the sign bit position is discarded.

The subtraction consists of first taking the 2’s complement of the subtrahend and then
adding it to the minuend. When two numbers of n digits each are added and the sum
occupies n+ 1 digit, we say that an overflow occurred. An overflow can be detected by
inspecting the last two carries out of the addition.

The algorithm for adding and subtracting two binary numbers in signed- 2’s complement
representation is shown in the flowchart of Figure 2.5. The sum is obtained by adding the
contents of AC and BR (including their sign bits).

The overflow bit V is set to 1 if the Exclusive-OR of the last two carries is l, and it is cleared
to0otherwise.ThesubtractionoperationisaccomplishedbyaddingthecontentofACto
the 2’s complement of BR. Taking the 2’s complement of BR has the effect of changing a
positive number to negative, and vice versa.

Fig.2.5:AlgorithmforAddingandSubtractingNumbersinSigned-2'sComplement form
Representation
An overflow must be checked during this operation because the two numbers added could
have same sign. The programmer must realize that if an overflow occurs, there will be an
erroneous result in the AC register. Comparing this algorithm with its signed-magnitude
counterpart, we note that it is much simpler to add and subtract numbers if negative
numbers are maintained in signed 2’s complement representation. For this reason most
computers adopt this representation over the more familiar signed magnitude.

MULTIPLICATIONALGORITHM&FLOWCHART:

As shown in Figure 2.6 initially, the multiplicand is in B and the multiplier in Q. Their
corresponding signs are in Bs and Qs respectively. The signs are compared, and both Asand
Qs are set to correspond to sign the product since a double length product will be stored in
register A & Q. Registers A and E are cleared and sequence counter SC is set to a number
equal to the number of bits of the multiplier.

Fig.2.6:FlowchartoftheHardwareMultiplyAlgorithm
We are assuming here that operands are transferred to registers from a memory unit that
has words of n bits. Since operand must be stored with its sign, one bit of the word will be
occupied by the sign and the magnitude will consist of n-1 bits.

After the initialization, the low order bit of the multiplier in Q is tested. If it is 1 the
multiplicand in B is added to the present partial product in A. If it is 0, nothing is done.
Register EAQ is then shifted once to the right from the new partial product. The sequence
counter is decremented by 1 and its new value is checked. If it is not equal to zero, the
process is repeated and a new partial product is formed. The process stops when SC= 0.
Note that the partial product formed in A is shifted into Q one bit at a time and eventually
replaces the multiplier. The final product is available in both A and Q, with A holding the
most significant bits and Q holding the least significant bits.

Table2.2:BinaryMultiplicationExample

MultiplicandB=10111 E A Q SC
MultiplierinQ Qn=1; 0 00000 10011 101
add B 101111
Firstpartialproduct 0 0111
Shift right EAQ 0 01011 11001 100
Qn=1; add B 10111
Secondpartialproduct Shift 1 00010
right EAQ 0 10001 01100 011
Qn=0;shiftrightEAQ 0 01000 10110 010
Qn=0;shiftrightEAQ 0 00100 01011 001
Qn=1; add B 10111
Fifthpartialproduct 0 11011
Shift right EAQ 0 01101 10101 000
FinalproductinAQ=0110110101

BoothMultiplicationAlgorithm

Booth algorithm gives a procedure for multiplying binary integers in signed2’scomplement

representation.

Booth algorithm requires examination of the multiplier bits and shifting of the partial
product. Prior to the shifting, the multiplicand may be added to the partial product,
subtracted from the partial product, or left unchanged according to the following rules:

 The multiplicand is subtracted from the partial product upon encountering the first
least significant in a string of 1's in the multiplier.
 Themultiplicandisaddedtothepartialproductuponencounteringthefirst0 (provided
that there was a previous 1) in a string of 0’s in the multiplier.
 Thepartialproductdoesnotchangewhenthemultiplierbitisidenticaltothe previous
multiplier bit.
 Fig.2.7:FlowchartforBoothAlgorithm
The hardware implementation of the Booth algorithm requires the register configuration
shown in Figure 2.7. This is similarto Figure 2.6, (multiply)except that the sign bits are not
separated from the rest of the register. To show this difference, we rename registers A, B,
andQasAC,BR,andQR,ifthetwobitsareequalto10,itmeansthatthefirst1inastringof 1's has
been encountered. This requires a subtraction of the multiplicand from the partial product
in AC. If the two bits are equal to 0 it means that the first 0 in a string of 0's has been
encountered. This requires the addition of the multiplicand to the partial product in AC.
When the two bits are equal, the partial product does not change. An overflow cannot occur
because the addition and subtraction of the multiplicand follow each other. As a
consequence, the two numbers that are added always have opposite sign, a condition that
excludes an overflow. The next step is to shift right the partial product and the multiplier
(including bit Qn +1). This is an arithmetic shift right (ashr) operation which shifts AC and
QR to the right and leaves the sign bit in AC unchanged. The sequence counter is
decremented and the computational loop is repeated n times.
 Table2.3:BoothMultiplicationExample

BR=10111
Qn Qn+1 BR+1= 01001 AC QR Qn+1 SC
Initial 00000 10011 0 101
1 0 SubtractBR 010010
1001
ashr 00100 11001 1 100
1 1 ashr 00010 01100 1 011
0 1 AddBR 10111
11001
ashr 11100 10110 0 010
0 0 ashr 11110 01011 0 001
1 0 Subtract BR 01001
00111
ashr 00011 10101 1 000

DIVISIONALGORITHM&FLOWCHART:

The reciprocal operation of multiply is divide, an operation that is even less frequent and
even more quirky.It even offers the opportunity to perform a mathematically invalid
operation dividing by 0.
Example:

When the division is implemented in a digital computer, it is convenient to change the

process slightly. Instead of shifting the divisor to the right, the dividend, or partial
remainder, is shifted to the left, thus leaving the two numbers in the required relative
position. Subtraction may be achieved by adding A to the 2’s complement of B. The
information about the relative magnitudes is then available from the end carry.
The hardware for implementing the division operation is identical to that required for
multiplication and consists of the component shown above multiplication.
 Fig.2.8:HardwareImplementationofDivision
InFigure2.9registerEAQisnowshiftedtothe leftwith0insertedintoQnandtheprevious value of
E lost. The divisor is stored in the B register and the double-length dividend is stored in
registers A and Q . The dividend is shifted to the left and the divisor is subtracted by adding
its 2's complement value. The information about the relative magnitude is available in E. If
E=1 it signifies that A>=B. A quotient bit 1 is inserted into Qn and the partial remainder is
shifted to the left to repeat the process. If E= 0, it signifies that A< B so the quotient in Qn.

Fig.2.9:FlowchartforDivisionAlgorithm

ThehardwaredividealgorithmisshownintheflowchartofFigure2.9. ThedividendisinA and Q

and the divisor in B.The sign of the result is transferred into Q Sto be part of the quotient. A
constant is set into the sequence counter SC to specify thenumber of bits in the quotient. As
in multiplication, we assume that operands are transferred to registers from a
memoryunitthathaswordsofnbits.Sinceanoperandmustbestoredwithitssign,one
bit of the word will be occupied by the sign and the magnitude will consist of n-1 bits. A
divide overflow condition is tested by subtracting the divisor in B from half of the bits of
the dividend stored in A. If A > B, the divide overflow flip-flop DVF is set and the operation
is terminated prematurely. If A <B, no divide overflow occurs so the value of the dividendis
restored by adding B to A.
Table2.4:DivisionAlgorithmExample

Divisor B=10001, B+1=01111

E A Q SC
Dividend: 01110 00000 5
shlEAQ 0 11100 00000
Add B+1 01111
E=1 1 01011
SetQn=1 1 01011 00011 4
shlEAQ 0 10110 00010
Add B+1 01111
E=1 1 00101
SetQn=1 1 00101 00011 3
shlEAQ 0 01010 00110
Add B+1 01111
E=0:leaveQn=0 0 11001 00110
AddB 10001 2
Restore reminder 1 01010 00110
shlEAQ 1 10100
Add B+1 0 01111
E=1 00011 01101 1
SetQn=1 00011 11010
shlEAQ 00110
Add B+1 01111
E=0:leaveQn=0 0 10101 11010
AddB 10001 10001
Restore reminder 1 00110 11010 0
NeglectE
ReminderinA: 00110
QuotientinQ: 11010

FLOATINGPOINTREPRESENTATION:
To accommodate very large integers and very small fractions, a computer must be able to
represent numbers andoperate on them in sucha waythat the position ofthe binarypoint is
variable and is automatically adjusted as computation proceeds.
In this case, the binary point is said to float, and the numbers are called floating-point
numbers. The floating-point representation has three fields: sign, significant digits and
exponent.
Torepresentthenumber111101.1000110infloating-pointformat,thefirstbinarypointis
shifted to right of the first bit and the number is multiplied by the correct scaling factor to
get the same value. The number is said to be in the normalized form and is given as shown
in the below format.
 111101.1000110---1.11101100110 x25<------------ Exponent
Significantdigits ScalingFactor

Itisimportanttonotethatthebaseinthescalingfactorisfixed2.Thestringofthe significant digits is

commonly known as mantissa. In the above example:

Sign=0 Mantissa=11101100110 Exponent=5

Infloatingpointnumbers, biasvalueisaddedtothetrueexponent. Thissolvestheproblem of

representation of negative exponent.

Example:Represent(1259.125)10insingleanddoubleprecisionformat. Solution:

Step 1: Convert decimal number in binary format

IntegerPart:

Q R
16 1259 11 B LSD
16 78 14 E
16 4 4 4 MSD
0

(1259)10=(4EB)16

4 E B HexNumber
0 1 0 0 1 1 1 0 1 0 1 1 BinaryNumber

FractionalPart:

Fraction Base Product

0.125 x 2 0.25 0

0.25 x 2 0.50 0

0.50 x 2 1.00 1

(1259)10=(10011101011)2 and (0.125)10=(0.001)2

Binarynumber=10011101011+0.001= 10011101011.001
Step 2: Normalize the number
10011101011.001=1.0011101011001x210
Step3:Singleprecisionrepresentation
For a given number S = 0, E = 10 and M = 0011101011001 Bias for single precision format
is - 127
E'=E+127=10+ 127=13710=100010012
Numberinsingleprecisionformatisgivenas
Step4:Doubleprecisionrepresentation.Foragivennumber S =
0, E = 10, and M = 0011101011001
Biasfordoubleprecisionformatis=1023
E'=E+1023= 10+1023=103310=100000010012
Numberindoubleprecisionformatisgivenas

DESIGNOFARITHMETIC UNIT:
ALUisresponsibletoperformtheoperationinthecomputer.Thebasicoperationsare implemented
in the hardware level. ALU is having a collection of two types of operations:

ArithmeticOperations(ADD,SUB,MUL,DIV)
Logical Operations (AND, OR, NOT, EX-OR)
Consider an ALU having 4 arithmetic operations and 4 logical operations. To identify any
one of these four logical operations or four arithmetic operations, two control lines are
needed. Also to identify any one of these two groups- arithmetic or logical, another control
line isneeded.So, withthe help ofthreecontrollines,anyoneoftheseeight operationscan be
identified. Consider an ALU as having four arithmetic operations: Addition, Subtraction,
Multiplication, and Division. Also, consider that the ALU is having four logical operations:
OR, AND, NOT & EX-OR.
We need three control lines to identify any one of these operations. The input combination
of these control lines are shown in Table 2.5: Control line C 2is used to identify the group:
logical or arithmetic, i.e. C2=0: arithmetic operation, C2=1:logical operation. Control lines
C0and C1are used to identify any one of the four operations in a group. One possible
combination is given here:
 Table2.5:OperationIdentificationin ALU
C1 C0 ArithmeticC2=0 LogicalC2=1
0 0 Addition OR
0 1 Subtraction AND
1 0 Multiplication NOT
1 1 Division EX-OR

Figure 2.10 shows the block diagram of ALU in which the ALU has got two input registers
named as A and B and one output storage register, named as C. It performs the operation
as:
C=AopB
The input data are stored in A and B, and according to the operation specified in thecontrol
lines, the ALU performs the operation and puts the result in register C.
For example, if the contents of controls lines are, 000, then the decoder enables the
addition operation and it activates the adder circuit and the addition operation is
performed on the data that are available in storage register A and B. After the completionof
the operation, the result is stored in register C.

Fig.2.10:BlockDiagramofALU Design