Unit-IV

Computer Arithmetic: Introduction, Addition and Subtraction,

Multiplication Algorithms, Division Algorithms

Input-Output Organization: Peripheral Devices, Input-Output

Interface, Asynchronous data transfer, Modes of Transfer, Priority
Interrupt, Direct memory Access, Input –Output Processor (IOP).
COMPUTER ARITHMETIC
Introduction:

Data is manipulated by using the arithmetic instructions in digital

computers. Data is manipulated to produce results necessary to give solution
for the computation problems.
The Addition, subtraction, multiplication and division are the four basic arithmetic
operations.
Using these operations other arithmetic functions can be formulated and scientific
problems can be solved by numerical analysis methods.
Arithmetic Processor:
• It is the part of a processor unit that executes arithmetic operations.
• The arithmetic instructions definitions specify the data type that should be
present in the registers used .
• The arithmetic instruction may specify binary or decimal data and in
each case the data may be in fixed-point or floating point form.
• Fixed point numbers may represent integers or fractions.
• The negative numbers may be in signed magnitude or signed-2’s
complement representation.
• The arithmetic processor is very simple if only a binary fixed point
add instruction is included.
• It would be more complicated if it includes all four arithmetic operations for
binary and decimal data in fixed and floating point representations.
Algorithm
• Algorithm can be defined as a finite number of well defined procedural
steps to solve a problem.
 • Usually, an algorithm will contain a number of procedural steps which are
dependent on results of previous steps.
• A convenient method for presenting an algorithm is a flowchart
whichconsists of rectangular and diamond –shaped boxes.
• The computational steps are specified in the rectangular boxes and
thedecision steps are indicated inside diamond-shaped boxes from which 2
or more alternate path emerge
Addition and Subtraction:
There are three ways of representing negative fixed point binary numbers:
1. Signed-magnitude representation ---- used for the representation of mantissa for
floating point operations by most computers.
2. Signed-1’s complement
3. Signed -2’s complement—Most computers use this form for performing
arithmetic operation with integers.
Addition and subtraction algorithm for signed-magnitude data:
The representation of numbers in signed-magnitude is familiar because it is used in
arithmetic calculations.
• Let the magnitude of two numbers be A & B.
• When signed numbers are added or subtracted, there are 4 different
conditions to be considered for each addition and subtraction depending on
the sign of the numbers.
• The conditions are listed in the table below. The table shows the operation to
be performed with magnitude(addition or subtraction) are indicated for
different conditions
 • The last column is needed to prevent a negative zero. In other words, when
two equal numbers are subtracted, the result should be +0 not -0.
• The algorithm for addition and subtraction ( from the table above):
Addition Algorithm:
• When the signs of A and B are identical, add two magnitudes and attach the
sign of A to the result.
• When the sign of A and B are different, compare the magnitudes and
subtract the smaller number from the larger.
• Choose the sign of the result to be the same as A if A>B or the complement
of sign of A if A < B.
• If the two magnitudes are equal, subtract B from A and make the sign of the
result positive.
Subtraction Algorithm:
• When the signs of A and B are different, add two magnitudes and attach the
sign of A to the result.
 • When the sign of A and B are identical, compare the magnitudes and
subtract the smaller number from the larger.
• Choose the sign of the result to be the same as A if A>B or the complement
of sign of A if A < B.
• If the two magnitudes are equal, subtract B from A and make the sign of the
result positive.
Hardware Implementation:
• Let A and B are two registers that hold the numbers. AS and BS are 2, flip-
flops that hold sign of corresponding numbers.
• The result is stored in A and AS and thus they form Accumulator register.
• We need to perform micro operation, A+ B and hence a parallel adder is
required.
• A comparator is needed to establish if A> B, A=B, or A=B, or A<B
• We need to perform micro operations A-B and B-A and hence two parallel
subtractor are required.
• An exclusive OR gate can be used to determine the sign relationship, that is,
equal or not.
• Thus the hardware components required are a magnitude comparator, an
adder, and two subtractors
Reduction of hardware by using different procedure:
• We know subtraction can be done by complement and add.
• The result of comparison can be determined from the end carry after the
subtraction.
• We find an adder and a complementer can do subtraction and comparison if
2’s complement is used for subtraction.
• AVF Add overflow flip flop. It hold the overflow bit when A & B are added.
• Flip flop E —Output carry is transferred to E. It can be checked to see the
relative magnitudes of the two numbers.
• A-B = A +( -B )= Adding A and 2’s complement of B.
• The A register provides other micro operations that may be needed when
the sequence of steps in the algorithm is specified.
• The complementer passes the contents of B or the complement of B to the
Parallel Adder depending on the state of the mode control M.
• It consists of EX-OR gates and the parallel adder consists of full adder
circuits.
• The M(Mode Control) signal is also applied to the input carry of the adder.
When input carry M=0, the sum of full adder is A +B.
• When M=1, S = A + B’ +1= A – B
Hardware algorithm: Flow Chart for Add and Subtract operations:

• The EX-OR gate provides 0 as output when the signs are identical. It is
1 when the signs are different.
• A + B is computed for the following and the sum is stored in EA:
1. When the signs are same and addition operation is required.
2. When the signs are different and subtract operation is required.
• The carry in E after addition indicates an overflow if it is 1 and it
is transferred to AVF, the add overflow flag
• A-B = A+ B’+1 computed for the following:
• 1. When the signs are different and addition operation is required.
 • 2. When the signs are same and subtract operation is required. No
overflow can occur if the numbers are subtracted and hence AVF is
cleared to Zero.
• A 1 in E indicates that A ≥ B and the number in A is the correct result.
If this number in A is zero, the sign AS must be made positive to avoid a
negative zero.
• A 0 in E indicates that A< B. For this case it is necessary to take the
2’s complement of the value in A.
• In the algorithm shown in flow chart, it is assumed that A register
has circuits for micro operations complement and increment.
• Hence two complement of value in A is obtained in 2, micro operations..
• In other paths of the flow chart, the sign of the result is the same as the
sign of A, so no change in AS is required.
• However, when A < B, the sign of the result is the complement
of original sign of A.
• Hence the complement of AS stored in AS.
• Final Result: As and A

Addition and Subtraction with signed-2’s complement Data

• The addition of two numbers in signed-2's complement form consists of
adding the numbers with the sign bits treated the same as the other bits of the
number.
• A carry-out of the sign-bit position is discarded.
• The subtraction consists of first taking the 2's complement of the subtrahend
and then adding it to the minuend.
• The register configuration for the hardware implementation is shown in
Figure below.
Hardware implementation of signed 2’s complement for addition/subtraction
• Here the sign bits are not separated from the registers and named it as
AC(Accumulator) and the B register(BR)
• The leftmost bit in AC and BR represents the sign bits of the numbers.
• The two sign bits are added or subtracted together with the other bits in the
complementer and parallel adder.
• The overflow flip-flop V is set to1 if there is an overflow.
• The output of the carry in this case is discarded.
• The algorithm for adding and subtracting two binary numbers in signed2's
complement representation is shown in the flow chart below

Algorithm for adding and subtracting numbers in 2’s

complement form:
 Algorithm for adding and subtracting numbers in 2’s complement form
• The sum is obtained by adding the contents of AC and BR (including their
sign bits).
• The overflow bit V is set to 1 if the exclusive-OR of the last two carries is 1,
and it is cleared to 0 otherwise.
• The subtraction operation is accomplished by adding the content of AC to
the 2's complement of BR.
• Taking the 2's complement of BR has the effect of changing a positive
number to negative, and vice versa.
• An overflow must be checked during this operation because the two
numbers added could have the same sign.
• The programmer must realize that if an overflow occurs, there will be an
erroneous result in the AC register.

Multiplication Algorithms:
• Multiplication of two fixed-point binary numbers in signed-magnitude
representation is done with process of successive shift and adds
operations.
 • This process is best illustrated with a numerical example as follows:

Numerical example of Multiplication

• If the multiplier bit is equal to 1, the multiplicand is copied down; otherwise
zeros are copied down.
• The numbers copied down are shifted one position to the left from
the previous number.
• Finally, the numbers are added and their sum forms the product.

Hardware Implementation for Signed-Magnitude Data Multiplication:

• The hardware for multiplication consists of the equipment shown in Figure
above.
• Initially, the multiplicand is in register B and the multiplier in Q.
• Their corresponding signs are stored in the flip-flops Qs and Bs
• Initially A is set to 0 as number of bits in the multiplicand.
• The sequence counter SC is initially set to a number equal to the number of
bits in the multiplier.
• The sum of A and B forms a partial product which is transferred to the EA
register.
• Both partial product and multiplier are shifted to the right.
• This shift will be denoted by the statement shr EAQ to designate the right
shift depicted in Figure above.
• The least significant bit of A is shifted into the most significant position of
Q, the bit from E is shifted into the most significant position of A, and 0 is
shifted into E.
• After the shift, one bit of the partial product is shifted into Q, pushing the
multiplier bits one position to the right.
• In this manner, the rightmost flip-flop in register Q, designated by Q n, will
hold the bit of the multiplier, which must be inspected next.
• The counter is decremented by 1 after forming each partial product.
When the content of the counter reaches zero, the product is formed and the
process stops.
Hardware Algorithm(Flow chart) Signed-Magnitude Data
Multiplication:

Fig : Flowchart multiply operation on sign magnitude representation numbers

• Initially, the multiplicand is in B and the multiplier in Q.
Theircorresponding signs are in Bs and Qs, respectively.
• The signs are compared, and both signs of A and Q are set to correspond to
the sign of the product since a double-length product will be stored in
registers A and Q.
• Registers A and E are cleared and the sequence counter SC is set to a
 number equal to the number of bits of the multiplier.
• After the initialization, the low-order bit of the multiplier in Qn, is tested.
• If Qn is a 1, the multiplicand in B is added to the present partial product in
A. If Qn is a 0, nothing is done.
• Register EAQ is then shifted once to the right to form the new partial
product.
• The sequence counter is decremented by 1 and its new value checked. If it is
not equal to zero, the process is repeated and a new partial product is
formed. The process stops when SC = 0.
• Note that the partial product formed in A is shifted into Q one bit at a time
and eventually replaces the multiplier.
• The final product is available in both A and Q, with A holding the most
significant bits and Q holding the least significant bits.
• The following table describes multiplication of binary numbers 10111(+23)
and 10011(+19) which are represented using Sign Magnitude Representation.

Table : Numerical Example for Binary Multiplier

 • Now Result is available in Registers A and Q. i.e. 0110110101 => 437 and
sign bit of A is 0. So result is +437.
• The following table 3 describes multiplication of binary numbers 10011(+19)
and 00110(+6)which are represented using Sign Magnitude Representation.
• Here Multiplicand is positive value, so Bs = 0. Here Multiplier is positive
value, so Qs = 0.
• Now As = Bs+ Qs , i.e As is positive; when both Bs and Qs are equal

Booth Multiplication Algorithm (for signed-2’s

complement numbers)
• Booth algorithm gives a procedure for multiplying binary integers in signed-
2's complement representation.

• As in all multiplication schemes, Booth algorithm requires examination of

the multiplier bits and shifting of the partial product.
• Prior to the shifting, the multiplicand may be added to the partial product,
subtracted from the partial product, or left unchanged according to the
following rules:
 1. The multiplicand is subtracted from the partial product upon encountering
the first least significant 1 in a string of 1's in the multiplier.
2.The multiplicand is added to the partial product upon encountering the first
0 (provided that there was a previous 1) in a string of 0's in the multiplier.
3.The partial product does not change when the multiplier bit is identical to
the previous multiplier bit.

The hardware implementation of Booth algorithm requires the register

configuration shown in Figure.
Qn designates the least significant bit of the multiplier in register QR. An extra flip-
flop Qn+1is appended to QR to facilitate a double bit inspection of the multiplier.
The flowchart for Booth algorithm is shown in Figure .
• AC and the appended bit Qn+1 are initially cleared to 0 and the sequence
counter SC is set to a number n equal to the number of bits in the multiplier.
• The two bits of the multiplier in Qn and Qn+1 are inspected.
• If the two bits are equal to 10, it means that the first 1 in a string of 1's has
been encountered. This requires a subtraction of the multiplicand from the
partial product in AC.
• If the two bits are equal to 01, it means that the first 0 in a string of 0's has
been encountered. This requires the addition of the multiplicand to thepartial
product in AC.
• When the two bits are equal, the partial product does not change. An
overflow cannot occur because the addition and subtraction of the
multiplicand follow each other.
• The next step is to shift right the partial product and the multiplier (including
bit Qn+1).
• This is an arithmetic shift right (ashr) operation which shifts AC and QR
to the right and leaves the sign bit in AC unchanged.
• The sequence counter is decremented and the computational loop is repeated
n times.
• A numerical example of Booth algorithm is shown in Table 5. It shows the
step-by-step multiplication of (-9) x (-13) = + 117.
• Here the multiplier in QR is negative and that the multiplicand in BR is also
negative. The 10-bit product appears in AC and QR and is positive.
 Table : Example of Multiplication with Booth Algorithm
• Now Result is available in Registers AR and QR. i.e. 0001110101 =>+117.
ARRAY MULTIPLIER::
• An Array multiplier is implemented with combinational circuit.
• Consider the multiplication of two 2-bit numbers as shown in figure.
• The multiplicand bits are b1 and bo; the multiplier bits are a1 and a0 and
the product is c3c2c1c0.
• The partial product is formed by multiplying a0 by b1b0.
• The multiplication of two bits such as ao and b0 produces a result 1 if both
bits are 1; otherwise , it produces a 0.
• This is identical to an AND operation and can be implemented with an
AND gate.
• As shown in the figure, the first partial product is formed by means of two
AND gates.
• The second partial product is formed by multiplying a1 by b1b0 and is
shifted to one position to the left.
• The two partial products are added with two half adders circuits.
2 bit by 2 bit Array multiplier

Division Algorithm:
• Division of two fixed-point binary numbers in signed magnitude
representation is performed with paper and pencil by a process of successive
compare, shift and subtract operations.
• Binary division is much simpler than decimal division because here the
quotient digits are either 0 or 1.
• The division process is described in Figure
Example of Division Operation:

Hardware Implementation
Division Operation using Pen and Paper:
• The divisor is compared with the five most significant bits of the dividend.
• Since the 5-bit number is smaller than B, we again repeat the same process.
• Now the 6-bit number is greater than B, so we place a 1 for the quotient bit
in the sixth position above the dividend.
• Now we shift the divisor once to the right and subtract it from the dividend.
• The difference is known as a partial remainder because the division could
have stopped here to obtain a quotient of 1 and a remainder equal to the
partial remainder.

Hardware Implementation for Signed-Magnitude Data

• In hardware implementation for signed-magnitude data in a digital
computer, it is convenient to change the process slightly.
• Instead of shifting the divisor to the right, two dividends, or partial
remainders, are shifted to the left, thus leaving the two numbers in the
required relative position.
• Subtraction is achieved by adding A to the 2's complement of B.
• End carry gives the information about the relative magnitudes.
• The hardware required is identical to that of multiplication.
• Comparing a partial remainder with the divisor continues the process.
• If the partial remainder is greater than or equal to the divisor, the
quotient bit is equal to 1.
• The divisor is then shifted right and subtracted from the partial remainder. If
the partial remainder is smaller than the divisor, the quotient bit is 0 and no
subtraction is needed.
• The divisor is shifted once to the right in any case. Obviously the result
gives both a quotient and a remainder.
• Register EAQ is now shifted to the left with 0 inserted into Qn and the
previous value of E is lost.
• The example is given in Figure to clear the proposed division process.
• The divisor is stored in the B register and the double-length dividend
is stored in registers A and Q.
• The dividend is shifted to the left and the divisor is subtracted by adding its
2's complement value.
• End carry(E) gives the information about the relative magnitudes.
• If E = 1, it signifies that A ≥ B. The quotient bit 1 is inserted into Qn and
the partial remainder is shifted to left to the process.
• If E = 0, it signifies that A < B. So the quotient in Qn remains a 0.
• The value of B is added to restore the partial remainder in A to restore to its
previous value.
• The partial remainder is shifted to the left and the process is repeated again
until all quotient bits are formed.
• The remainder is then found in register A and the quotient is in register Q.
• Before showing the algorithm in flowchart form, we have to consider the
sign of the result and a overflow condition.
 Considering the sign of the result and a Overflow condition.

Considerin Normal
g the sign Division
of the
Process
result and a
overflow
condition.
 • Initially, the dividend is in A & Q and the divisor is in B.
• Sign of result is transferred into Q, to be the part of quotient. Then a
constant is set into the SC to specify the number of bits in the quotient.
• Since an operand must be saved with its sign, one bit of the word will be
inhabited by the sign, and the magnitude will be composed of n -1 bits.
• The condition of divide-overflow is checked by subtracting the divisor in
B from the half of bits of the dividend stored in A.
• If A ≥ B, DVF is set and the operation is terminated before time.
• If A < B, no overflow condition occurs and so the value of the dividend
is reinstated by adding B to A.

Normal Division Process using Flowchart:

• The division of the magnitudes starts by shl dividend in AQ to left in the
high- order bit shifted into E.
• Note – If shifted a bit into E is equal to 1, and we know that EA > B as EA
comprises a 1 followed by n -1 bits whereas B comprises only n -1 bits). In
this case, B must be subtracted from EA, and 1 should insert into Q, for the
quotient bit.
• If the shift-left operation (shl) inserts a 0 into E, the divisor is subtracted by
adding its 2’s complement value and the carry is moved into E.
• If E = 1, it means that A ≥ B; thus, Q, is set to 1. If E = 0, it means that A <
B and the original number is restored or reimposed by adding B into A.
• Now, this process is repeated with register A containing the partial
remainder. After n-1 times, the final result is available in A and Q registers.
Example of Binary Division with Digital Hardware:
Input-Output Organization:
Contents:
Peripheral Devices,
Input-Output Interface,
Asynchronous data transfer,
Modes of Transfer,
Priority Interrupt,
Direct memory
Access,
Input –Output Processor (IOP)
Peripheral Devices:
The Input / output organization of computer depends upon the size of computer
and the peripherals connected to it.
The I/O Subsystem of the computer, provides an efficient mode of communication
between the central system and the outside environment
Input/output devices attached to the computer are called Peripheral devices.
The most common input output devices are:
i) Monitor
ii) Keyboard
iii) Mouse
iv) Printer
v) Magnetic tapes
Input Devices

Output Devices
ASCII(American Standard Code for Information
Interchange)- Alphanumeric Characters:
• Input/output devices that communicate with people and the computer are
usually involved in the transfer of Alphanumeric Information to and from
the device and the computer.
• The standard binary code for the alphanumeric characters is ASCII
• It uses 7 bits to code 128 characters.
• ASCII code contains 94 characters that are printable and 34 characters that
are nonprinting characters used for various control functions.
• Among 94, 26 used for uppercase letters, 26 used for lowercase letters,10
are used for numerical and 32 are used for special characters.
• 34 control characters are used for routing and arranging the printed text in a
prescribed format
• 3 types of control characters:
1. Format Effectors (control the layout of printing includes BS-Back
space,HT-Horizontaltab,CR-Carriage Return)
2. Information Separators(used to separate data into paragraphs & pages
includes RS-record seperator and FS-file seperator)
3. Communication control characters (useful for transmission of text
between remote terminals includes STX-Start of text, ETX-End of text)

Input - Output Interface

• Input Output Interface provides a method for transferring information
between internal storage and external I/O devices.
• Peripherals connected to a computer need special communication links for
 interfacing them with the central processing unit.
• The purpose of communication link is to resolve the differences that exist
between the central computer and each peripheral.
The Major Differences are:-
1. Peripherals are electromechnical and electromagnetic devices and CPU and
memory are electronic devices. Therefore, a conversion of signal values may be
needed.
2. The data transfer rate of peripherals is usually slower than the transfer rate of
CPU and consequently, a synchronization mechanism may be needed.
3. Data codes and formats in the peripherals differ from the word format in the
CPU and memory.
4. The operating modes of peripherals are different from each other and must be
controlled so as not to disturb the operation of other peripherals connected to the
CPU.
To Resolve these differences, computer systems include special hardware components
between the CPU and Peripherals to supervises and synchronizes all input and out
transfers
These components are called Interface Units because they interface between the
processor bus and the peripheral devices.

I/O BUS and Interface Module:

• It defines the typical link between the processor and several peripherals as
shown in figure.
 Input/output bus

• The I/O Bus consists of data lines, address lines and control lines.
• The I/O bus from the processor is attached to all peripherals interface.
• To communicate with a particular device, the processor places a device
address on address lines.
• Each Interface decodes the address and control received from the I/O
bus, interprets them for peripherals and provides signals for the
peripheral controller.
• It is also synchronizes the data flow and supervises the transfer between
peripheral and processor.
• Each peripheral has its own controller. For example, the printer controller
controls the paper motion, the print timing
 • The processor provides a function code in the control lines.
• The control lines are referred as I/O command.
• The commands are as following:
• Control command- A control command is issued to activate the peripheral
and to inform it what to do.
• Status command- A status command is used to test various status conditions
in the interface and the peripheral.
• Data Output command- A data output command causes the interface to
respond by transferring data from the bus into one of its registers.
• Data Input command- The data input command is the opposite of the data
output.

I/O Bus Versus Memory Bus:

• To addition to communicate with I/O, the processor must communicate with
the memory unit.
• Like the I/O bus, the memory bus contains data, address and read/write
control lines.
• There are 3 ways that computer buses can be used to communicate with
memory and I/O:
i. Use two Separate buses , one for memory and other for I/O
ii. Use one common bus for both memory and I/O but separate
control lines for each.
iii. Use one common bus for memory and I/O with common
control lines.
• In the first method, the computer has independent sets of data, address and
control buses one for accessing memory and other for I/O.
• This is done in computers that provide a separate I/O processor (IOP).
 • The purpose of IOP is to provide an independent pathway for the transfer of
information between external device and internal memory.
ISOLATED I/O Bus Versus MEMORY MAPPED I/O Bus
Isolated I/O Bus :
The distinction between Memory transfer and I/O transfer is made through separate
read and Write lines.
During an I/O transfer, the I/O read and I/O write contro lsignals are enabled. During
an Memory transfer, the Memory read and Memory write contro lsignals are
enabled.
This configuration isolates all I/O interface addresses from Memory Addresses.
 Separate (isolated) memory and I/O address spaces
• Distinct input and output instructions
Memory Mapped I/O Bus:
 A single set of read/write control lines(no distinction between memory and
I/O transfer)
 Memory and I/O addresses share the common address space ( reduces
memory address range available).
 No specific input or output instruction
 The same memory reference instructions can be used for I/O transfers
 Considerable flexibility in handling I/O operations
Example of I/O INTERFACE:
It consists of two data registers called ports, a control register, a status register, Bus
buffers and Timing and control circuits.
The chip select and register select determines the address assigned to interface.
Asynchronous Data Transfer:
Two units such as CPU and I/O interface are designed independently of each other
and the internal timing of each unit is independent of each other. In this case, the
two units are said to be asynchronous.
• This Scheme is used when speed of I/O devices does not match with
microprocessor, and timing characteristics of I/O devices is not
predictable.
• In this method, process initiates the device and checks its status. As a result,
CPU has to wait till I/O device is ready to transfer data.
• When device is ready CPU issues instruction for I/O transfer. In this method
 two types of techniques are used based on signals before data transfer.
i. Strobe Control
ii. Handshaking
Strobe pulse
A strobe pulse is supplied by one unit to indicate the other unit when the transfer
has to occur(or time at which data is being transferred)
Handshaking
A control signal is accompanied with each data being transmitted to indicate the
presence of data The receiving unit responds with another control signal to
acknowledge receipt of the data.
Strobe Signal :
The strobe control method of Asynchronous data transfer employs a single control
line to time each transfer. The strobe may be activated by either the source or the
destination unit.
Data Transfer Initiated by Source Unit(source initiated strobe signal for data
transfer)

• In the block diagram fig. (a), the data bus carries the binary information
from source to destination unit.
• Typically, the bus has multiple lines to transfer an entire byte or word.
 • The strobe is a single line that informs the destination unit when a valid data
word is available.
• The timing diagram fig. (b) the source unit first places the data on the data
bus.
• The information on the data bus and strobe signal remain in the active state
to allow the destination unit to receive the data.
Data Transfer Initiated by Destination Unit(Destinaation initiated strobe
signal for data transfer)

• In this method, the destination unit activates the strobe pulse, to informing
the source to provide the data.
• The source will respond by placing the requested binary information on the
data bus.
• The data must be valid and remain in the bus long enough for the
destination unit to accept it.
• When accepted the destination unit then disables the strobe and the source
unit removes the data from the bus
Disadvantage of Strobe Signal:
The disadvantage of the strobe method is that, the source unit initiates the transfer
has no way of knowing whether the destination unit has actually received the
data item that was places in the bus.
Similarly, a destination unit that initiates the transfer has no way of knowing
whether the source unit has actually placed the data on bus. The Handshaking
method solves this problem

Handshaking
• The handshaking method solves the problem of strobe method by
introducing a second control signal that provides a reply to the unit that
initiates the transfer.
Principle of Handshaking:
• The basic principle of the two-wire handshaking method of data transfer is
as follow:
• One control line is in the same direction as the data flows in the bus from
the source to destination.
• It is used by source unit to inform the destination unit whether there a valid
data in the bus.
• The other control line is in the other direction from the destination to the
source.
• It is used by the destination unit to inform the source whether it can accept
the data. The sequence of control during the transfer depends on the unit that
initiates the transfer.
Source Initiated Transfer using Handshaking:

• The sequence of events shows four possible states that the system can be at
any given time.
• The source unit initiates the transfer by placing the data on the bus and
enabling its data valid signal.
• The data accepted signal is activated by the destination unit after it accepts
the data from the bus.
• The source unit then disables its data accepted signal and the system goes
into its initial state .
Destination Initiated Transfer Using Handshaking:
• The name of the signal generated by the destination unit has been changed
to ready for data to reflects its new meaning.
• The source unit in this case does not place data on the bus until after it
receives the ready for data signal from the destination unit.
• From there on, the handshaking procedure follows the same pattern as in
the source initiated case.
• The only difference between the Source Initiated and the Destination
Initiated transfer is in their choice of Initial sate
 • Advantage of the Handshaking method:
• The Handshaking scheme provides degree of flexibility and reliability
because the successful completion of data transfer relies on active
participation by both units.
• If any of one unit is faulty, the data transfer will not be completed. Such an
error can be detected by means of a Timeout mechanism which provides an
alarm if the data is not completed within time.

Asynchronous Serial Transmission:

• The transfer of data between two units is serial or parallel.
• In parallel data transmission, n bit in the message must be
transmitted through n separate conductor path.
• In serial transmission, each bit in the message is sent in sequence one at a
time.
• Parallel transmission is faster but it requires many wires. It is used for short
 distances and where speed is important.
• Serial transmission is slower but is less expensive.
• In Asynchronous serial transfer, each bit of message is sent a sequence at a
time, and binary information is transferred only when it is available. When
there is no information to be transferred, line remains idle.
• In this technique each character consists of three points :
i. Start bit
ii. Character bit
iii. Stop bit
• Start Bit- First bit, called start bit is always zero and used to indicate the
beginning character.
• Stop Bit- Last bit, called stop bit is always one and used to indicate end of
characters. Stop bit is always in the 1- state and frame the end of the
characters to signify the idle or wait state.
• Character Bit- Bits in between the start bit and the stop bit are known as
character bits. The character bits always follow the start bit.
Asynchronous Serial Transmission
Serial Transmission of Asynchronous is done by two ways:
a) Asynchronous Communication Interface
b) First In First out Buffer

Asynchronous Communication Interface:

• It works as both a receiver and a transmitter.

• Its operation is initialized by CPU by sending a byte to the control register.
• The transmitter register accepts a data byte from CPU through the data bus
and transferred to a shift register for serial transmission.
• The receive portion receives information into another shift register, and
when a complete data byte is received it is transferred to receiver register.
• CPU can select the receiver register to read the byte through the data bus.
Data in the status register is used for input and output flags.
First In First Out Buffer (FIFO):
• A First In First Out (FIFO) Buffer is a memory unit that stores information
in such a manner that the first item is in the item first out.
• A FIFO buffer comes with separate input and output terminals.
 • The important feature of this buffer is that it can input data and output data
at two different rates.
• When placed between two units, the FIFO can accept data from the source
unit at one rate, rate of transfer and deliver the data to the destination unit at
another rate.
• If the source is faster than the destination, the FIFO is useful for source data
arrive in bursts that fills out the buffer.
• FIFO is useful in some applications when data are transferred asynchronously.

Modes of Data Transfer:

• The data transfer can be handled by various modes.
• Some of the modes use CPU as an intermediate path, others transfer the data
directly to and from the memory unit and

• This can be handled by 3 following ways:

i. Programmed I/O
ii. Interrupt-Initiated I/O
iii. Direct Memory Access (DMA)
Programmed I/O Mode
• In this mode, Programmed I/O operations are the results of I/O instructions
which is a part of computer program.
• Each data transfer is initiated by a instruction in the program.
• Normally the transfer is from a CPU register to peripheral device or vice-
versa.
• Once the data transfer is initiated the CPU starts monitoring the interface to
see when next transfer can made.
• The instructions of the program keep close tabs on everything that takes
 place in the interface unit and the I/O devices.
• In the Programmed I/O Mode, the CPU stays in the program loop until the
I/O indicates that it is ready for data transfer.
Example of Programmed I/O:
• An example of data transfer from an I/O device through an interface into
the CPU is shown in figure:

• The peripheral device transfers bytes of bytes of data one at a time when
they are available.
• When a byte of data is available, the device places it in the I/O bus and
enables data valid line.
• The interface accepts the data into its data register and enables data accepted
line.
• The interface sets a bit in the status register that is referred as Flag bit(F).
 • A program is written for the computer too check for flag in status register to
determine if a byte has placed in the data register by the I/O device.
• This is done by reading the status register to a CPU register and checking
the value of flag bit.
• If F=1, CPU reads the data from data register.
• If F=0, CPU/interface disables the data accepted line.
• A flowchart of the program is written for CPU is shown below
• Here the device is sending a sequence of bytes that must be stored in
memory.
• The transfer of data requires three instructions:

Flowchart:
Drawback of the Programmed I/O :
• The main drawback of the Program Initiated I/O was that the CPU has to
monitor the units all the times when the program is executing.
• Thus the CPU stays in a program loop until the I/O unit indicates that it is
ready for data transfer.
• This is a time consuming process and the CPU time is wasted a lot in
keeping an eye to the executing of program.
• To remove this problem an Interrupt facility and special commands are used.
•

Interrupt-Initiated I/O :
• In this method an interrupt facility called an interrupt command is used to
inform the device about the start and end of transfer.
• In the meantime the CPU executes other program. When the interface
determines that the device is ready for data transfer it generates an Interrupt
Request and sends it to the computer.
• When the CPU receives such an signal, it temporarily stops the execution of
the program and branches to a service program to process the I/O transfer
and after completing it returns back to task, what it was originally
performing.
• In this type of IO, computer does not check the flag. It continue to perform
its task.
• Whenever any device wants the attention, it sends the interrupt signal
to the CPU.
• CPU then deviates from what it was doing, store the return address from
PC and branch to the address of the subroutine.
• There are two ways of choosing the branch address:
 • Vectored Interrupt
• Non-vectored Interrupt
• In vectored interrupt the source that interrupts the CPU provides the
branch information. This information is called interrupt vectored.
• In non-vectored interrupt, the branch address is assigned to the fixed
address in the memory.
Priority Interrupt:
• There are number of IO devices attached to the computer.
• They are all capable of generating the interrupt.
• When the interrupt is generated from more than one device, priority
interrupt system is used to determine which device is to be serviced
first.
• Devices with high speed transfer are given higher priority and slow devices
are given lower priority.
• Establishing the priority can be done in two ways:
Using Software Using
Hardware
• A polling procedure is used to identify highest priority in software means.
• Polling Procedure :
• There is one common branch address for all interrupts.
• Branch address contain the code that polls the interrupt sources in sequence.
• The highest priority is tested first.
• The particular service routine of the highest priority device is served.
• The disadvantage is that time required to poll them can exceed the time to
serve them in large number of IO devices.
• Using Hardware:
• Hardware priority system function as an overall manager
 • It accepts interrupt request and determine the priorities.
• To speed up the operation each interrupting devices has its own interrupt
vector.
• No polling is required, all decision are established by hardware
priority interrupt unit.
• It can be established by serial or parallel connection of interrupt lines.

Serial or Daisy Chaining Priority:

• Device with highest priority is placed first.
• Device that wants the attention send the interrupt request to the CPU.
• CPU then sends the INTACK signal which is applied to PI(priority in) of
the first device.
• If it had requested the attention, it place its VAD(vector address) on the
bus. And it block the signal by placing 0 in PO(priority out)
• If not it pass the signal to next device through PO(priority out) by placing 1.
• This process is continued until appropriate device is found.
• The device whose PI is 1 and PO is 0 is the device that send the interrupt
request
Parallel Priority Interrupt:
• It consists of interrupt register whose bits are set separately by the
interrupting devices.
• Priority is established according to the position of the bits in the register.
• Mask register is used to provide facility for the higher priority devices to
interrupt when lower priority device is being serviced or disable all lower
priority devices when higher is being serviced.
• Corresponding interrupt bit and mask bit are ANDed and applied to priority
encoder.
• Priority encoder generates two bits of vector address.
• Another output from it sets IST(interrupt status flip flop).

Priority Interrupt Hardware

Priority Encoder:
Determines the highest priority interrupt when more than one interrupts take place
If two or more inputs arrive at the same time, the input having the highest priority
will take precedence.
Input I0 has the highest priority and I3 has the lowest Priority.

Priority Encoder Truth Table

INTERRUPT CYCLE:
• At the end of each Instruction cycle
• CPU checks IEN and IST
• If IEN  IST = 1, CPU -> Interrupt Cycle

SP  SP - 1 Decrement stack
M[SP]  PC
pointer Push PC into
INTACK  1
stack
PC  VAD
Enable interrupt
IEN  0
acknowledge Transfer vector
Go To Fetch
address to PC Disable further
interrupts
to execute the first instruction
in the interrupt service
routine
Direct Memory Access (DMA):
• In the Direct Memory Access (DMA) the interface transfer the data into
and out of the memory unit through the memory bus.
• The transfer of data between a fast storage device such as magnetic disk and
memory is often limited by the speed of the CPU.
• Removing the CPU from the path and letting the peripheral device
manage the memory buses directly would improve the speed of transfer.
• This transfer technique is called Direct Memory Access (DMA).
• During the DMA transfer, the CPU is idle and has no control of the memory
buses.
• A DMA Controller takes over the buses to manage the transfer directly
between the I/O device and memory.
• The CPU may be placed in an idle state in a variety of ways. One common
method extensively used in microprocessor is to disable the buses through
special control signals such as:
Bus Request (BR)
Bus Grant (BG)
 These two control signals in the CPU that facilitates the DMA transfer.
 The Bus Request (BR) input is used by the DMA controller to request the
CPU.
 When this input is active, the CPU terminates the execution of the current
instruction and places the address bus, data bus and read write lines into a
high Impedance state. High Impedance state means that the output is
disconnected.
 CPU Bus signals for DMA Transfer:

• The CPU activates the Bus Grant (BG) output to inform the external DMA
that the Bus Request (BR) can now take control of the buses to conduct
memory transfer without processor.
• When the DMA terminates the transfer, it disables the Bus Request (BR) line.
• The CPU disables the Bus Grant (BG), takes control of the buses and return
to its normal operation.
• The transfer can be made in several ways that are:
i. DMA Burst
ii. Cycle Stealing
DMA Burst :-
In DMA Burst transfer, a block sequence consisting of a number of memory words
is transferred in continuous burst while the DMA controller is master of the
memory buses.
Cycle Stealing:
• Cycle stealing allows the DMA controller to transfer one data word at a
time, after which it must returns control of the buses to the CPU
 DMA Controller:
• The DMA controller needs the usual circuits of an interface to communicate
with the CPU and I/O device. The DMA controller has three registers:
i. Address Register
ii. Word Count Register
iii. Control Register
i. Address Register :- Address Register contains an address to specify the
desired location in memory.
ii. Word Count Register :- WC holds the number of words to be
transferred and internally tested for zero.
iii. Control Register :-
 Control Register specifies the mode of transfer
The unit communicates with the CPU via the data bus and control lines.
The registers in the DMA are selected by the CPU through the address bus by
enabling the DS (DMA select) and RS (Register select) inputs.
 The RD (read) and WR (write) inputs are bidirectional.
 When the BG (Bus Grant) input is 0, the CPU can communicate with the
DMA registers through the data bus to read from or write to the DMA
registers.
 When BG =1, the DMA can communicate directly with the memory by
specifying an address in the address bus and activating the RD or WR
control.
Block Diagram of DMA Controller

DMA Transfer:
 • The CPU communicates with the DMA through the address and data buses
as with any interface unit.
• The DMA has its own address, which activates the DS and RS lines.
• The CPU initializes the DMA through the data bus. Once the DMA receives
the start control command, it can transfer between the peripheral and the
memory.
• When BG = 0 the RD and WR are input lines allowing the CPU to
communicate with the internal DMA registers.
• When BG=1, the RD and WR are output lines from the DMA controller to
the random access memory to specify the read or write operation of data.

Input-Output Processor:
• It is a processor with direct memory access capability that
communicates with IO devices.
• IOP is similar to CPU except that it is designed to handle the details of IO
operation.
• Unlike DMA which is initialized by CPU, IOP can fetch and execute its
own instructions.
• IOP instruction are specially designed to handle IO operation.
Block Diagram of a computer with a I/O Processor:

• Memory occupies the central position and can communicate with each
processor by DMA.
• CPU is responsible for processing data.
• IOP provides the path for transfer of data between various peripheral
devices and memory.
• Data formats of peripherals differ from CPU and memory. IOP maintain
such problems.
• Data is transferred from IOP to memory by stealing one memory cycle.
• Instructions that are read from memory by IOP are called commands to
distinguish them from instructions that are read by the CPU.
CPU- IOP Communication:

• Instruction that are read from memory by an IOP

• Distinguish from instructions that are read by the CPU.
• Commands are prepared by experienced programmers and are stored
in memory
• Command word = IOP program
– m