UNIT-3

COMPUTER ARITHMETIC

Introduction:

Data is manipulated by using the arithmetic instructions in digital computers. Data is

manipulated to produce results necessary to give solution for the computation problems.
The Addition, subtraction, multiplication and division are the four basic arithmetic
operations. If we want then we can derive other operations by using these four operations.

To execute arithmetic operations there is a separate section called arithmetic processing

unit in central processing unit. The arithmetic instructions are performed generally on
binary or decimal data. Fixed-point numbers are used to represent integers or fractions.
We can have signed or unsigned negative numbers. Fixed-point addition is the simplest
arithmetic operation.

If we want to solve a problem then we use a sequence of well-defined steps. These steps
are collectively called algorithm. To solve various problems we give algorithms.

In order to solve the computational problems, arithmetic instructions are used in digital
computers that manipulate data. These instructions perform arithmetic calculations.

And these instructions perform a great activity in processing data in a digital computer.
As we already stated that with the four basic arithmetic operations addition, subtraction,
multiplication and division, it is possible to derive other arithmetic operations and solve
scientific problems by means of numerical analysis methods.

A processor has an arithmetic processor(as a sub part of it) that executes arithmetic
operations. The data type, assumed to reside in processor, registers during the execution
of an arithmetic instruction. Negative numbers may be in a signed magnitude or signed
complement representation. There are three ways of representing negative fixed point -
binary numbers signed magnitude, signed 1’s complement or signed 2’s complement.
Most computers use the signed magnitude representation for the mantissa.
Addition and Subtraction :
Addition and Subtraction with Signed –Magnitude Data

We designate the magnitude of the two numbers by A and B. Where the signed numbers
are added or subtracted, we find that there are eight different conditions to consider,
depending on the sign of the numbers and the operation performed. These conditions are
listed in the first column of Table 4.1. The other columns in the table show the actual
operation to be performed with the magnitude of the numbers. The last column is needed
to present a negative zero. In other words, when two equal numbers are subtracted, the
result should be +0 not -0. The algorithms for addition and subtraction are derived from
the table and can be stated as follows (the words parentheses should be used for the
subtraction algorithm).
Addition and Subtraction of Signed-Magnitude Numbers

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Computer Arithmetic Addition and Subtraction

SIGNED MAGNITUDEADDITION AND SUBTRACTION

Addition: A + B ; A: Augend; B: Addend
Subtraction: A - B: A: Minuend; B: Subtrahend

Add Subtract Magnitude

Operation Magnitude When A>B When A<B When A=B
(+A) + (+B) +(A + B)
(+A) + (- B) +(A - B) - (B - A) +(A - B)
(- A) + (+B) - (A - B) +(B - A) +(A - B)
(- A) + (- B) - (A + B)
(+A) - (+B) +(A - B) - (B - A) +(A - B)
(+A) - (- B) +(A + B)
(- A) - (+B) - (A + B)
(- A) - (- B) - (A - B) +(B - A) +(A - B)

Hardware Implementation Bs B Register

AVF Complementer M(Mode Control)

E Output Input
Parallel Adder
Carry Carry
S
As A Register Load Sum

Computer Arithmetic Addition and Subtraction

SIGNED 2’S COMPLEMENT ADDITION AND SUBTRACTION

Hardware
B Register

Complementer and
V
Parallel Adder
Overflow

AC

Algorithm
Subtract Add

Minuend in AC Augend in AC
Subtrahend in B Addend in B

AC m AC + B’+ 1 AC m AC + B
V m overflow V m overflow

END END

Algorithm:

The flowchart is shown in Figure 7.1. The two signs A, and B, are
compared by an exclusive-OR gate.

If the output of the gate is 0 the signs

are identical; If it is 1, the signs are
different.

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For an add operation, identical signs dictate that the magnitudes be

added. For a subtract operation, different signs dictate that the
magnitudes be added.
The magnitudes are added with a microoperation EA A + B, where EA is a
register that combines E and A. The carry in E after the addition constitutes an
overflow if it is equal to 1. The value of E is transferred into the add-overflow
flip-flop AVF.

The two magnitudes are subtracted if the signs are different for an add
operation or identical for a subtract operation. The magnitudes are subtracted
by adding A to the 2's complemented B. No overflow can occur if the numbers
are subtracted so AVF is cleared to 0.

1 in E indicates that A >= B and the number in A is the correct result. If this
numbs is zero, the sign A must be made positive to avoid a negative zero.

0 in E indicates that A < B. For this case it is necessary to take the 2's
complement of the value in A. The operation can be done with one
microoperation A A' +1.
However, we assume that the A register has circuits for microoperations
complement and increment, so the 2's complement is obtained from these two
microoperations.

In other paths of the flowchart, the sign of the result is the same as the sign of
A. so no change in A is required. However, when A < B, the sign of the result
is the complement of the original sign of A. It is then necessary to complement
A, to obtain the correct sign.

The final result is found in register A and its sign in As. The value in AVF
provides an overflow indication. The final value of E is immaterial.

Figure 7.2 shows a block diagram of the hardware for implementing the
addition and subtraction operations.
It consists of registers A and B and sign flip-flops As
and Bs. Subtraction is done by adding A to the 2's
complement of B.

The output carry is transferred to flip-flop E , where it can be checked to

determine the relative magnitudes of two numbers.
The add-overflow flip-flop AVF holds the overflow bit when A and B are added.

The A register provides other microoperations that may be needed when we

specify the sequence of steps in the algorithm.

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Multiplication Algorithm:
In the beginning, the multiplicand is in B and the multiplier in Q. Their
corresponding signs are in Bs and Qs respectively. We compare the signs
of both A and Q and set to corresponding sign of the product since a
double-length product will be stored in registers A and Q. Registers A and
E are cleared and the sequence counter SC is set to the number of bits of
the multiplier. Since an operand must be stored with its sign, one bit of the
word will be occupied by the sign and the magnitude will consist of n-1
bits.

Now, the low order bit of the multiplier in Qn is tested. If it is 1, the

multiplicand (B) is added to present partial product (A), 0 otherwise.
Register EAQ is then shifted once to the right to form the new partial
product. The sequence counter is decremented by 1 and its new value
checked. If it is not equal to zero, the process is repeated and a new partial
product is formed. When SC = 0 we stops the process.

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Booth’s algorithm :
Booth algorithm gives a procedure for multiplying binary
integers in signed- 2’s complement representation.
It operates on the fact that strings of 0’s in the multiplier require no addition
but just

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shifting, and a string of 1’s in the multiplier from bit weight
2k to weight 2m can be treated as 2k+1 – 2m.

For example, the binary number 001110 (+14) has a string 1’s
from 23 to 21 (k=3, m=1). The number can be represented as 2k+1 –
2m. = 24 – 21 = 16 – 2 = 14. Therefore, the multiplication M X 14,
where M is the multiplicand and 14 the multiplier, can be done
as M X 24 – M X 21.
Thus the product can be obtained by shifting the binary
multiplicand M four times to the left and subtracting M shifted
left once.

As in all multiplication schemes, booth algorithm

requires examination of the multiplier bits and shifting
of partial product.

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Prior to the shifting, the multiplicand may be added to the

partial product, subtracted from the partial, or left unchanged
according to the following rules:
1. The multiplicand is subtracted from the partial product upon
encountering the first least significant 1 in a string of 1’s in
the multiplier.

2. The multiplicand is added to the partial product upon

encountering the first 0 in a string of 0’s in the multiplier.

3. The partial product does not change when multiplier bit is

identical to the previous multiplier bit.

The algorithm works for positive or negative

multipliers in 2’s complement representation.

This is because a negative multiplier ends with a string of 1’s

and the last operation will be a subtraction of the appropriate
weight.
The two bits of the multiplier in Qn and Qn+1 are inspected.

If the two bits are equal to 10, it means that the first 1 in a string
of 1 's has been encountered. This requires a subtraction of the
multiplicand from the partial product in AC.

If the two bits are equal to 01, it means that the first 0 in a string
of 0's has been encountered. This requires the addition of the
multiplicand to the partial product in AC.
When the two bits are equal, the partial product does not change.

Division Algorithms
Division of two fixed-point binary numbers in signed magnitude
representation is performed with paper and pencil by a process of
successive compare, shift and subtract operations. Binary division is much
simpler than decimal division because here the quotient digits are either 0
or 1 and there is no need to estimate how many times the dividend or
partial remainder fits into the divisor. The division process is described in
Figure

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The devisor is compared with the five most significant bits of the dividend. Since the 5-bit number is smaller
than B, we again repeat the same process. Now the 6-bit number is greater than B, so we place a 1 for the
quotient bit in the sixth position above the dividend. Now we shift the divisor once to the
right and subtract it from the dividend. The difference is known
as a partial remainder because the division could have stopped
here to obtain a quotient of 1 and a remainder equal to the partial
remainder. Comparing a partial remainder with the divisor
continues the process. If the partial remainder is greater than or
equal to the divisor, the quotient bit is equal to
1. The divisor is then shifted right and subtracted from the partial
remainder. If the partial remainder is smaller than the divisor, the
quotient bit is 0 and no subtraction is needed. The divisor is
shifted once to the right in any case. Obviously the result gives
both a quotient and a remainder.

Hardware Implementation for Signed-Magnitude Data

In hardware implementation for signed-magnitude data in a

digital computer, it is convenient to change the process slightly.
Instead of shifting the divisor to the right, two dividends, or
partial remainders, are shifted to the left, thus leaving the two
numbers in the required relative position. Subtraction is achieved
by adding A to the 2's complement of B. End carry gives the
information about the relative magnitudes.

The hardware required is identical to that of multiplication.

Register EAQ is now shifted to the left with 0 inserted into Qn
and the previous value of E is lost. The example is given in
Figure 4.10 to clear the proposed division process. The divisor is
stored in the B register and the double-length dividend is stored
in registers A and Q. The dividend is shifted to the left and the
divisor is subtracted by adding its 2's complement value. E

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Hardware Implementation for Signed-Magnitude Data

\Algorithm:

Example of Binary Division with Digital Hardware

Floating-point Arithmetic operations :

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In many high-level programming languages we have a facility for

specifying floating-point numbers. The most common way is by a real
declaration statement. High level programming languages must have a
provision for handling floating-point arithmetic operations. The operations
are generally built in the internal hardware. If no hardware is available, the
compiler must be designed with a package of floating-point software
subroutine. Although the hardware method is more expensive, it is much
more efficient than the software method. Therefore, floating- point
hardware is included in most computers and is omitted only in very small
ones.

Basic Considerations :

There are two part of a floating-point number in a computer - a mantissa m

and an exponent e. The two parts represent a number generated from
multiplying m times a radix r raised to the value of e. Thus

m x re

The mantissa may be a fraction or an integer. The position of the radix

point and the value of the radix r are not included in the registers. For
example, assume a fraction representation and a radix
10. The decimal number 537.25 is represented in a register with m = 53725
and e = 3 and is interpreted to represent the floating-point number

.53725 x 103

A floating-point number is said to be normalized if the most significant

digit of the mantissa in nonzero. So the mantissa contains the maximum
possible number of significant digits. We cannot normalize a zero because
it does not have a nonzero digit. It is represented in floating-point by all 0’s
in the mantissa and exponent.

Floating-point representation increases the range of numbers for a given

register. Consider a computer with 48-bit words. Since one bit must be
reserved for the sign, the range of fixed-point integer numbers will be +
(247 – 1), which is approximately + 1014. The 48 bits can be used to
represent a floating-point number with 36 bits for the mantissa and 12 bits
for the exponent. Assuming fraction representation for the mantissa and
taking the two sign bits into consideration, the range of numbers that can be
represented is

+ (1 – 2-35) x 22047

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This number is derived from a fraction that contains 35 1’s, an exponent of

11 bits (excluding its sign), and because 211–1 = 2047. The largest number
that can be accommodated is approximately 10615. The mantissa that can
accommodated is 35 bits (excluding the sign) and if considered as an
integer it can store a number as large as (235 –1). This is approximately
equal to 1010, which is equivalent to a decimal number of 10 digits.

Computers with shorter word lengths use two or more words to represent a
floating-point number. An 8-bit microcomputer uses four words to
represent one floating-point number. One word of 8 bits are reserved for
the exponent and the 24 bits of the other three words are used in the
mantissa.
Arithmetic operations with floating-point numbers are more complicated
than with fixed-point numbers. Their execution also takes longer time and
requires more complex hardware. Adding or subtracting two numbers
requires first an alignment of the radix point since the exponent parts must
be made equal before adding or subtracting the mantissas. We do this
alignment by shifting one mantissa while its exponent is adjusted until it
becomes equal to the other exponent. Consider the sum of the following
floating-point numbers:

.5372400 x 102

+ .1580000 x 10-1

Floating-point multiplication and division need not do an alignment of the

mantissas. Multiplying the two mantissas and adding the exponents can
form the product. Dividing the mantissas and subtracting the exponents
perform division.

The operations done with the mantissas are the same as in fixed-point
numbers, so the two can share the same registers and circuits. The
operations performed with the exponents are compared and incremented
(for aligning the mantissas), added and subtracted (for multiplication) and
division), and decremented (to normalize the result). We can represent the
exponent in any one of the three representations - signed-magnitude, signed
2’s complement or signed 1’s complement.

Biased exponents have the advantage that they contain only positive
numbers. Now it becomes simpler to compare their relative magnitude
without bothering about their signs. Another advantage is that the smallest
possible biased exponent contains all zeros. The floating-point

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representation of zero is then a zero mantissa and the smallest possible

exponent.
Register Configuration

The register configuration for floating-point operations is shown in figure

4.13. As a rule, the same registers and adder used for fixed-point arithmetic
are used for processing the mantissas. The difference lies in the way the
exponents are handled.

The register organization for floating-point operations is shown in Fig.

4.13. Three registers are there, BR, AC, and QR. Each register is
subdivided into two parts. The mantissa part has the same uppercase letter
symbols as in fixed-point representation. The exponent part may use
corresponding lower-case letter symbol.
Computer Arithmetic 14 Floating Point Arithmetic

FLOATING POINT ARITHMETIC OPERATIONS

F = m x re
where m: Mantissa
r: Radix
e: Exponent

Registers for Floating Point Arithmetic

Bs B b BR

Parallel Adder
E Parallel Adder and Comparator

As A1 A a AC

Qs Q q QR

Computer Organization Prof. H. Yoon

Figure 4.13: Registers for Floating Point arithmetic operations

Assuming that each floating-point number has a mantissa in signed-

magnitude representation and a biased exponent. Thus the AC has a
mantissa whose sign is in As, and a magnitude that is in A. The diagram
shows the most significant bit of A, labeled by A1. The bit in his position
must be a 1 to normalize the number. Note that the symbol AC represents
the entire register, that is, the concatenation of As, A and a.

In the similar way, register BR is subdivided into Bs, B, and b and QR into

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Qs, Q and q. A parallel-adder adds the two mantissas and loads the sum
into A and the carry into E. A separate parallel adder can be used for the
exponents. The exponents do not have a district sign bit because they are
biased but are represented as a biased positive quantity. It is assumed that
the floating- point number are so large that the chance of an exponent
overflow is very remote and so the exponent overflow will be neglected.
The exponents are also connected to a magnitude comparator that provides
three binary outputs to indicate their relative magnitude.

The number in the mantissa will be taken as a fraction, so they binary point
is assumed to reside to the left of the magnitude part. Integer representation
for floating point causes certain scaling problems during multiplication and
division. To avoid these problems, we adopt a fraction representation.

The numbers in the registers should initially be normalized. After each

arithmetic operation, the result will be normalized. Thus all floating-point
operands are always normalized.
Addition and Subtraction of Floating Point
Numbers
During addition or subtraction, the two floating-point operands are kept in
AC and BR. The sum or difference is formed in the AC. The algorithm can
be divided into four consecutive parts:

1. Check for zeros.

2. Align the mantissas.

3. Add or subtract the mantissas

4. Normalize the result

A floating-point number cannot be normalized, if it is 0. If this number is

used for computation, the result may also be zero. Instead of checking for
zeros during the normalization process we check for zeros at the beginning
and terminate the process if necessary. The alignment of the mantissas
must be carried out prior to their operation. After the mantissas are added
or subtracted, the result may be un-normalized. The normalization
procedure ensures that the result is normalized before it is transferred to
memory.

If the magnitudes were subtracted, there may be zero or may have an underflow in
the result. If the mantissa is equal to zero the entire floating-point number in the

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AC is cleared to zero. Otherwise, the mantissa must have at least one bit that is
equal to 1. The mantissa has an underflow if the most significant bit in position
A1, is 0. In that case, the mantissa is shifted left and the exponent decremented.
The bit in A1 is checked again and the process is repeated until A1 = 1. When A1
= 1, the mantissa is normalized and the operation is completed.

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Algorithm for Floating Point Addition and Subtraction

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Multiplication:

Computer Arithmetic 17 Floating Point Arithmetic

FLOATING POINT DIVISION

BR m Divisor
AC m Dividend

=0
BR
z0
=0 AC
Qs m As + Bs z 0
Q m 0 SC
QR m 0 m n-1
EA m A+B’+1
divide
by 0

1 E 0
A>=B A<B

A m A+B A m A+B
shr A a
m a+1

a m a+b’+1
a m a+bias
qma

Divide Magnitude of mantissa as

in fixed point numbers

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UNIT III
Basic Computer Organization and Design
Instruction codes. Computer Registers Computer instructions, Timing and
Control, Instruction cycle. Memory Reference Instructions, Input – Output and
Interrupt, Complete Computer Description.

-----------------------------------------------------------------------------------
-------------------------
Instruction Formats:

A computer will usually have a variety of instruction code formats. It

is the function of the control unit within the CPU to interpret each
instruction code and provide the necessary control functions needed to
process the instruction.
The format of an instruction is usually depicted in a rectangular box
symbolizing the bits of the instruction as they appear in memory words or in
a control register. The bits of the instruction are divided into groups called
fields. The most common fields found in instruction formats are:
1 An operation code field that specifies the operation to be
performed.
2. An address field that designates a memory address or a processor
registers.
3. A mode field that specifies the way the operand or the effective
address is determined.
Other special fields are sometimes employed under certain
circumstances, as for example a field that gives the number of shifts in a
shift-type instruction.
The operation code field of an instruction is a group of bits that define
various processor operations, such as add, subtract, complement, and shift.
The bits that define the mode field of an instruction code specify a variety
of alternatives for choosing the operands from the given address.
Operations specified by computer instructions are executed on some
data stored in memory or processor registers, Operands residing in
processor registers are specified with a register address. A register address
is a binary number of k bits that defines one of 2k registers in the CPU. Thus
a CPU with 16 processor registers R0 through R15 will have a register
address field of four bits. The binary number 0101, for example, will

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designate register R5.

Computers may have instructions of several different lengths

containing varying number of addresses. The number of address fields in
the instruction format of a computer depends on the internal organization of
its registers. Most computers fall into one of three types of CPU
organizations:
1 Single accumulator organization.
2 General register organization.
3 Stack organization.
All operations are performed with an implied accumulator register.
The instruction format in this type of computer uses one address field. For
example, the instruction that specifies an arithmetic addition is defined by
an assembly language instruction as ADD.

Where X is the address of the operand. The ADD instruction in this

case results in the operation AC ← AC + M[X]. AC is the accumulator
register and M[X] symbolizes the memory word located at address X.
An example of a general register type of organization was presented
in Fig. 7.1. The instruction format in this type of computer needs three
register address fields. Thus the instruction for an arithmetic addition may
be written in an assembly language as

ADD R1, R2, R3

To denote the operation R1 ← R2 + R3. The number of address fields
in the instruction can be reduced from three to two if the destination register
is the same as one of the source registers. Thus the instruction
ADD R1, R2
Would denote the operation R1 ← R1 + R2. Only register addresses
for R1 and R2 need be specified in this instruction.
Computers with multiple processor registers use the move instruction
with a mnemonic MOV to symbolize a transfer instruction. Thus the
instruction
MOV R1, R2
Denotes the transfer R1 ← R2 (or R2 ← R1, depending on the
particular computer). Thus transfer-type instructions need two address fields

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to specify the source and the destination.

General register-type computers employ two or three address fields in
their instruction format. Each address field may specify a processor register
or a memory word. An instruction symbolized by
ADD R1, X
Would specify the operation R1 ← R + M [X]. It has two address
fields, one for register R1 and the other for the memory address X.
The stack-organized CPU was presented in Fig. 8-4. Computers with
stack organization would have PUSH and POP instructions which require
an address field. Thus the instruction
PUSH X
Will push the word at address X to the top of the stack. The stack
pointer is updated automatically. Operation-type instructions do not need an
address field in stack-organized computers. This is because the operation is
performed on the two items that are on top of the stack. The instruction
ADD in a stack computer consists of an operation code only with no address
field. This operation has the effect of popping the two top numbers from the
stack, adding the numbers, and pushing the sum into the stack. There is no
need to specify operands with an address field since all operands are
implied to be in the stack.
To illustrate the influence of the number of addresses on computer
programs, we will evaluate the arithmetic statement X = (A + B) 䌫 (C + D).

Using zero, one, two, or three address instruction. We will use the
symbols ADD, SUB, MUL, and DIV for the four arithmetic operations;
MOV for the transfer-type operation; and LOAD and STORE for transfers
to and from memory and AC register. We will assume that the operands are
in memory addresses A, B, C, and D, and the result must be stored in
memory at address X.

Three-Address Instructions
Computers with three-address instruction formats can use each
address field to specify either a processor register or a memory operand.
The program in assembly language that evaluates X = (A + B) 䌫 (C + D) is
shown below, together with comments that explain the register transfer

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operation of each instruction.

ADD R1, A, B R1 ←
M [A] + M [B]
ADD R2, C, D R2 ←
M [C] + M [D]
MUL X, R1, R2 M [X]
← R1 䌫 R2
It is assumed that the computer has two processor registers, R1 and R2. The
symbol M [A] denotes the operand at memory address symbolized by A.
The advantage of the three-address format is that it results in short programs
when evaluating arithmetic expressions. The disadvantage is that the binary-
coded instructions require too many bits to specify three addresses. An
example of a commercial computer that uses three-address instructions is
the Cyber 170. The instruction formats in the Cyber computer are restricted
to either three register address fields or two register address fields and one
memory address field.

Two-Address Instructions
Two address instructions are the most common in commercial computers.
Here again each address field can specify either a processor register or a
memory word. The program to evaluate X = (A + B) 䌫 (C + D) is as
follows:
MOV R1, A R1 ← M [A]
ADD R1, B R1 ← R1 + M [B]
MOV R2, C R2 ← M [C]
ADD R2, D R2 ← R2 + M [D]
MUL R1, R2 R1 ← R1䌫R2
MOV X, R1 M [X] ← R1

The MOV instruction moves or transfers the operands to and from

memory and processor registers. The first symbol listed in an instruction is
assumed to be both a source and the destination where the result of the
operation is transferred.

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One-Address Instructions
One-address instructions use an implied accumulator (AC) register for
all data manipulation. For multiplication and division there is a need for a
second register. However, here we will neglect the second and assume that
the AC contains the result of tall operations. The program to evaluate X =
(A + B) 䌫 (C + D) is
LOAD A AC ← M [A]
ADD B AC ← A [C] + M [B]
STORE T M [T] ← AC
LOAD C AC ← M [C]
ADD D AC ← AC + M [D]
MUL T AC ← AC 䌫 M [T]
STORE X M [X] ← AC
All operations are done between the AC register and a memory
operand. T is the address of a temporary memory location required for
storing the intermediate result.

Zero-Address Instructions
A stack-organized computer does not use an address field for the
instructions ADD and MUL. The PUSH and POP instructions, however,
need an address field to specify the operand that communicates with the
stack. The following program shows how X = (A + B) 䌫 (C + D) will be
written for a stack organized computer. (TOS stands for top of stack)
PUSH A TOS ← A
PUSH B TOS ← B
ADD TOS ← (A + B)
PUSH C TOS ← C
PUSH D TOS ← D
ADD TOS ← (C + D)
MUL TOS ← (C + D) 䌫 (A + B)
POP X M [X] ← TOS

To evaluate arithmetic expressions in a stack computer, it is necessary

to convert the expression into reverse Polish notation. The name “zero-
address” is given to this type of computer because of the absence of an

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address field in the computational instructions.

Instruction Codes
A set of instructions that specify the operations, operands, and the sequence by
which processing has to occur. An instruction code is a group of bits that tells the
computer to perform a specific operation part.

Format of Instruction
The format of an instruction is depicted in a rectangular box symbolizing the bits
of an instruction. Basic fields of an instruction format are given below:
1. An operation code field that specifies the operation to be performed.
2. An address field that designates the memory address or register.
3. A mode field that specifies the way the operand of effective address is
determined.

Computers may have instructions of different lengths containing varying number

of addresses. The number of address field in the instruction format depends upon
the internal organization of its registers.

Addressing Modes
To understand the various addressing modes to be presented in this section,
it is imperative that we understand the basic operation cycle of the computer.
The control unit of a computer is designed to go through an instruction cycle
that is divided into three major phases:

1. Fetch the instruction from memory

2. Decode the instruction.
3. Execute the instruction.
There is one register in the computer called the program counter of PC that
keeps track of the instructions in the program stored in memory. PC holds the
address of the instruction to be executed next and is incremented each time an
instruction is fetched from memory. The decoding done in step 2 determines
the operation to be performed, the addressing mode of the instruction and the
location of the operands. The computer then executes the instruction and
returns to step 1 to fetch the next instruction in sequence.
In some computers the addressing mode of the instruction is specified
with a distinct binary code, just like the operation code is specified. Other
computers use a single binary code that designates both the operation and
the mode of the instruction. Instructions may be defined with a variety of

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addressing modes, and sometimes, two or more addressing modes are

combined in one instruction.
1. The operation code specified the operation to be performed. The
mode field is sued to locate the operands needed for the operation. There
may or may not be an address field in the instruction. If there is an address
field, it may designate a memory address or a processor register. Moreover,
as discussed in the preceding section, the instruction may have more than
one address field, and each address field may be associated with its own
particular addressing mode.
Although most addressing modes modify the address field of the
instruction, there are two modes that need no address field at all. These are
the implied and immediate modes.
1 Implied Mode: In this mode the operands are specified implicitly in the
definition of the instruction. For example, the instruction “complement accumulator” is
an implied-mode instruction because the operand in the accumulator register is implied
in the definition of the instruction. In fact, all register reference instructions that sue an
accumulator are implied-mode instructions.
Op code Mode Address

Figure 1: Instruction format with mode field

Zero-address instructions in a stack-organized computer are implied-
mode instructions since the operands are implied to be on top of the stack.

2 Immediate Mode: In this mode the operand is specified in the instruction

itself. Inother words, an immediate- mode instruction has an operand field rather than
an address field. The operand field contains the actual operand to be used in
conjunction with the operation specified in the instruction. Immediate-mode
instructions are useful for initializing registers to a constant value.
It was mentioned previously that the address field of an instruction
may specify either a memory word or a processor register. When the
address field specifies a processor register, the instruction is said to be in the
register mode.

3 Register Mode: In this mode the operands are in registers that reside within
the CPU.The particular register is selected from a register field in the instruction. A k-
bit field can specify any one of 2k registers.
4 Register Indirect Mode: In this mode the instruction specifies a register in the
CPUwhose contents give the address of the operand in memory. In other words, the

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selected register contains the address of the operand rather than the operand itself.
Before using a register indirect mode instruction, the programmer must
ensure that the memory address fo the operand is placed in the processor
register with a previous instruction. A reference to the register is then
equivalent to specifying a memory address. The advantage of a register
indirect mode instruction is that the address field of the instruction sues
fewer bits to select a register than would have been required to specify a
memory address directly.
5 Auto increment or Auto decrement Mode: This is similar to the register indirect
modeexcept that the register is incremented or decremented after (or before) its value is
used to access memory. When the address stored in the register refers to a table of data
in memory, it is necessary to increment or decrement the register after every access to
the table. This can be achieved by using the increment or decrement instruction.
However, because it is such a common requirement, some computers incorporate a
special mode that automatically increments or decrements the content of the register
after data access.

The address field of an instruction is used by the control unit in the

CPU to obtain the operand from memory. Sometimes the value given in the
address field is the address of the operand, but sometimes it is just an
address from which the address of the operand is calculated. To differentiate
among the various addressing modes it is necessary to distinguish between
the address part of the instruction and the effective address used by the
control when executing the instruction. The effective address is defined to
be the memory address obtained from the computation dictated by the given
addressing mode. The effective address is the address of the operand in a
computational-type instruction. It is the address where control branches in
response to a branch-type instruction. We have already defined two
addressing modes in previous chapter.

6 Direct Address Mode: In this mode the effective address is equal to the address part
ofthe instruction. The operand resides in memory and its address is given directly by
the address field of the instruction. In a branch-type instruction the address field
specifies the actual branch address.
7 Indirect Address Mode: In this mode the address field of the instruction gives
theaddress where the effective address is stored in memory. Control fetches the
instruction from memory and uses its address part to access memory again to read the

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effective address.

8 Relative Address Mode: In this mode the content of the program counter is added to
theaddress part of the instruction in order to obtain the effective address. The address
part of the instruction is usually a signed number (in 2’s complement representation)
which can be either positive or negative. When this number is added to the content of
the program counter, the result produces an effective address whose position in
memory is relative to the address of the next instruction. To clarify with an example,
assume that the program counter contains the number 825 and the address part of the
instruction contains the number 24. The instruction at location 825 is read from
memory during the fetch phase and the program counter is then incremented by one
to 826 + 24 = 850. This is 24 memory locations forward from the address of the next
instruction. Relative addressing is often used with branch-type instructions when the
branch address is in the area surrounding the instruction word itself. It results in a
shorter address field in the instruction format since the relative address can be
specified with a smaller number of bits compared to the number of bits required to
designate the entire memory address.

9 Indexed Addressing Mode: In this mode the content of an index register is added
to theaddress part of the instruction to obtain the effective address. The index
register is a special CPU register that contains an index value. The address field of
the instruction defines the beginning address of a data array in memory. Each
operand in the array is stored in memory relative to the beginning address. The
distance between the beginning address and the address of the operand is the index
value stores in the index register. Any operand in the array can be accessed with
the same instruction provided that the index register contains the correct index
value. The index register can be incremented to facilitate access to consecutive
operands. Note that if an index-type instruction does not include an address field in
its format, the instructionconverts to the register indirect mode of operation. Some
computers dedicate one CPU register to function solely as an index register. This
register is involved implicitly when the index-mode instruction is used. In
computers with many processor registers, any one of the CPU registers can contain
the index number. In such a case the register must be specified explicitly in a
register field within the instruction format.

10 Base Register Addressing Mode: In this mode the content of a base register is
added tothe address part of the instruction to obtain the effective address. This is
similar to the indexed addressing mode except that the register is now called a base
register instead of an index register. The difference between the two modes is in
the way they are used rather than in the way that they are computed. An index

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register is assumed to hold an index number that is relative to the address part of
the instruction. A base register is assumed to hold a base address and the address
field of the instruction gives a displacement relative to this base address. The base
register addressing mode is used in computers to facilitate the relocation of
programs in memory. When programs and data are moved from one segment of
memory to another, as required in multiprogramming systems, the address values
of the base register requires updating to reflect the beginning of a new memory
segment.

Numerical Example

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Computer Registers

„ Data Register(DR) : hold the operand(Data) read from memory

y Accumulator Register(AC) : general purpose processing register
y Instruction Register(IR) : hold the instruction read from memory
y Temporary Register(TR) : hold a temporary data during processing
y Address Register(AR) : hold a memory address, 12 bit width
y Program Counter(PC) :
»hold the address of the next instruction to be read from memory
after the current instruction is executed
»Instruction words are read and executed in sequence unless a branch
instruction is encountered
»A branch instruction calls for a transfer to a nonconsecutive
instruction in the program
»The address part of a branch instruction is transferred to PC to become
the address of the next instruction
Input Register(INPR) : receive an 8-bit character from an input device
y Output Register(OUTR) : hold an 8-bit character for an
output device
The following registers are used in Mano’s example computer.

Register Number Register Register

symbol of bits name Function-----------------------

DR 16 Data register Holds memory operands

AR 12 Address register Holds address for memory

AC 16 Accumulator Processor register

IR 16 Instruction register Holds instruction code

PC 12 Program counter Holds address of instruction

TR 16 Temporary register Holds temporary data

INPR 8 Input register Holds input character

OUTR 8 Output register Holds output character

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Computer Instructions:
The basic computer has 16 bit instruction register (IR) which can denote either
memory reference or register reference or input-output instruction.
1. Memory Reference – These instructions refer to memory address as an
operand. The other operand is always accumulator. Specifies 12 bit
address, 3 bit opcode (other than 111) and 1 bit addressing mode for direct
and indirect addressing.
Example –
IR register contains = 0001XXXXXXXXXXXX, i.e. ADD after fetching
and decoding of instruction we find out that it is a memory reference
instruction for ADD operation.
Hence, DR <- M[AR]
AC <- AC+ DR, SC <- 0
2. Register Reference – These instructions perform operations on registers
rather than memory addresses. The IR(14-12) is 111 (differentiates it from
memory reference) and IR(15) is 0 (differentiates it from input/output
instructions). The rest 12 bits specify register operation.
Example –
IR register contains = 0111001000000000, i.e. CMA after fetch and decode
cycle we find out that it is a register reference instruction for complement
accumulator.
Hence, AC <- ~AC
3. Input/Output – These instructions are for communication between
computer and outside environment. The IR(14-12) is 111 (differentiates it
from memory reference) and IR(15) is 1 (differentiates it from register
reference instructions). The rest 12 bits specify I/O operation.
Example –
IR register contains = 1111100000000000, i.e. INP after fetch and decode
cycle we find out that it is an input/output instruction for inputing
character. Hence, INPUT character from peripheral device.

Timing and Control

All sequential circuits in the Basic Computer CPU are driven by a master clock,
with the exception of the INPR register. At each clock pulse, the control unit
sends control signals to control inputs of the bus, the registers, and the ALU.
Control unit design and implementation can be done by two general methods:
x A hardwired control unit is designed from scratch using traditional digital
logic design techniques to produce a minimal, optimized circuit. In other
words, the control unit is like an ASIC (application-specific integrated
circuit).
x A microprogrammed control unit is built from some sort of ROM. The
desired control signals are simply stored in the ROM, and retrieved in
sequence to drive the microoperations needed by a particular instruction.

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Instruction Cycle

The CPU performs a sequence of microoperations for each instruction. The

sequence for each instruction of the Basic Computer can be refined into 4
abstract phases:

1. Fetch instruction
2. Decode
3. Fetch operand
4. Execute

Program execution can be represented as a top-down design:

1. Program execution
a. Instruction 1
i. Fetch instruction
ii. Decode
iii. Fetch operand
iv. Execute
b. Instruction 2
i. Fetch instruction
ii. Decode
iii. Fetch operand
iv. Execute
c. Instruction 3 ...

Program execution begins with:

PC ← address of first instruction, SC ← 0

After this, the SC is incremented at each clock cycle until an instruction is

completed, and then it is cleared to begin the next instruction. This process
repeats until a HLT instruction is executed, or until the power is shut off.

Instruction Fetch and Decode

The instruction fetch and decode phases are the same for all instructions, so the
control functions and microoperations will be independent of the instruction
code.
Everything that happens in this phase is driven entirely by timing variables T 0,
T1 and T2. Hence, all control inputs in the CPU during fetch and decode are
functions of these three variables alone.

T0: AR ← PC

T1: IR ← M[AR], PC ← PC + 1

T2: D0-7 ← decoded IR(12-14), AR ← IR(0-11), I ← IR(15)

For every timing cycle, we assume SC ← SC + 1 unless it is stated that SC ← 0.

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