X5R Dielectric

General Specifications
GENERAL DESCRIPTION
• General Purpose Dielectric for Ceramic Capacitors
• EIA Class II Dielectric
• Temperature variation of capacitance is within ±15%
from -55°C to +85°C
• Well suited for decoupling and filtering applications
• Available in High Capacitance values (up to 100µF)

PART NUMBER (see page 2 for complete part number explanation)

2220 6 D 107 M A T 2 A

Size Voltage Dielectric Capacitance Capacitance Failure Terminations Packaging Special

(L" x W") 4 = 4V D = X5R Code (In pF) Tolerance Rate 2 = 7" Reel Code
T = Plated Ni
6 = 6.3V 2 Sig. Digits + K = ±10% A = N/A 4 = 13" Reel A = Std.
and Sn
Z = 10V Number of M = ±20% 7 = Bulk Cass.
Y = 16V Zeros 9 = Bulk
3 = 25V
D = 35V

TYPICAL ELECTRICAL CHARACTERISTICS

Temperature Coefficient Insulation Resistance vs Temperature

Insulation Resistance (Ohm-Farads)

20 10,000

15

10
%
Capacitance

5 1,000

-5
100
-10

-15
-20
-60 -40 -20 0 +20 +40 +60 +80 0
0 20 40 60 80 100 120
Temperature °C Temperature °C

15
X5R Dielectric
Specifications and Test Methods
Parameter/Test X5R Specification Limits Measuring Conditions
Operating Temperature Range -55ºC to +85ºC Temperature Cycle Chamber
Capacitance Within specified tolerance
≤ 2.5% for ≥ 50V DC rating Freq.: 1.0 kHz ± 10%
Dissipation Factor ≤ 3.0% for 25V DC rating Voltage: 1.0Vrms ± .2V
≤ 3.5% for 16V DC rating For Cap > 10 µF, 0.5Vrms @ 120Hz
≤ 5.0% for ≤ 10V DC rating
100,000MΩ or 500MΩ - µF, Charge device with rated voltage for
Insulation Resistance whichever is less 60 ± 5 secs @ room temp/humidity
Charge device with 300% of rated voltage for
Dielectric Strength No breakdown or visual defects 1-5 seconds, w/charge and discharge current
limited to 50 mA (max)
Appearance No defects Deflection: 2mm
Capacitance ≤ ±12% Test Time: 30 seconds
Resistance to Variation 1mm/sec
Flexure Dissipation
Stresses Factor Meets Initial Values (As Above)
Insulation
Resistance ≥ Initial Value x 0.3 90 mm
≥ 95% of each terminal should be covered Dip device in eutectic solder at 230 ± 5ºC
Solderability with fresh solder for 5.0 ± 0.5 seconds
Appearance No defects, <25% leaching of either end terminal
Capacitance ≤ ±7.5%
Variation
Dip device in eutectic solder at 260ºC for 60
Dissipation
Resistance to Meets Initial Values (As Above) seconds. Store at room temperature for 24 ± 2
Factor
Solder Heat hours before measuring electrical properties.
Insulation
Resistance Meets Initial Values (As Above)
Dielectric
Strength Meets Initial Values (As Above)
Appearance No visual defects Step 1: -55ºC ± 2º 30 ± 3 minutes
Capacitance ≤ ±7.5% Step 2: Room Temp ≤ 3 minutes
Variation
Dissipation
Thermal Meets Initial Values (As Above) Step 3: +85ºC ± 2º 30 ± 3 minutes
Factor
Shock
Insulation
Resistance Meets Initial Values (As Above) Step 4: Room Temp ≤ 3 minutes
Dielectric Repeat for 5 cycles and measure after
Strength Meets Initial Values (As Above) 24 ± 2 hours at room temperature
Appearance No visual defects
Capacitance Charge device with twice rated voltage in
≤ ±12.5%
Variation test chamber set at 85ºC ± 2ºC
Dissipation for 1000 hours (+48, -0)
Load Life Factor ≤ Initial Value x 2.0 (See Above)
Insulation Remove from test chamber and stabilize
Resistance ≥ Initial Value x 0.3 (See Above) at room temperature for 24 ± 2 hours
Dielectric before measuring.
Strength Meets Initial Values (As Above)
Appearance No visual defects
Store in a test chamber set at 85ºC ± 2ºC/
Capacitance ≤ ±12.5% 85% ± 5% relative humidity for 1000 hours
Variation
(+48, -0) with rated voltage applied.
Load Dissipation
Humidity Factor ≤ Initial Value x 2.0 (See Above)
Remove from chamber and stabilize at
Insulation
Resistance ≥ Initial Value x 0.3 (See Above) room temperature and humidity for
24 ± 2 hours before measuring.
Dielectric
Strength Meets Initial Values (As Above)

16
X5R Dielectric
Capacitance Range

PREFERRED SIZES ARE SHADED

SIZE 0201 0402 0603 0805 1206 1210 1812 2220

Soldering Reflow Only Reflow Only Reflow/Wave Reflow/Wave Reflow/Wave Reflow/Wave Reflow Only Reflow Only
Packaging All Paper All Paper All Paper Paper/Embossed Paper/Embossed Paper/Embossed All Embossed All Embossed
MM 0.60 ± 0.03 1.00 ± 0.10 1.60 ± 0.15 2.01 ± 0.20 3.20 ± 0.20 3.20 ± 0.20 4.50 ± 0.30 5.70 ± 0.40
(L) Length
(in.) (0.024 ± 0.001) (0.040 ± 0.004) (0.063 ± 0.006) (0.079 ± 0.008) (0.126 ± 0.008) (0.126 ± 0.008) (0.177 ± 0.012) (0.225 ± 0.016)
MM 0.30 ± 0.03 0.50 ± 0.10 0.81 ± 0.15 1.25 ± 0.20 1.60 ± 0.20 2.50 ± 0.20 3.20 ± 0.20 5.00 ± 0.40
(W) Width
(in.) (0.011 ± 0.001) (0.020 ± 0.004) (0.032 ± 0.006) (0.049 ± 0.008) (0.063 ± 0.008) (0.098 ± 0.008) (0.126 ± 0.008) (0.197 ± 0.016)
MM 0.15 ± 0.05 0.25 ± 0.15 0.35 ± 0.15 0.50 ± 0.25 0.50 ± 0.25 0.50 ± 0.25 0.61 ± 0.36 0.64 ± 0.39
(t) Terminal
(in.) (0.006 ± 0.002) (0.010 ± 0.006) (0.014 ± 0.006) (0.020 ± 0.010) (0.020 ± 0.010) (0.020 ± 0.010) (0.024 ± 0.014) (0.025 ± 0.015)
WVDC 10 4 6.3 10 16 4 6.3 10 16 25 6.3 10 16 25 35 6.3 10 16 25 35 4 6.3 10 16 25 35 6.3 10 16 25 6.3
Cap 100
(pF) 150
220
330

470

W
L

680

1000 T
1200 A

1500 A
1800 A

2200 A t
2700 A
3300 A
3900 A
4700 A
5600 A
6800 A
8200 A
Cap. 0.010 A
(µF) 0.012
0.015
0.018
0.022
0.027 C C
0.033 C C
0.039 C C
0.047 C C
0.056 C G
0.068 C G
0.082 C G
0.10 C C C G
0.12 C G G
0.15 C G G
0.18 C G G
0.22 C G G G J N
0.27 G G G
0.33 G G G N N
0.47 G G G N N Q
0.56 G G G N M
0.68 G G G N N M
0.82 G G G N M
1.0 C G G G N N N Q Q
1.2 G N Q
1.5 G N Q
1.8 G Q
2.2 G N Q X Z
3.3 N Q
4.7 J N N Q Q Q Q Q Z
6.8 N
10 N Q Q Q X X X X Z
22 Q Z Z Z Z
47 Z Z
100 Z BB Z
WVDC 10 4 6.3 10 16 4 6.3 10 16 25 6.3 10 16 25 35 6.3 10 16 25 35 4 6.3 10 16 25 35 6.3 10 16 25 6.3
SIZE 0201 0402 0603 0805 1206 1210 1812 2220

Letter A C E G J K M N P Q X Y Z BB CC
Max. 0.33 0.56 0.71 0.86 0.94 1.02 1.27 1.40 1.52 1.78 2.29 2.54 2.79 3.05 3.175
Thickness (0.013) (0.022) (0.028) (0.034) (0.037) (0.040) (0.050) (0.055) (0.060) (0.070) (0.090) (0.100) (0.110) (0.120) (0.125)
PAPER EMBOSSED

Contact Factory for Multiples

17
Packaging of Chip Components
Automatic Insertion Packaging
TAPE & REEL QUANTITIES
All tape and reel specifications are in compliance with RS481.

8mm 12mm
Paper or Embossed Carrier 0612, 0508, 0805, 1206,
1210
Embossed Only 1812, 1825
0306 1808 2220, 2225
Paper Only 0201, 0402, 0603
Qty. per Reel/7" Reel 2,000, 3,000 or 4,000, 10,000, 15,000 3,000 500, 1,000
Contact factory for exact quantity Contact factory for exact quantity
Qty. per Reel/13" Reel 5,000, 10,000, 50,000 10,000 4,000
Contact factory for exact quantity

REEL DIMENSIONS

Tape A B* C D* N W1 W2 W3
Size(1) Max. Min. Min. Min. Max.
7.90 Min.
8mm 8.40 +1.5
-0.0 14.4 (0.311)
(0.331 +0.059
-0.0 ) (0.567) 10.9 Max.
330 1.5 13.0 +0.50
-0.20 20.2 50.0 (0.429)
(12.992) (0.059) (0.512 +0.020
-0.008 ) (0.795) (1.969)
11.9 Min.
12mm 12.4 +2.0
-0.0 18.4 (0.469)
(0.488 +0.079
-0.0 ) (0.724) 15.4 Max.
(0.607)
Metric dimensions will govern.
English measurements rounded and for reference only.
(1) For tape sizes 16mm and 24mm (used with chip size 3640) consult EIA RS-481 latest revision.

47
Embossed Carrier Configuration
8 & 12mm Tape Only
10 PITCHES CUMULATIVE
P0 TOLERANCE ON TAPE
±0.2mm (±0.008)
T2 EMBOSSMENT
D0 P2
T
DEFORMATION
BETWEEN E1
EMBOSSMENTS
A0
F W
TOP COVER E2
B1 TAPE
K0 B0

T1 P1 D1 FOR COMPONENTS
S1 CENTER LINES
OF CAVITY MAX. CAVITY 2.00 mm x 1.20 mm AND
SIZE - SEE NOTE 1 LARGER (0.079 x 0.047)
B1 IS FOR TAPE READER REFERENCE ONLY
INCLUDING DRAFT CONCENTRIC AROUND B0 User Direction of Feed

8 & 12mm Embossed Tape

Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size D0 E P0 P2 S1 Min. T Max. T1
+0.10
8mm 1.50 -0.0 1.75 ± 0.10 4.0 ± 0.10 2.0 ± 0.05 0.60 0.60 0.10
+0.004
and (0.059 -0.0 ) (0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002) (0.024) (0.024) (0.004)
12mm Max.

VARIABLE DIMENSIONS
Tape Size B1 D1 E2 F P1 R T2 W A0 B0 K0
Max. Min. Min. Min. Max.
See Note 5 See Note 2

4.35 1.00 6.25 3.50 ± 0.05 4.00 ± 0.10 25.0 2.50 Max. 8.30
8mm (0.171) (0.039) (0.246) (0.138 ± 0.002) (0.157 ± 0.004) (0.984) (0.098) (0.327) See Note 1

8.20 1.50 10.25 5.50 ± 0.05 4.00 ± 0.10 30.0 6.50 Max. 12.3
12mm (0.323) (0.059) (0.404) (0.217 ± 0.002) (0.157 ± 0.004) (1.181) (0.256) (0.484) See Note 1

8mm 4.35 1.00 6.25 3.50 ± 0.05 2.00 ± 0.10 25.0 2.50 Max. 8.30
1/2 Pitch (0.171) (0.039) (0.246) (0.138 ± 0.002) (0.079 ± 0.004) (0.984) (0.098) (0.327) See Note 1

12mm
8.20 1.50 10.25 5.50 ± 0.05 8.00 ± 0.10 30.0 6.50 Max. 12.3 See Note 1
Double
(0.323) (0.059) (0.404) (0.217 ± 0.002) (0.315 ± 0.004) (1.181) (0.256) (0.484)
Pitch
NOTES: 2. Tape with or without components shall pass around radius “R” without damage.
1. The cavity defined by A0, B0, and K0 shall be configured to provide the following: 3. Bar code labeling (if required) shall be on the side of the reel opposite the round sprocket holes.
Surround the component with sufficient clearance such that: Refer to EIA-556.
a) the component does not protrude beyond the sealing plane of the cover tape.
b) the component can be removed from the cavity in a vertical direction without mechanical 4. B1 dimension is a reference dimension for tape feeder clearance only.
restriction, after the cover tape has been removed. 5. If P1 = 2.0mm, the tape may not properly index in all tape feeders.
c) rotation of the component is limited to 20º maximum (see Sketches D & E).
d) lateral movement of the component is restricted to 0.5mm maximum (see Sketch F).

Top View, Sketch "F"

Component Lateral Movements
0.50mm (0.020)
Maximum

0.50mm (0.020)
Maximum

48
Paper Carrier Configuration
8 & 12mm Tape Only
10 PITCHES CUMULATIVE
P0 TOLERANCE ON TAPE
±0.20mm (±0.008)
T D0 P2

E1
BOTTOM TOP
COVER COVER F
TAPE W
TAPE E2
B0

G
T1 A0 P1
T1 CAVITY SIZE CENTER LINES
SEE NOTE 1 OF CAVITY User Direction of Feed

8 & 12mm Paper Tape

Metric Dimensions Will Govern
CONSTANT DIMENSIONS
Tape Size D0 E P0 P2 T1 G. Min. R Min.
+0.10
8mm 1.50 -0.0 1.75 ± 0.10 4.00 ± 0.10 2.00 ± 0.05 0.10 0.75 25.0 (0.984)
+0.004
and (0.059 -0.0 ) (0.069 ± 0.004) (0.157 ± 0.004) (0.079 ± 0.002) (0.004) (0.030) See Note 2
12mm Max. Min. Min.

VARIABLE DIMENSIONS
P1
Tape Size See Note 4 E2 Min. F W A0 B0 T

8mm 4.00 ± 0.10 6.25 3.50 ± 0.05 8.00 +0.30

-0.10 See Note 1
(0.157 ± 0.004) (0.246) (0.138 ± 0.002) (0.315 +0.012
-0.004 )
1.10mm
(0.043) Max.
4.00 ± 0.010 10.25 5.50 ± 0.05 12.0 ± 0.30 for Paper Base
12mm (0.157 ± 0.004) (0.404) (0.217 ± 0.002) (0.472 ± 0.012) Tape and

1.60mm
8mm 2.00 ± 0.05 6.25 3.50 ± 0.05 8.00 +0.30
-0.10
(0.063) Max.
1/2 Pitch (0.079 ± 0.002) (0.246) (0.138 ± 0.002) (0.315 +0.012
-0.004 )
for Non-Paper
Base Compositions
12mm
8.00 ± 0.10 10.25 5.50 ± 0.05 12.0 ± 0.30
Double
(0.315 ± 0.004) (0.404) (0.217 ± 0.002) (0.472 ± 0.012)
Pitch

NOTES: 2. Tape with or without components shall pass around radius “R” without damage.
1. The cavity defined by A0, B0, and T shall be configured to provide sufficient clearance 3. Bar code labeling (if required) shall be on the side of the reel opposite the sprocket
surrounding the component so that: holes. Refer to EIA-556.
a) the component does not protrude beyond either surface of the carrier tape;
b) the component can be removed from the cavity in a vertical direction without 4. If P1 = 2.0mm, the tape may not properly index in all tape feeders.
mechanical restriction after the top cover tape has been removed;
c) rotation of the component is limited to 20º maximum (see Sketches A & B);
d) lateral movement of the component is restricted to 0.5mm maximum
(see Sketch C).
Top View, Sketch "C"
Component Lateral
0.50mm (0.020)
Maximum

0.50mm (0.020)
Maximum

Bar Code Labeling Standard

AVX bar code labeling is available and follows latest version of EIA-556

49
Bulk Case Packaging

BENEFITS BULK FEEDER

• Easier handling
• Smaller packaging volume
(1/20 of T/R packaging)
• Easier inventory control Case
• Flexibility
• Recyclable Cassette

Gate

Shooter
CASE DIMENSIONS

Shutter
Slider
12mm

36mm
Mounter
Expanded Drawing Head

110mm Chips
Attachment Base

CASE QUANTITIES
Part Size 0402 0603 0805 1206
Qty. 10,000 (T=.023") 5,000 (T=.023")
80,000 15,000
(pcs / cassette) 8,000 (T=.031") 4,000 (T=.032")
6,000 (T=.043") 3,000 (T=.044")

50
Basic Capacitor Formulas

I. Capacitance (farads) XI. Equivalent Series Resistance (ohms)

English: C = .224 K A E.S.R. = (D.F.) (Xc) = (D.F.) / (2 π fC)
TD XII. Power Loss (watts)
Metric: C = .0884 KA Power Loss = (2 π fCV2) (D.F.)
TD
XIII. KVA (Kilowatts)
II. Energy stored in capacitors (Joules, watt - sec) KVA = 2 π fCV2 x 10 -3
E = 1⁄2 CV2
XIV. Temperature Characteristic (ppm/°C)
III. Linear charge of a capacitor (Amperes)
dV T.C. = Ct – C25 x 106
I=C C25 (Tt – 25)
dt
IV. Total Impedance of a capacitor (ohms) XV. Cap Drift (%)
Z =
R2S + (XC - XL )2
C1 – C2
C.D. = x 100
C1
V. Capacitive Reactance (ohms)
XVI. Reliability of Ceramic Capacitors
1
xc =
2 π fC
L0
Lt
= ( ) ( )
Vt
Vo
X Tt
To
Y

VI. Inductive Reactance (ohms) XVII. Capacitors in Series (current the same)
xL = 2 π fL
Any Number: 1 = 1 + 1 --- 1
VII. Phase Angles: CT C1 C2 CN
Ideal Capacitors: Current leads voltage 90° C1 C2
Ideal Inductors: Current lags voltage 90° Two: CT =
C1 + C2
Ideal Resistors: Current in phase with voltage
XVIII. Capacitors in Parallel (voltage the same)
VIII. Dissipation Factor (%)
CT = C1 + C2 --- + CN
D.F.= tan  (loss angle) = E.S.R. = (2 πfC) (E.S.R.)
Xc XIX. Aging Rate
IX. Power Factor (%) A.R. = %
P.F. = Sine  (loss angle) = Cos (phase angle) D C/decade of time
P.F. = (when less than 10%) = DF
f XX. Decibels
db = 20 log V1
X. Quality Factor (dimensionless) V2
Q = Cotan  (loss angle) = 1
D.F.

METRIC PREFIXES SYMBOLS

Pico X 10-12 K = Dielectric Constant f = frequency Lt = Test life

Nano X 10-9
A = Area L = Inductance Vt = Test voltage
Micro X 10-6
Milli X 10-3
TD = Dielectric thickness  = Loss angle Vo = Operating voltage
Deci X 10-1
Deca X 10+1
Kilo X 10+3
V = Voltage
f = Phase angle Tt = Test temperature

Mega X 10+6 t = time X&Y = exponent effect of voltage and temp. To = Operating temperature
Giga X 10+9
Tera X 10+12 Rs = Series Resistance Lo = Operating life

51
General Description

Basic Construction – A multilayer ceramic (MLC) capaci- structure requires a considerable amount of sophistication,
tor is a monolithic block of ceramic containing two sets of both in material and manufacture, to produce it in the quality
offset, interleaved planar electrodes that extend to two and quantities needed in today’s electronic equipment.
opposite surfaces of the ceramic dielectric. This simple

Electrode
Ceramic Layer

End Terminations

Terminated
Edge

Terminated
Edge
Margin Electrodes

Multilayer Ceramic Capacitor

Figure 1

Formulations – Multilayer ceramic capacitors are available Class 2 – EIA Class 2 capacitors typically are based on the
in both Class 1 and Class 2 formulations. Temperature chemistry of barium titanate and provide a wide range of
compensating formulation are Class 1 and temperature capacitance values and temperature stability. The most
stable and general application formulations are classified commonly used Class 2 dielectrics are X7R and Y5V. The
as Class 2. X7R provides intermediate capacitance values which vary
only ±15% over the temperature range of -55°C to 125°C. It
finds applications where stability over a wide temperature
Class 1 – Class 1 capacitors or temperature compensating
range is required.
capacitors are usually made from mixtures of titanates
where barium titanate is normally not a major part of the The Y5V provides the highest capacitance values and is
mix. They have predictable temperature coefficients and used in applications where limited temperature changes are
in general, do not have an aging characteristic. Thus they expected. The capacitance value for Y5V can vary from
are the most stable capacitor available. The most popular 22% to -82% over the -30°C to 85°C temperature range.
Class 1 multilayer ceramic capacitors are C0G (NP0) The Z5U dielectric is between X7R and Y5V in both stability
temperature compensating capacitors (negative-positive and capacitance range.
0 ppm/°C). All Class 2 capacitors vary in capacitance value under the
influence of temperature, operating voltage (both AC and
DC), and frequency. For additional information on perfor-
mance changes with operating conditions, consult AVX’s
software, SpiCap.

52
General Description
Effects of Voltage – Variations in voltage have little effect
Table 1: EIA and MIL Temperature Stable and General
on Class 1 dielectric but does affect the capacitance and
Application Codes dissipation factor of Class 2 dielectrics. The application of
EIA CODE DC voltage reduces both the capacitance and dissipation
Percent Capacity Change Over Temperature Range factor while the application of an AC voltage within a
reasonable range tends to increase both capacitance and
RS198 Temperature Range dissipation factor readings. If a high enough AC voltage is
X7 -55°C to +125°C applied, eventually it will reduce capacitance just as a DC
X5 -55°C to +85°C voltage will. Figure 2 shows the effects of AC voltage.
Y5 -30°C to +85°C
Z5 +10°C to +85°C Cap. Change vs. A.C. Volts
X7R
Code Percent Capacity Change

Capacitance Change Percent

D ±3.3% 50
E ±4.7%
40
F ±7.5%
P ±10% 30
R ±15%
S ±22% 20
T +22%, -33%
U +22%, - 56% 10
V +22%, -82%
0
EXAMPLE – A capacitor is desired with the capacitance value at 25°C 12.5 25 37.5 50
to increase no more than 7.5% or decrease no more than 7.5% from
-30°C to +85°C. EIA Code will be Y5F. Volts AC at 1.0 KHz
Figure 2

MIL CODE Capacitor specifications specify the AC voltage at which to

measure (normally 0.5 or 1 VAC) and application of the
Symbol Temperature Range wrong voltage can cause spurious readings. Figure 3 gives
the voltage coefficient of dissipation factor for various AC
A -55°C to +85°C voltages at 1 kilohertz. Applications of different frequencies
B -55°C to +125°C will affect the percentage changes versus voltages.
C -55°C to +150°C
Cap. Change Cap. Change D.F. vs. A.C. Measurement Volts
Symbol
Zero Volts Rated Volts X7R
10.0
R +15%, -15% +15%, -40%
Dissipation Factor Percent

Curve 1 - 100 VDC Rated Capacitor Curve 3

W +22%, -56% +22%, -66% 8.0 Curve 2 - 50 VDC Rated Capacitor
X +15%, -15% +15%, -25% Curve 3 - 25 VDC Rated Capacitor
Y +30%, -70% +30%, -80% 6.0 Curve 2
Z +20%, -20% +20%, -30%
4.0
Temperature characteristic is specified by combining range and
change symbols, for example BR or AW. Specification slash sheets
indicate the characteristic applicable to a given style of capacitor. 2.0 Curve 1

0
In specifying capacitance change with temperature for Class .5 1.0 1.5 2.0 2.5
2 materials, EIA expresses the capacitance change over an AC Measurement Volts at 1.0 KHz
operating temperature range by a 3 symbol code. The first Figure 3
symbol represents the cold temperature end of the temper-
ature range, the second represents the upper limit of the Typical effect of the application of DC voltage is shown in
operating temperature range and the third symbol repre- Figure 4. The voltage coefficient is more pronounced for
sents the capacitance change allowed over the higher K dielectrics. These figures are shown for room tem-
operating temperature range. Table 1 provides a detailed perature conditions. The combination characteristic known
explanation of the EIA system. as voltage temperature limits which shows the effects of
rated voltage over the operating temperature range is
shown in Figure 5 for the military BX characteristic.

53
General Description

Typical Cap. Change vs. D.C. Volts tends to de-age capacitors and is why re-reading of capaci-
X7R tance after 12 or 24 hours is allowed in military specifica-
tions after dielectric strength tests have been performed.
2.5
Capacitance Change Percent

Typical Curve of Aging Rate

0 X7R
-2.5 +1.5

-5
0

Capacitance Change Percent

-7.5
-1.5
-10
25% 50% 75% 100%
Percent Rated Volts -3.0
Figure 4
-4.5
Typical Cap. Change vs. Temperature
X7R
-6.0
Capacitance Change Percent

+20 -7.5
1 10 100 1000 10,000 100,000
+10 Hours
0VDC Characteristic Max. Aging Rate %/Decade
0 C0G (NP0) None
X7R, X5R 2
-10 Y5V 7

-20 Figure 6
-30 Effects of Frequency – Frequency affects capacitance
-55 -35 -15 +5 +25 +45 +65 +85 +105 +125 and impedance characteristics of capacitors. This effect is
Temperature Degrees Centigrade much more pronounced in high dielectric constant ceramic
Figure 5 formulation that is low K formulations. AVX’s SpiCap soft-
ware generates impedance, ESR, series inductance, series
Effects of Time – Class 2 ceramic capacitors change resonant frequency and capacitance all as functions of
capacitance and dissipation factor with time as well as tem- frequency, temperature and DC bias for standard chip sizes
perature, voltage and frequency. This change with time is and styles. It is available free from AVX and can be down-
known as aging. Aging is caused by a gradual re-alignment loaded for free from AVX website: www.avxcorp.com.
of the crystalline structure of the ceramic and produces an
exponential loss in capacitance and decrease in dissipation
factor versus time. A typical curve of aging rate for semi-
stable ceramics is shown in Figure 6.
If a Class 2 ceramic capacitor that has been sitting on the
shelf for a period of time, is heated above its curie point,
(125°C for 4 hours or 150°C for 1⁄2 hour will suffice) the part
will de-age and return to its initial capacitance and dissi-
pation factor readings. Because the capacitance changes
rapidly, immediately after de-aging, the basic capacitance
measurements are normally referred to a time period some-
time after the de-aging process. Various manufacturers use
different time bases but the most popular one is one day
or twenty-four hours after “last heat.” Change in the aging
curve can be caused by the application of voltage and
other stresses. The possible changes in capacitance due to
de-aging by heating the unit explain why capacitance
changes are allowed after test, such as temperature cycling,
moisture resistance, etc., in MIL specs. The application of
high voltages such as dielectric withstanding voltages also

54
General Description

Effects of Mechanical Stress – High “K” dielectric Energy Stored – The energy which can be stored in a
ceramic capacitors exhibit some low level piezoelectric capacitor is given by the formula:
reactions under mechanical stress. As a general statement,
the piezoelectric output is higher, the higher the dielectric E = 1⁄2CV2
constant of the ceramic. It is desirable to investigate this
effect before using high “K” dielectrics as coupling capaci-
tors in extremely low level applications. E = energy in joules (watts-sec)
Reliability – Historically ceramic capacitors have been one V = applied voltage
of the most reliable types of capacitors in use today. C = capacitance in farads
The approximate formula for the reliability of a ceramic Potential Change – A capacitor is a reactive component
capacitor is: which reacts against a change in potential across it. This is


Lo Vt X Tt Y
shown by the equation for the linear charge of a capacitor:
=
Lt Vo To
I ideal = C dV
where dt
Lo = operating life Tt = test temperature and where
Lt = test life To = operating temperature
I = Current
Vt = test voltage in °C
C = Capacitance
Vo = operating voltage X,Y = see text
dV/dt = Slope of voltage transition across capacitor
Thus an infinite current would be required to instantly
Historically for ceramic capacitors exponent X has been
change the potential across a capacitor. The amount of
considered as 3. The exponent Y for temperature effects
current a capacitor can “sink” is determined by the above
typically tends to run about 8.
equation.
Equivalent Circuit – A capacitor, as a practical device,
A capacitor is a component which is capable of storing exhibits not only capacitance but also resistance and
electrical energy. It consists of two conductive plates (elec- inductance. A simplified schematic for the equivalent circuit
trodes) separated by insulating material which is called the is:
dielectric. A typical formula for determining capacitance is:
C = Capacitance L = Inductance
Rs = Series Resistance Rp = Parallel Resistance
C = .224 KA
t RP
C = capacitance (picofarads)
K = dielectric constant (Vacuum = 1)
A = area in square inches
t = separation between the plates in inches L RS
(thickness of dielectric)
.224 = conversion constant C
(.0884 for metric system in cm) Reactance – Since the insulation resistance (Rp) is normal-
Capacitance – The standard unit of capacitance is the ly very high, the total impedance of a capacitor is:
farad. A capacitor has a capacitance of 1 farad when 1

coulomb charges it to 1 volt. One farad is a very large unit
and most capacitors have values in the micro (10-6), nano Z= R 2S + (XC - XL )2
(10-9) or pico (10-12) farad level. where
Dielectric Constant – In the formula for capacitance given Z = Total Impedance
above the dielectric constant of a vacuum is arbitrarily cho- Rs = Series Resistance
sen as the number 1. Dielectric constants of other materials XC = Capacitive Reactance = 1
are then compared to the dielectric constant of a vacuum. 2 π fC
XL = Inductive Reactance = 2 π fL
Dielectric Thickness – Capacitance is indirectly propor-
tional to the separation between electrodes. Lower voltage The variation of a capacitor’s impedance with frequency
requirements mean thinner dielectrics and greater capaci- determines its effectiveness in many applications.
tance per volume. Phase Angle – Power Factor and Dissipation Factor are
Area – Capacitance is directly proportional to the area of often confused since they are both measures of the loss in
the electrodes. Since the other variables in the equation are a capacitor under AC application and are often almost
usually set by the performance desired, area is the easiest identical in value. In a “perfect” capacitor the current in the
parameter to modify to obtain a specific capacitance within capacitor will lead the voltage by 90°.
a material group.

55
General Description

di
I (Ideal) The dt seen in current microprocessors can be as high as
I (Actual) 0.3 A/ns, and up to 10A/ns. At 0.3 A/ns, 100pH of parasitic
inductance can cause a voltage spike of 30mV. While this
does not sound very drastic, with the Vcc for microproces-
Loss sors decreasing at the current rate, this can be a fairly large
Phase
Angle  percentage.
Angle
Another important, often overlooked, reason for knowing
the parasitic inductance is the calculation of the resonant
f frequency. This can be important for high frequency, by-
pass capacitors, as the resonant point will give the most
V signal attenuation. The resonant frequency is calculated
IR s from the simple equation:
In practice the current leads the voltage by some other fres = 1
2
LC
phase angle due to the series resistance RS. The comple-
ment of this angle is called the loss angle and:
Insulation Resistance – Insulation Resistance is the
Power Factor (P.F.) = Cos f or Sine  resistance measured across the terminals of a capacitor
Dissipation Factor (D.F.) = tan  and consists principally of the parallel resistance R P shown
in the equivalent circuit. As capacitance values and hence
the area of dielectric increases, the I.R. decreases and
for small values of  the tan and sine are essentially equal hence the product (C x IR or RC) is often specified in ohm
which has led to the common interchangeability of the two faradsor more commonly megohm-microfarads. Leakage
terms in the industry. current is determined by dividing the rated voltage by IR
(Ohm’s Law).
Equivalent Series Resistance – The term E.S.R. or
Dielectric Strength – Dielectric Strength is an expression
Equivalent Series Resistance combines all losses both
of the ability of a material to withstand an electrical stress.
series and parallel in a capacitor at a given frequency so
Although dielectric strength is ordinarily expressed in volts, it
that the equivalent circuit is reduced to a simple R-C series
is actually dependent on the thickness of the dielectric and
connection.
thus is also more generically a function of volts/mil.
Dielectric Absorption – A capacitor does not discharge
instantaneously upon application of a short circuit, but
drains gradually after the capacitance proper has been dis-
E.S.R. C charged. It is common practice to measure the dielectric
absorption by determining the “reappearing voltage” which
appears across a capacitor at some point in time after it has
Dissipation Factor – The DF/PF of a capacitor tells what
been fully discharged under short circuit conditions.
percent of the apparent power input will turn to heat in the
capacitor. Corona – Corona is the ionization of air or other vapors
which causes them to conduct current. It is especially
Dissipation Factor = E.S.R. = (2 π fC) (E.S.R.) prevalent in high voltage units but can occur with low voltages
XC
as well where high voltage gradients occur. The energy
The watts loss are: discharged degrades the performance of the capacitor and
can in time cause catastrophic failures.
Watts loss = (2 π fCV2 ) (D.F.)
Very low values of dissipation factor are expressed as their
reciprocal for convenience. These are called the “Q” or
Quality factor of capacitors.
Parasitic Inductance – The parasitic inductance of capac-
itors is becoming more and more important in the decou-
pling of today’s high speed digital systems. The relationship
between the inductance and the ripple voltage induced on
the DC voltage line can be seen from the simple inductance
equation:
V = L di
dt

56
Surface Mounting Guide
MLC Chip Capacitors
REFLOW SOLDERING

Case Size D1 D2 D3 D4 D5
D2
0402 1.70 (0.07) 0.60 (0.02) 0.50 (0.02) 0.60 (0.02) 0.50 (0.02)
0603 2.30 (0.09) 0.80 (0.03) 0.70 (0.03) 0.80 (0.03) 0.75 (0.03)
D1 D3 0805 3.00 (0.12) 1.00 (0.04) 1.00 (0.04) 1.00 (0.04) 1.25 (0.05)
1206 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 1.60 (0.06)
1210 4.00 (0.16) 1.00 (0.04) 2.00 (0.09) 1.00 (0.04) 2.50 (0.10)
D4
1808 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 2.00 (0.08)
1812 5.60 (0.22) 1.00 (0.04)) 3.60 (0.14) 1.00 (0.04) 3.00 (0.12)
D5 1825 5.60 (0.22) 1.00 (0.04) 3.60 (0.14) 1.00 (0.04) 6.35 (0.25)
2220 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 5.00 (0.20)
Dimensions in millimeters (inches) 2225 6.60 (0.26) 1.00 (0.04) 4.60 (0.18) 1.00 (0.04) 6.35 (0.25)

Component Pad Design

Component pads should be designed to achieve good • Pad width equal to component width. It is permissible to
solder filets and minimize component movement during decrease this to as low as 85% of component width but it
reflow soldering. Pad designs are given below for the most is not advisable to go below this.
common sizes of multilayer ceramic capacitors for both • Pad overlap 0.5mm beneath component.
wave and reflow soldering. The basis of these designs is:
• Pad extension 0.5mm beyond components for reflow and
1.0mm for wave soldering.

WAVE SOLDERING
D2
Case Size D1 D2 D3 D4 D5
D1 D3 0603 3.10 (0.12) 1.20 (0.05) 0.70 (0.03) 1.20 (0.05) 0.75 (0.03)
0805 4.00 (0.15) 1.50 (0.06) 1.00 (0.04) 1.50 (0.06) 1.25 (0.05)
D4 1206 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 1.60 (0.06)
1210 5.00 (0.19) 1.50 (0.06) 2.00 (0.09) 1.50 (0.06) 2.50 (0.10)
D5
Dimensions in millimeters (inches)

Component Spacing Preheat & Soldering

For wave soldering components, must be spaced sufficiently The rate of preheat should not exceed 4°C/second to
far apart to avoid bridging or shadowing (inability of solder prevent thermal shock. A better maximum figure is about
to penetrate properly into small spaces). This is less impor- 2°C/second.
tant for reflow soldering but sufficient space must be
For capacitors size 1206 and below, with a maximum
allowed to enable rework should it be required.
thickness of 1.25mm, it is generally permissible to allow a
temperature differential from preheat to soldering of 150°C.
In all other cases this differential should not exceed 100°C.
For further specific application or process advice, please
consult AVX.
Cleaning
≥1.5mm (0.06) Care should be taken to ensure that the capacitors are
thoroughly cleaned of flux residues especially the space
≥1mm (0.04)
beneath the capacitor. Such residues may otherwise
become conductive and effectively offer a low resistance
bypass to the capacitor.
≥1mm (0.04)
Ultrasonic cleaning is permissible, the recommended
conditions being 8 Watts/litre at 20-45 kHz, with a process
cycle of 2 minutes vapor rinse, 2 minutes immersion in the
ultrasonic solvent bath and finally 2 minutes vapor rinse.

57
Surface Mounting Guide
MLC Chip Capacitors
APPLICATION NOTES General
Surface mounting chip multilayer ceramic capacitors
Storage are designed for soldering to printed circuit boards or other
Good solderability is maintained for at least twelve months, substrates. The construction of the components is such that
provided the components are stored in their “as received” they will withstand the time/temperature profiles used in both
packaging at less than 40°C and 70% RH. wave and reflow soldering methods.
Solderability Handling
Terminations to be well soldered after immersion in a 60/40 Chip multilayer ceramic capacitors should be handled with
tin/lead solder bath at 235 ± 5°C for 2 ± 1 seconds. care to avoid damage or contamination from perspiration
and skin oils. The use of tweezers or vacuum pick ups
Leaching is strongly recommended for individual components. Bulk
Terminations will resist leaching for at least the immersion handling should ensure that abrasion and mechanical shock
times and conditions shown below. are minimized. Taped and reeled components provides the
ideal medium for direct presentation to the placement
Termination Type Solder Solder Immersion Time
Tin/Lead/Silver Temp. °C Seconds machine. Any mechanical shock should be minimized during
handling chip multilayer ceramic capacitors.
Nickel Barrier 60/40/0 260 ± 5 30 ± 1
Preheat
Recommended Soldering Profiles It is important to avoid the possibility of thermal shock during
soldering and carefully controlled preheat is therefore
Reflow required. The rate of preheat should not exceed 4°C/second
and a target figure 2°C/second is recommended. Although
300
Natural
an 80°C to 120°C temperature differential is preferred,
Preheat
Cooling recent developments allow a temperature differential
250 between the component surface and the soldering temper-
ature of 150°C (Maximum) for capacitors of 1210 size and
200 below with a maximum thickness of 1.25mm. The user is
Solder Temp.

cautioned that the risk of thermal shock increases as chip

220°C size or temperature differential increases.
150 to
250°C
Soldering
100
Mildly activated rosin fluxes are preferred. The minimum
amount of solder to give a good joint should be used.
50 Excessive solder can lead to damage from the stresses
caused by the difference in coefficients of expansion
0 between solder, chip and substrate. AVX terminations are
1min 1min 10 sec. max suitable for all wave and reflow soldering systems. If hand
(Minimize soldering time)
soldering cannot be avoided, the preferred technique is the
utilization of hot air soldering tools.
Wave Cooling
Natural cooling in air is preferred, as this minimizes stresses
300
Preheat within the soldered joint. When forced air cooling is used,
Natural cooling rate should not exceed 4°C/second. Quenching
250 Cooling
is not recommended but if used, maximum temperature
differentials should be observed according to the preheat
200 T
Solder Temp.

conditions above.
150 230°C Cleaning
to
250°C Flux residues may be hygroscopic or acidic and must be
100 removed. AVX MLC capacitors are acceptable for use with
all of the solvents described in the specifications MIL-STD-
50 202 and EIA-RS-198. Alcohol based solvents are acceptable
and properly controlled water cleaning systems are also
0
acceptable. Many other solvents have been proven successful,
and most solvents that are acceptable to other components
1 to 2 min 3 sec. max on circuit assemblies are equally acceptable for use with
(Preheat chips before soldering) ceramic capacitors.
T/maximum 150°C

58
Surface Mounting Guide
MLC Chip Capacitors
POST SOLDER HANDLING COMMON CAUSES OF
Once SMP components are soldered to the board, any MECHANICAL CRACKING
bending or flexure of the PCB applies stresses to the sol-
The most common source for mechanical stress is board
dered joints of the components. For leaded devices, the
depanelization equipment, such as manual breakapart, v-
stresses are absorbed by the compliancy of the metal leads
cutters and shear presses. Improperly aligned or dull cutters
and generally don’t result in problems unless the stress is
may cause torqueing of the PCB resulting in flex stresses
large enough to fracture the soldered connection.
being transmitted to components near the board edge.
Ceramic capacitors are more susceptible to such stress Another common source of flexural stress is contact during
because they don’t have compliant leads and are brittle in parametric testing when test points are probed. If the PCB
nature. The most frequent failure mode is low DC resistance is allowed to flex during the test cycle, nearby ceramic
or short circuit. The second failure mode is significant loss capacitors may be broken.
of capacitance due to severing of contact between sets of
A third common source is board to board connections at
the internal electrodes.
vertical connectors where cables or other PCBs are con-
Cracks caused by mechanical flexure are very easily identi- nected to the PCB. If the board is not supported during the
fied and generally take one of the following two general plug/unplug cycle, it may flex and cause damage to nearby
forms: components.
Special care should also be taken when handling large (>6"
on a side) PCBs since they more easily flex or warp than
smaller boards.

REWORKING OF MLCs
Thermal shock is common in MLCs that are manually
attached or reworked with a soldering iron. AVX strongly
recommends that any reworking of MLCs be done with hot
Type A: air reflow rather than soldering irons. It is practically impossi-
Angled crack between bottom of device to top of solder joint. ble to cause any thermal shock in ceramic capacitors when
using hot air reflow.
However direct contact by the soldering iron tip often caus-
es thermal cracks that may fail at a later date. If rework by
soldering iron is absolutely necessary, it is recommended
that the wattage of the iron be less than 30 watts and the
tip temperature be <300ºC. Rework should be performed
by applying the solder iron tip to the pad and not directly
contacting any part of the ceramic capacitor.

Type B:
Fracture from top of device to bottom of device.

Mechanical cracks are often hidden underneath the termi-

nation and are difficult to see externally. However, if one end
termination falls off during the removal process from PCB,
this is one indication that the cause of failure was excessive
mechanical stress due to board warping.

59
Surface Mounting Guide
MLC Chip Capacitors

Solder Tip Solder Tip

Preferred Method - No Direct Part Contact Poor Method - Direct Contact with Part

PCB BOARD DESIGN

To avoid many of the handling problems, AVX recommends that MLCs be located at least .2" away from nearest edge of
board. However when this is not possible, AVX recommends that the panel be routed along the cut line, adjacent to where the
MLC is located.

No Stress Relief for MLCs Routed Cut Line Relieves Stress on MLC

60