CPEN 211: Introduction to Microcomputers

Slide Set 10:

Adder Circuits, Two’s Complement

Prof. Tor Aamodt

[ Background image: Logic gate diagram for a portion of the PDP 11 data path; The PDP 11 was a famous “minicomputer” from the 1970s.
Copyright © DEC. Source: http://www.psych.usyd.edu.au/pdp-11/Images/11_20_dp.gif ]
 Learning Objectives
By the end of this slide set you should be able to:
1. Explain how addition is performed using
combinational logic
2. Represent negative numbers in 2’s complement
3. Build an efficient adder/subtractor unit

Slide Set #10 2

 Addition
• We can design an iterative combinational logic
circuit to perform addition…
• Inputs:
A = (an-1,an-2,…,a1,a0)
B = (bn-1,bn-2,…,b1,b0)
• Output:
Sum = (sn-1,sn-2,…,s1,s0)
• Carry?
Slide Set #10 3
Binary addition
1-bit 0+0 = 0, 1+0 = 1, 1+1 = 10

110_
10_
0_ 111_
11_
1_
6 110 5 101
+ 3 011 +7 111
9 1001
001
01
1 12 1100
100
00
0

carry-in carry-out

c[i] b[i] a[i] count c[i+1] s[i]

0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 1 0 1
0 1 1 2 1 0
1 0 0 1 0 1
1 0 1 2 1 0
1 1 0 2 1 0
1 1 1 3 1 1

Slide Set #10 4

Text: Dally §10.2
 One bit of an adder
• Counts the number of “1” bits on its input
• Outputs the result in binary
• For a half-adder, 2 inputs, output can be 0, 1, or 2
• For a full-adder, 3 inputs, output can be 0, 1, 2, or 3

c[i] b[i] a[i] count c[i+1] s[i]

0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 1 0 1
0 1 1 2 1 0
1 0 0 1 0 1
1 0 1 2 1 0
1 1 0 2 1 0
1 1 1 3 1 1

Slide Set #10

Text: Dally §10.2
 Half Adder
ab cs
a c # 00 00
# 01 01
HA # 10 01
b s
# 11 10

a
c

s // half adder
b module HalfAdder(a,b,c,s);
input a,b ;
output c,s ; // carry and sum
wire s = a ^ b ;
wire c = a & b ;
endmodule
Slide Set #10 6
Text: Dally §10.2
 Full Adder
• Counts the number of “1” bits on its input
• For a full-adder, 3 inputs, output can be 0, 1, 2, or 3
c[i] b[i] a[i] count c[i+1] s[i]
0 0 0 0 0 0
0 0 1 1 0 1
0 1 0 1 0 1
0 1 1 2 1 0
1 0 0 1 0 1
1 0 1 2 1 0
1 1 0 2 1 0
1 1 1 3 1 1

Full adder symbol:

b

a
cout
cin
FA
s

Slide Set #10 7

Text: Dally §10.2
Full adder from a truth table

c[i] b[i] a[i] count c[i+1] s[i]

0 0 0 0 0 0
0 0 1 1 0 1 a
0 1 0 1 0 1 b
Majority
cout
0 1 1 2 1 0
1 0 0 1 0 1
1 0 1 2 1 0 s
cin
1 1 0 2 1 0
1 1 1 3 1 1

Slide Set #10 8

Text: Dally §10.2
 Full adder from truth table
// full adder - logical
module FullAdder2(a,b,cin,cout,s) ;
input a,b,cin ;
output cout,s ; // carry and sum
wire s = a ^ b ^ cin ;
wire cout = (a & b)|(a & cin)|(b & cin) ; // majority
endmodule

Slide Set #10 9

Text: Dally §10.2
Full Adder via Factoring
• Can build (smaller) full-adder out of half adders…
half adder
ab cs
# 00 00
# 01 01
# 10 01
# 11 10

a (1) (2)
(2) (2) (4)
a c a c
(2)
HA HA
b (1) (1)
(1) (2) (2)
b s a c b s
HA
cin (1) (1)
(1)
b s
(1) (1)

Slide Set #10 10

Text: Dally §10.2
 # 000 00
a (1) (2) g # 001 01
a c
(2) cout # 010 01
HA
b (1)
b s
(1) p
a c
(2) cp # 011 10
HA # 100 01
cin (1)
b s
(1) s # 101 10
# 110 10
# 111 11

// full adder - from half adders

module FullAdder1(a,b,cin,cout,s) ;
input a,b,cin ;
output cout,s ; // carry and sum
wire g,p ; // generate and propagate
wire cp ;
HalfAdder ha1(a,b,g,p) ;
HalfAdder ha2(cin,p,cp,s) ;
assign cout = g | cp;
endmodule

Slide Set #10 11

Text: Dally §10.2
 Adder in Verilog - behavioral

// multi-bit adder - behavioral

module Adder1(a,b,cin,cout,s) ;
parameter n = 8 ;
input [n-1:0] a, b ;
input cin ; Verilog automatically zero
output [n-1:0] s ;
output cout ; extends “cin” to be n bits
wire [n-1:0] s; for this addition.
wire cout ;

assign {cout, s} = a + b + cin ;

endmodule

Slide Set #10 12

Text: Dally §10.2
 Multi-bit Adder
110_
10_
0_
cout
6 110
+ 3 011 a[n-1] a
cout
s[n-1]
9 1001
001
01
1 FA s
b[n-1] b
cin

a[1] a
cout
s[1]
FA s
b[1] b
cin
c[1]
a[0] a
cout
s[0]
FA s
b[0] b
cin
cin

Slide Set #10 13

Text: Dally §10.2
a (1)
a c
(2) g
(2) cout
c[i]
HA
b (1) (1) p (2) cp
b s a c
HA a[i]
cin s
s[i]
(1) (1)
b s
b[i]

c[i] p

a[i] g
p[i] s[i]
b[i]
c[i+1]

g[i]
c[i+1]

p[i]: Propagate carry in position i if a[i] or b[i] is 1

g[i]: Generate carry in position i if both a[i] and b[i] are 1 14
Slide Set #10
 Ripple-carry adder – bit-slice notation

// multi-bit adder – with vectors c[i]

module Adder2(a,b,cin,cout,s) ;
parameter n = 8 ; a[i] s[i]
input [n-1:0] a, b ; b[i]
p[i]

input cin ;
output [n-1:0] s ;
output cout ;
g[i]
c[i+1]
wire [n-1:0] p = a ^ b ;
wire [n-1:0] g = a & b ;
wire [n:0] c = {g | (p & c[n-1:0]), cin} ;
wire [n-1:0] s = p ^ c[n-1:0] ;
wire cout = c[n] ;
endmodule

Slide Set #10 15

Text: Dally §10.2
 Negative Integers
• Thus far we have only addressed positive integers. What about negative numbers?

• 3 ways to represent negative integers in binary:

– Sign Magnitude
– One’s complement
– Two’s complement

• Example: Consider +23 –23

– Sign Magnitude 0 10111 1 10111
– One’s complement 0 10111 1 01000
– Two’s complement 0 10111 1 01001

Slide Set #10 16

Text: Dally §10.3
 Converting Positive to Negative
• To convert a positive number in 2’s
complement to a negative number:
invert bits and then add 1

• E.g., convert 0011 to negative number:

step 1: 1100 (flip all bits)
step 2: 1100+0001 (add one)
1101 (-3 in 2’s complement)

Slide Set #10 17

Text: Dally §10.3
 Converting Negative to Positive
• Use same operation to convert back

• E.g., convert 1101 (-3) to positive number:

step 1: 0010 (flip all bits)
step 2: 0010+0001 (add one)
0011 (3 in 2’s complement)

Slide Set #10 18

Text: Dally §10.3
 Why do we use 2’s complement?
2’s complement makes subtraction easy

Represent negative number, –x as 2n – x

All arithmetic is done modulo 2n so no adjustments are necessary

x + (– y) = (x + (2n – y)) mod 2n
consider 4-bit numbers
4 – 3 = 4 + (– 3)
= (4 + (16 – 3)) mod 16 // 4+(16-3) = 17; 17 mod 16 = 1
= 4 + (15 – 3 + 1)
= 4 + (15 – 3) + 1
= 0100 + (1111 – 0011) + 0001

= 0100 + (1100) + 0001

= 0001
Slide Set #10 19
Text: Dally §10.3
2’s Complement
1 = 0001
-1 = 1110 + 1 = 1111

7 = 0111
-7 = 1000+1 = 1001

Interesting case: -8
5-bits:
8 = 01000
-8 = 10111 + 1 = 11000

Note: Lower 4-bit same!

Want MSB to indicate

negative number, so in 4-bits:
1000 is -8

Slide Set #10 20

Text: Dally §10.3
 Value Function (2’s Complement)
Assume bi is value of ith bit in 2’s complement representation of a
number, then
n− 2
v = −2n −1bn −1 + ∑
bi 2i
i= 0

Example, n=4:
-810 = 10002 = (-23 • 1) + (0 • 20) + (0 • 21) + (0 • 20)
Slide Set #10 21
Text: Dally §10.3
 Impact of <signed> (s) in
Verilog Bit Literals…
wire [7:0] a;
assign a = <val>;

<val>
2’b10 // a == 8’b0000_0010 (zero extended)
2’b01 // a == 8’b0000_0001

2’sb10 // a == 8’b1111_1110 (sign extended)

2’sb01 // a == 8’b0000_0001

Note: “Does not work” with “x” – use {n{x}} to get n x’s.
Slide Set #10 22
2’s Complement Adder/Subtractor

a a
cout

b n out
Adder s
n b n
n cin

sub

Slide Set #10 23

Text: Dally §10.3
 Overflow
• If using 4-bits, 4 + 4 = 8 which cannot fit into 4-bit
(recall, 1000 means -8 if using 4-bit 2’s complement)
• If using 4-bits, -6 + (-3) = -9 which doesn’t fit in 4-bits
(lower 4-bits of 101112 is 01112 which is 710)

• Observation: Inputs same sign, result different sign.

Slide Set #10 24
Text: Dally §10.3
 Detecting Overflow
1 here if sign of A and B differ

1 here if sign of A and result differ

This works fine, but it turns out there is a more clever implementation
that uses fewer gates...
Slide Set #10 25
Text: Dally §10.3
 Alternative implementation
Let’s consider inputs and outputs of full-adder used to compute sign bit:
as bs cis ss cos ovf comment
0 0 0 0 0 0 Both inputs positive, no overflow, carry in = carry out
0 0 1 1 0 1 Both inputs positive, overflow, carry in != carry out
0 1 0 1 0 0 Inputs signs different, no overflow, carry in = carry out
0 1 1 0 1 0 Inputs signs different, no overflow, carry in = carry out
1 1 0 0 1 1 Both inputs negative, overflow, carry in != carry out
1 1 1 1 1 0 Both inputs negative, no overflow, carry in = carry out

c[i] b[i] a[i] count c[i+1] s[i]

0 0 0 0 0 0
0 0 1 1 0 1
So we know there is an overflow if:
0 1 0 1 0 1
0 1 1 2 1 0 carry in != carry out for the sign bit!
1 0 0 1 0 1
1 0 1 2 1 0
1 1 0 2 1 0
1 1 1 3 1 1 Slide Set #10 26
Text: Dally §10.3
 ovf

a[n-1] a
cout

b[n-1] out[n-1]
Adder s
b
cin

a[n-2:0] a
cout

b[n-2:0] n-1 out[n-2:0]

Adder s
n-1 b n-1
n-1 cin

sub

Slide Set #10 27

Text: Dally §10.3
// add a+b or subtract a-b, check for overflow
module AddSub(a,b,sub,s,ovf) ;
parameter n = 8 ;
input [n-1:0] a, b ;
input sub ; // subtract if sub=1, otherwise add
output [n-1:0] s ;
output ovf ; // 1 if overflow
wire c1, c2 ; // carry out of last two bits
wire ovf = c1 ^ c2 ; // overflow if signs don't match

// add non sign bits

Adder1 #(n-1) ai(a[n-2:0],b[n-2:0]^{n-1{sub}},sub,c1,s[n-2:0]) ;
// add sign bits
Adder1 #(1) as(a[n-1],b[n-1]^sub,c1,c2,s[n-1]) ;
endmodule
ovf

// multi-bit adder – with vectors a[n-1] cout

module Adder2(a,b,cin,cout,s) ; b[n-1]
a
Adder s
out[n-1]
b
cin

a[n-2:0] a
cout

b[n-2:0] n-1 out[n-2:0]

Adder s
n-1 b n-1
n-1 cin

sub

Slide Set #10 28

Text: Dally §10.3
 Summary
• Learned about addition and 2’s complement

Slide Set #10 29