Chapter 3

Number Representation
and
Arithmetic Circuits
 Binary numbers
Unsigned numbers
• all bits represent the magnitude of a positive integer

Signed numbers
• left-most bit represents the sign of a number
Table 3.1. Numbers in different systems.
 x 0 0 1 1
+y +0 +1 +0 +1
cs 00 01 01 10

Carry Sum

(a) The four possible cases

Carry Sum
x y c s
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

(b) Truth table

x
s
y
x s
HA
y c
c

(c) Circuit (d) Graphical symbol

Figure 3.1. Half-adder.

 Bit position i

Figure 3.2. Addition of multibit numbers

 xi yi
ci 00 01 11 10
0 1 1
ci xi yi ci + 1 si
1 1 1
0 0 0 0 0
0 0 1 0 1 si = xi ⊕ yi ⊕ ci
0 1 0 0 1
0 1 1 1 0 xi yi
1 0 0 0 1
ci 00 01 11 10
1 0 1 1 0
1 1 0 1 0 0 1
1 1 1 1 1
1 1 1 1
(a) Truth table
ci + 1 = xi yi + xi ci + yi ci

(b) Karnaugh maps

xi

yi si

ci

ci + 1

(c) Circuit

Figure 3.3. Full-adder.

 ci s si
s HA c
xi
HA c ci + 1
yi

(a) Block diagram

ci
si
xi
yi

ci + 1

(b) Detailed diagram

Figure 3.4. A decomposed implementation of the full-adder circuit.

 xn –1 yn – 1 x1 y1 x0 y0

c1
cn FA cn ” 1 c2 FA FA c0

sn – 1 s1 s0
MSB position LSB position

Figure 3.5. An n-bit ripple-carry adder.

 A : a7 a0

A : a7 a0

x7 x0 y7 y0
c7
s7 s0 0 0

x8 x1 x0 y8 y7 y0
c8
0 s8 s0

x8 x7 x0 y8 y7 y0
c8
s8 s0 P = 3 A : P9 P8 P0

(b) Efficient design

P = 3 A : P9 P8 P0

(a) Naive approach

Figure 3.6. Circuit that multiplies an eight-bit unsigned number by 3.

 bn – 1 b1 b0

Magnitude
MSB

(a) Unsigned number

bn – 1 bn – 2 b1 b0

Magnitude
Sign
0 denotes +
1 denotes – MSB

(b) Signed number

Figure 3.7. Formats for representation of integers.

Negative numbers can be represented in following ways:

• Sign and magnitude

•1’s complement

•2’s complement
 1’s complement

Let K be the negative equivalent of an n-bit positive number P.

Then, in 1’s complement representation K is obtained by

subtracting P from 2n – 1, namely

K = (2n – 1) – P

This means that K can be obtained by inverting all bits of P.

 2’s complement

Let K be the negative equivalent of an n-bit positive number P.

Then, in 2’s complement representation K is obtained by

subtracting P from 2n , namely

K = 2n – P
 Deriving 2’s complement

For a positive n-bit number P, let K1 and K2 denote its 1’s

and 2’s complements, respectively.

K1 = (2n – 1) – P
K2 = 2n – P

Since K2 = K1 + 1, it is evident that in a logic circuit the 2’s

complement can computed by inverting all bits of P and then
adding 1 to the resulting 1’s-complement number.
Table 3.2. Interpretation of four-bit signed integers.
 (+ 5) 0101 (– 5 ) 1010
+ (+ 2) +0010 + (+ 2) +0010
(+ 7) 0111 (- 3 ) 1100

(+ 5) 0101 (–5 ) 1010

+ (– 2) +1101 + (– 2 ) +1101
(+ 3) 10010 (–7 ) 10111
1 1
0011 1000

Figure 3.8. Examples of 1’s complement addition.

 ( + 5) 0101 (–5) 1011
+ ( + 2) + 0010 + ( + 2) + 0010
( + 7) 0111 (–3) 1101

( + 5) 0101 (–5) 1011

+ (–2) + 1110 + (–2) + 1110
( + 3) 10011 (–7) 11 0 0 1

ignore ignore

Figure 3.9. Examples of 2’s complement addition.

 ( + 5) 0101 0101
– ( + 2) – 0010 + 1110
( + 3) 10011

ignore

(–5) 1011 1011

– ( + 2) – 0010 + 1110
(–7) 11001

ignore

( + 5) 0101 0101
– (–2) – 1110 + 0010
( + 7) 0111

(–5) 1011 1011

– (–2) – 1110 + 0010
(–3) 1101

Figure 3.10. Examples of 2’s complement subtraction.

Graphical interpretation of four-bit 2’s complement numbers
 yn – 1 y1 y0

Add ⁄ Sub
control

xn – 1 x1 x0

cn n-bit adder c0

sn – 1 s1 s0

Figure 3.12. Adder/subtractor unit.

 ( + 7) 0111 (–7) 1001
+ ( + 2) + 0010 + ( + 2) + 0010
( + 9) 1001 (–5) 1011
c4 = 0 c4 = 0
c3 = 1 c3 = 0

( + 7) 0111 (–7) 1001

+ ( – 2) + 1110 + (–2) + 1110
( + 5) 10101 (–9) 10 1 1 1
c4 = 1 c4 = 1
c3 = 1 c3 = 0

Figure 3.13. Examples of determination of overflow.

 x1 y1 x0 y0

g1 p1 g0 p0
c1
c2 c0

Stage 1 Stage 0

s1 s0

Figure 3.14. A ripple-carry adder based on Expression 3.3.

 x1 y1 x0 y0

x0 y0

g1 p1 g0 p0

c0
c2
c1

s1 s0

Figure 3.15. The first two stages of a carry-lookahead adder.

 x31 – 24 y31 – 24 x15 – 8 y15 – 8 x7 – 0 y7 – 0

c8
c32 Block c24 c16 Block Block c0
3 1 0

s31 – 24 s15 – 8 s7 – 0

Figure 3.16. A hierarchical carry-lookahead adder with

ripple-carry between blocks.
 x31 – 24 y31 – 24 x15 – 8 y15 – 8 x7 – 0 y7 – 0

Block Block Block c0

3 c24 1 0

G3 P3 G1 P1 G0 P0

s31 – 24 s15 – 8 s7 – 0

c32 c16 c8

Second-level lookahead

Figure 3.17. A hierarchical carry-lookahead adder.

 module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;

xor (s, x, y, Cin);

and (z1, x, y);
and (z2, x, Cin);
and (z3, y, Cin);
or (Cout, z1, z2, z3);

endmodule

Figure 3.18. Verilog code for the full-adder using gate level primitives.
 module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;

xor (s, x, y, Cin);

and (z1, x, y),
(z2, x, Cin),
(z3, y, Cin);
or (Cout, z1, z2, z3);

endmodule

Figure 3.19. Another version of Verilog code from Figure 3.18.

 module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin;
assign Cout = (x & y) | (x & Cin) | (y & Cin);

endmodule

Figure 3.20. Verilog code for the full-adder using continuous assignment.
 module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin,
Cout = (x & y) | (x & Cin) | (y & Cin);

endmodule

Figure 3.21. Another version of Verilog code from Figure 3.20.

module adder4 (carryin, x3, x2, x1, x0, y3, y2, y1, y0, s3, s2, s1, s0, carryout);
input carryin, x3, x2, x1, x0, y3, y2, y1, y0;
output s3, s2, s1, s0, carryout;

fulladd stage0 (carryin, x0, y0, s0, c1);

fulladd stage1 (c1, x1, y1, s1, c2);
fulladd stage2 (c2, x2, y2, s2, c3);
fulladd stage3 (c3, x3, y3, s3, carryout);

endmodule

module fulladd (Cin, x, y, s, Cout);

input Cin, x, y;
output s, Cout;

assign s = x ^ y ^ Cin,
assign Cout = (x & y) | (x & Cin) | (y & Cin);

endmodule

Figure 3.22. Verilog code for a four-bit adder.

module adder4 (carryin, X, Y, S, carryout);
input carryin;
input [3:0] X, Y;
output [3:0] S;
output carryout;
wire [3:1] C;

fulladd stage0 (carryin, X[0], Y[0], S[0], C[1]);

fulladd stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladd stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], Y[3], S[3], carryout);

endmodule

Figure 3.23. A four-bit adder using vectors.

 module addern (carryin, X, Y, S, carryout);
parameter n=32;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;
output reg carryout;
reg [n:0] C;
integer k;

always @(X, Y, carryin)

begin
C[0] = carryin;
for (k = 0; k < n; k = k+1)
begin
S[k] = X[k] ^ Y[k] ^ C[k];
C[k+1] = (X[k] & Y[k]) | (X[k] & C[k]) | (Y[k] & C[k]);
end
carryout = C[n];
end

endmodule

Figure 3.24. A generic specification of a ripple-carry adder.

module addern (carryin, X, Y, S, carryout);
parameter n = 32;
input carryin;
input [n-1:0] X, Y; module fulladd (Cin, x, y, s, Cout);
output [n-1:0] S; input Cin, x, y;
output carryout; output s, Cout;
wire [n:0] C; assign s = x ^ y ^ Cin,
Cout = (x & y) | (x & Cin) | (y & Cin);
genvar i; endmodule
assign C[0] = carryin;
assign carryout = C[n];
generate
for (i = 0; i <= n-1; i = i+1)
begin:addbit
fulladd stage (C[i], X[i], Y[i], S[i], C[i+1]);
end
endgenerate
endmodule

Figure 3.25. A ripple-carry adder specified by using the generate statement.

 module addern (carryin, X, Y, S);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;

always @(X, Y, carryin)

S = X + Y + carryin;

endmodule

Figure 3.26. Specification of an n-bit adder using arithmetic assignment.

module addern (carryin, X, Y, S, carryout, overflow);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;
output reg carryout, overflow;

always @(X, Y, carryin)

begin
S = X + Y + carryin;
carryout = (X[n-1] & Y[n-1]) | (X[n-1] & ~S[n-1]) | (Y[n-1] & ~S[n-1]);
overflow = (X[n-1] & Y[n-1] & ~S[n-1]) | (~X[n-1] & ~Y[n-1] & S[n-1]);
end

endmodule

Figure 3.27. An n-bit adder with carry-out and overflow signals.

 module addern (carryin, X, Y, S, carryout, overflow);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;
output reg carryout, overflow;
reg [n:0] Sum;

always @(X, Y, carryin)

begin
Sum = {1'b0,X} + {1'b0,Y} + carryin;
S = Sum[n-1:0];
carryout = Sum[n];
overflow = (X[n-1] & Y[n-1] & ~S[n-1]) | (~X[n-1] & ~Y[n-1] & S[n-1]);
end

endmodule

Figure 3.28. An alternative specification of an n-bit adder with carry-out and overflow signals.
module addern (carryin, X, Y, S, carryout, overflow);
parameter n = 32;
input carryin;
input [n-1:0] X, Y;
output reg [n-1:0] S;
output reg carryout, overflow;

always @(X, Y, carryin)

begin
{carryout, S} = X + Y + carryin;
overflow = (X[n-1] & Y[n-1] & ~S[n-1]) | (~X[n-1] & ~Y[n-1] & S[n-1]);
end

endmodule

Figure 3.29. Simplified complete specification of an n-bit adder.

 module fulladd (Cin, x, y, s, Cout);
input Cin, x, y;
output reg s, Cout;

always @(x, y, Cin)

{Cout, s} = x + y + Cin;

endmodule

Figure 3.30. Behavioral specification of a full-adder.

module adder_hier (A, B, C, D, S, T, overflow);
input [15:0] A, B;
input [7:0] C, D;
output [16:0] S;
output [8:0] T;
output overflow;

wire o1, o2; // used for the overflow signals

addern U1 (1’b0, A, B, S[15:0], S[16], o1);

defparam U1.n = 16;
addern U2 (1’b0, C, D, T[7:0], T[8], o2);
defparam U2.n = 8;

assign overflow = o1 | o2;

endmodule

Figure 3.31. An example of setting parameter values in Verilog code.

module adder_hier (A, B, C, D, S, T, overflow);
input [15:0] A, B;
input [7:0] C, D;
output [16:0] S;
output [8:0] T;
output overflow;

wire o1, o2; // used for the overflow signals

addern #(16) U1 (1’b0, A, B, S[15:0], S[16], o1);

addern #(8) U2 (1’b0, C, D, T[7:0], T[8], o2);

assign overflow = o1 | o2;

endmodule

Figure 3.32. Using the Verilog # operator to set the values of parameters.
Figure 3.33. A ripple-carry adder specified
by using the generate statement.
Figure 3.34. Multiplication of unsigned numbers.
Figure 3.35. A 4x4 multiplier circuit.
 Multiplicand M (+14) 01110
Multiplier Q (+11) x 01011
Partial product 0 0 00 1 1 1 0
+ 001110
Partial product 1 0010101
+ 000000
Partial product 2 00 0 1 0 1 0
+ 00 1 1 1 0
Partial product 3 00 1 0 0 1 1
+ 000000
Product P (+154) 0010011010

(a) Positive multiplicand

Figure 3.36. Multiplication of signed numbers.

 Multiplicand M (– 14) 10010
Multiplier Q (+11) × 01011
Partial product 0 1 11 0 0 1 0
+ 11 0 0 1 0
Partial product 1 11 0 1 0 1 1
+ 00 0 0 0 0
Partial product 2 11 1 0 1 0 1
+ 11 0 0 1 0
Partial product 3 11 0 1 1 0 0
+ 000000
Product P (– 154) 1101100110

(b) Negative multiplicand

Figure 3.36. Multiplication of signed numbers.

 32 bits

S E M

Sign
0 denotes+ 8-bit 23 bits of mantissa
1 denotes– excess-127
exponent

(a) Single precision

64 bits

S E M

Sign
11-bit excess-1023 52 bits of mantissa
exponent

(b) Double precision

Figure 3.37. IEEE Standard floating-point formats.

Table 3.3. Binary-coded decimal digits.
Figure 3.38. Addition of BCD digits.
Figure 3.39. Block diagram for a one-digit BCD adder.
 module bcdadd(Cin, X, Y, S, Cout);
input Cin;
input [3:0] X, Y;
output reg [3:0] S;
output reg Cout;
reg [4:0] Z;

always@ (X, Y, Cin)

begin
Z = X + Y + Cin;
if (Z < 10)
{Cout, S} = Z;
else
{Cout, S} = Z + 6;
end

endmodule

Figure 3.40. Verilog code for a one-digit BCD adder.

Figure 3.41. Circuit for a one-digit BCD adder.
Convert (14959)10

Remainder Hex digit

14959 ÷ 16 = 934 15 F LSB
934 ÷ 16 = 58 6 6
58 ÷ 16 = 3 10 A
3 ÷ 16 = 0 3 3 MSB

Result is (3A6F)16

Figure 3.42. Conversion from decimal to hexadecimal.

Figure 3.43. Conversion of fractions from decimal to binary.
Figure 3.44. Conversion of fixed point
numbers from decimal to binary.
Figure 3.45. A comparator circuit.
module comparator (X, Y, V, N, Z);
input [3:0] X, Y;
output V, N, Z; module fulladd (Cin, x, y, s, Cout);
wire [3:0] S;
wire [4:1] C; input Cin, x, y;
output s, Cout;
fulladd stage0 (1’b1, X[0], ~Y[0], S[0], C[1]); assign s = x ^ y ^ Cin,
fulladd stage1 (C[1], X[1], ~Y[1], S[1], C[2]); Cout = (x & y) | (x & Cin) | (y & Cin);
fulladd stage2 (C[2], X[2], ~Y[2], S[2], C[3]);
fulladd stage3 (C[3], X[3], ~Y[3], S[3], C[4]); endmodule
assign V = C[4] ^ C[3];
assign N = S[3];
assign Z = !S;

endmodule

Figure 3.46. Structural Verilog code for the comparator circuit.

 module comparator (X, Y, V, N, Z);
parameter n = 32;
input [n-1:0] X, Y;
output reg V, N, Z;
reg [n-1:0] S;
reg [n:0] C;
integer k;

always @(X, Y)
begin
C[0] = 1’b1;
for (k = 0; k < n; k = k + 1)
begin
S[k] = X[k] ^ ~Y[k] ^ C[k];
C[k+1] = (X[k] & ~Y[k]) | (X[k] & C[k]) | (~Y[k] & C[k]);
end
V = C[n] ^ C[n-1];
N = S[n-1];
Z = !S;
end

endmodule

Figure 3.47. Generic Verilog code for the comparator circuit.

Figure 3.48. Multiplier carry-save array.
 ci

xi pi si

V DD

yi gi

ci + 1

Figure P3.1. Circuit for Problem 3.11.

module problem5_17 (IN, OUT);
input [3:0] IN;
output reg [3:0] OUT;

always @(IN)
if (IN == 4'b0101) OUT = 4'b0001;
else if (IN == 4'b0110) OUT = 4'b0010;
else if (IN == 4'b0111) OUT = 4'b0011;
else if (IN == 4'b1001) OUT = 4'b0010;
else if (IN == 4'b1010) OUT = 4'b0100;
else if (IN == 4'b1011) OUT = 4'b0110;
else if (IN == 4'b1101) OUT = 4'b0011;
else if (IN == 4'b1110) OUT = 4'b0110;
else if (IN == 4'b1111) OUT = 4'b1001;
else OUT = 4'b0000;

endmodule

Figure P3.2. The code for Problem 3.17.

 00 0 0
01 0 1
02 0 2
10 0 1
11 0 2
12 1 0
20 0 2
21 1 0
22 1 1

Figure P3.3. Ternary half-adder.