NATIONAL UNIVERSITY OF TECHNOLOGY

COMPUTER ENGINEERING DEPARTMENT

LAB REPORT NO 2

COMPUTER ORGANIZATION AND ARCHITECTURE LAB

Submitted by: Mudassir Hussain

NUTECH ID: F22604036

Submitted to: Pro. Abdul Qadeer Khan

Date of Submission: 17-03-2024

Table of Contents
Objectives......................................................................................................................................................................
Introduction...................................................................................................................................................................
Lab Tasks:.....................................................................................................................................................................
Lab Task 01:..................................................................................................................................................................
Code:.............................................................................................................................................................................
Testbench.......................................................................................................................................................................
Lab Task 02:..................................................................................................................................................................
Code..............................................................................................................................................................................
TestBench:.....................................................................................................................................................................

Conclusion.............................................................................................

OBJECTIVES:

To introduce students to implementation of Adder circuits.

EXPLANATION:

In hardware, snake circuit performs expansion of the parallel numbers.in different PCs and
different sorts of processors.adder circuits are utilized in ALUs, yet in addition utilized in
different processors to compute augmentation or decrement tasks, table records, addresses,
and so forth. A run of the mill viper circuit produces total and convey as the result. The
principal reason for these addresses is utilized to add the various arrangements like XS-3,
parallel coded decimal (BCD) and dark code. When the a couple of's praise are being utilized
to determine negative numbers, modifying adder is little to subtractor. A more intricate snake
is utilized to address other marked numbers. The applications of viper circuit are, snake
circuits are utilized to add twofold numbers, yet in addition utilized in computerized
applications, for example, address, table file, deciphering and computation and so on.

Sorts of Adders

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Half Adder:

The half adder adds two single parallel digits An and B. It has two results, total (S) and
convey (C). The convey signal addresses a flood into the following digit of a multi-digit
expansion. The worth of the aggregate in decimal framework is 2C + S. The least difficult
half-viper configuration, envisioned on the right, consolidates a XOR door for S and an
What's more, entryway for C. The Boolean rationale for the total (for this situation S) will be
A'B+AB' though for convey (C) will be Stomach muscle. With the expansion of
an OR entryway to join their convey yields, two half adders can be consolidated to make a
full snake. [1] The half snake adds two information bits and creates a convey and total, which
are the two results of a half adder. The information factors of a half viper are known as the
augend and numbers to be added bits. The result factors are the total and convey. Verilog is an
Equipment Depiction Language; a text based design for portraying electronic circuits also,
frameworks. Verilog HDL permits architects to plan at different degrees of deliberation.
Essentially there are two information types in Verilog, Nets and Registers. Nets are actual
associations between parts. However many kinds of nets are characterized in Verilog yet we
utilize just wire in RTL Verilog. A variable of type wire must be relegated a worth or then
again articulation once for example it shows up just a single time on LHS in the whole plan. A
wire can be utilized on numerous occasions in the rationale for example it can seem on
numerous occasions in RHS articulations. This variable is normally a result of rationale and
consistently shows the rationale worth of the driving parts. A wire surmises an actual wire
once integrated.

FULL ADDER:

A full adder adds paired numbers and records for values conveyed in as well as out. A the
slightest bit full-snake adds three the slightest bit numbers, frequently composed as A, B, and
C in ; An and B are the operands, what's more, C in is a piece conveyed in from the past less-
huge stage. [2] The full viper is typically a part in a fountain of adders, which add 8, 16, 32,
and so forth nibbled parallel numbers. The circuit produces a no good result. Yield convey
and total regularly addressed by the signs C out and S, where in decimal framework. A full
viper can be executed in various ways, for example, with a custom semiconductor level
circuit or made out of different entryways. One model execution is with what's more. In this
execution, the last OR entryway before the do result might be supplanted by an XOR
entryway without adjusting the subsequent rationale. Utilizing just two sorts of doors is
helpful if the circuit is being executed utilizing basic IC chips which contain just a single
entryway type for each chip. A full viper can likewise be built from two half adders by
associating and to the contribution of one half viper, then, at that point, taking its aggregate
output(S) as one of the contributions to the last part snake and as its other input, lastly the
convey yields from the two half-adders are associated with an OR entryway. The total result
from the last part snake is the last Aggregate result of the Full-Viper and the result from the
OR entryway is the last Convey yield. The basic way of a full viper goes through both

XOR-entryways and closures at the aggregate piece.

LAB TASK 1:

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Write Verilog code for Full Adder in behavioral modeling and simulate the results using

test-bench, attach waveform screenshots of results showing for different instances.

INPUT:

Code:

TEST BENCH:

OUTPUTS:

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LAB TASK 2 :

Write Verilog code for 4bit Adder using (instantiating) Half and Full Adders and simulate the
results using test-bench, attach waveform screenshots of results showing for different
instances.

INPUT:
CODE:

TEST BENCH:

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OUTPUT:

CONCLUSION:

All in all we have found out about conduct level demonstrating. It contains a consistently
block. We have likewise found out about launch which is utilized to utilize a module which
we have made. Launch saves our experience as whenever we have created a module we could
re at any point use it however many times as

we need.