Lecture -5

Combination Circuits-1
Prepared By: Dr. Shahriyar Masud Rizvi
Adder
• Addition is one of the most common operations performed by computing devices such as
computers, mobile phones, and in fact, any device that is powered by a microprocessor.
• They are essential in digital filters as well as many machine learning models/devices.

• Let us consider adding two binary bits.

• The rules of binary addition provide us the following results.
• 0+0=0
• 0+1=1
• 1+0=1
• 1 + 1 = 0, with a carryout of 1
Adder
• Wires vs Busses
• Digital signals can be grouped together depending on their operation or source for
ease of verification. A grouping of digital signals (bundle of wires) is called a bus.

Here, A, B and Y are 1-bit signals.

The following device, A, B and Y are busses, which are 2-bit wide. In other words, they are 2-bit signals.
A bus is composed of bits A0 and A1, where they represent LSB and MSB respectively.
Similarly, B bus is composed of bits B0 and B1 and Y bus is composed of bits Y0 and Y1.
1-bit Adders
• There are two types of 1-bit adders namely, Half-adder and a Full-adder.
• Half adder can add two 1-bit signals, while Full adder can add three 1-bit signals.

Block diagram of a Half-Adder Block diagram of a Full-Adder

Multi-bit Adders
• Multi-bit adders are constructed by cascading (series placement) of full adders.
• In multi-bit adders, carryout of one stage becomes carry in of next stage.
• This happens for traditional (decimal-based) addition also as shown below.
• As shown below, when addition of two numbers (such as 9 and 5) cannot be represented
by the available numbers (0 to 9), a 1 is added to the addition of next stage. Here, 1 is
carry out of stage 0 and carry in of stage 1.
Multi-bit Adders
• Multi-bit adders are constructed by cascading (series placement) of full adders.
• Carryout of full adders that add lesser significant bits becomes carry in of full adders that
add more significant bits.
• So, input signals of a full adder in a multi-bit adder (adder chain) like the following can be
denoted as Ai, Bi and Ci, while the output signals can be denoted as Si and Ci+1. Here, Ci
represents carryin of stage i and Ci+1 represents carryout of stage i.
A
Ai Bi C i

A1 B1 A0 Cin B
C1 B0 C0
A B Cin
FA A B Cin A B Cin
(MSB) FA FA
Cout S FA2 FA1 (LSB)
Cout S Cout S
Cout
C2 S1 C1 S0
Ci+1 Si S
Half Adder
• Half adder can add two 1-bit signals. It produces a sum and a carryout.
• Let us denote the inputs as A and B and outputs as S and COUT

A B S COUT

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

• = ̅ . B + A. = A⊕B
• COUT =A . B
Half Adder
• = ̅ . B + A. = A⊕B
• COUT =A . B

//Device name and I/O ports

module HA (input wire A, B,
output wire S, Cout);

//Define behavior/structure of the circuit

assign S= A ^ B;
assign Cout= A & B;

endmodule
Full Adder
• Half adder can add two 1-bit signals. It produces a sum and a carryout.
• Let us denote the inputs as A and B and outputs as S and COUT
• = + + + = ⊕ ⊕
• = + + + = + ⊕

CIN A B S COUT
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Full Adder
• = + + + = ⊕ ⊕
• = + + + = + ⊕

//Device name and I/O ports

module FA (input wire Cin, A, B,
output wire S, Cout);

//Define behavior/structure of the circuit

assign S= A ^ B ^ Cin;
assign Cout= (A & B) | ((A ^ B ) & Cin);

endmodule
Full Adder from Half Adders
• A Full Adder can be built from two half adder and an OR gate. Let’s examine the
schematic.
• A full adder does a “half” addition of A and B and another “half” addition of (A⊕B) and
CIN. It also does a half-adder style carryout computation of A and B and another such
carryout computation between (A⊕B) and CIN.
• So, the XOR gate in the figure generating P and the AND gate generating R are forms a half
adder. The XOR gate generating S and the AND gate generating Q forms another half
adder. An OR gate is needed to compute COUT, which performs OR operation between Q
and R.
Full Adder from Half Adders
• Note that half adder (HA) now is a sub-system (component) of the overall system that is
full adder.
• The port names of a generic HA are A, B, as inputs and S and COUT as outputs. Ports of
different instances (copies) of HA (such as HA1, HA2) will have different actual signals
(such as A, B, CIN, P, R, P, Q, S) connected to them.
Multi-bit Adders from Full Adders
• A 2-bit adder can be constructed by cascading (series placement) of two full adders.
//Level-2
//Top-Level module //Device name and I/O ports
//Device name and I/O ports module FA (input wire Cin, A, B,
module Adder_2Bit (input wire [1:0] A, B, output wire S, Cout);
output wire [1:0] S,
output wire Cout); //Define behavior/structure of the circuit

//Define internal C incorporating all carry type signals assign S= A ^ B ^ Cin;

assign Cout= (A & B) | ((A ^ B ) & Cin);
wire [2:0] C;
assign C[0] = 0; //Use C[0] just for a “symmetric look” endmodule

//Define behavior/structure of the circuit

//Instantiating two half adders
FA FA1 (.Cin(C[0]), .A(A[0]), .B(B[0]), .S (S[0]), .Cout (C[1]));
FA FA2 (.Cin(C[1]), .A(A[1]), .B(B[1]), .S (S[1]), .Cout (C[2]));

assign Cout = C[2]; //Pass C[2] as Cout

endmodule
Multi-bit Adders from Full Adders
//Top-Level module Syntax
//Device name and I/O ports In Verilog, a sub-system (component) can be defined inn a
module Adder_2Bit (input wire [1:0] A, B, module and then instantiated in an upper-level module.
output wire [1:0] S,
output wire Cout); Here, the Adder_2bit is built from two instances of FA (full
adder). So, FA is the component. FA1 and FA2 are instances
//Define internal C incorporating all carry type signals of FA. You need to write module only for FA, since FA1 and
wire [2:0] C; FA2 are just copies (instances) of FA.
assign C[0] = 0; //Use C[0] just for a “symmetric look”
When components are instantiated, generic ports of a
//Define behavior/structure of the circuit component are preceded by a “.” and then the actual signal
//Instantiating two half adders coming in or going out through that port for a specific
FA FA1 (.Cin(C[0]), .A(A[0]), .B(B[0]), .S (S[0]), .Cout (C[1])); instance is listed inside a bracket.
FA FA2 (.Cin(C[1]), .A(A[1]), .B(B[1]), .S (S[1]), .Cout (C[2]));
So, FA FA1 (.Cin(C[0]), .A (A[0], ………….); means C[0] is
assign Cout = C[2]; //Pass C[2] as Cout connected to Cin port of FA1 (which is an instance of FA).
Similarly, A[0] signals is connected to port A of FA1.
endmodule
Component_name instance_name
(.port1_name(signal1_name), .port2_name(signal2_name),
.port3_name(signal3_name)……);
Multi-bit Adders from Full Adders
//Top-Level module Syntax
//Device name and I/O ports In Verilog, a bus is defined in the following manner. The MSB
module Adder_2Bit (input wire [1:0] A, B, and LSB are mentioned in a bracket, separated by a colon (:).
output wire [1:0] S, A 2-bit bus A will be declared as wire [1:0] A
output wire Cout); Here MSB is bit-1, LSB is bit-0.
A 3-bit bus A will be declared as wire [2:0] A
Here MSB is bit-2, LSB is bit-0.
//Define internal C incorporating all carry type signals
A 4-bit bus A will be declared as wire [3:0] A
wire [2:0] C;
Here MSB is bit-3, LSB is bit-0.
assign C[0] = 0; //Use C[0] just for a “symmetric look”
Note that single-bit signals such as Cout do not need to
//Define behavior/structure of the circuit defined with MSB and LSB.
//Instantiating two half adders Single bits from busses can be referenced with specific bits
FA FA1 (.Cin(C[0]), .A(A[0]), .B(B[0]), .S (S[0]), .Cout (C[1])); inside brackets.
FA FA2 (.Cin(C[1]), .A(A[1]), .B(B[1]), .S (S[1]), .Cout (C[2]));

assign Cout = C[2]; //Pass C[2] as Cout

endmodule
Overflow, Number Wheel
• In digital design, input and output sizes of a sub-system are kept the same in many cases.
So, if this is followed the carryout becomes an extra signal. Even if carryout is not
considered part of the result due to the above requirement, it can serve another
purpose—that is it serves as an overflow indicator.
• In addition, HIGH carryout indicates overflow.
• Overflow means that the result could not be mapped within the available number of bits.

• For example, consider 011 (3) + 110 (6) = 001 (1) in a 3-bit adder.
011 (3)
110 (6)
1 001 (1)
Overflow, Number Wheel
• For example, consider 011 (3) + 110 (6) in a 3-bit adder.
011 (3)
110 (6)
1 001 (1)
We can graphically represent the addition in a number wheel.
We go clock-wise for addition.
For this example, start at 3, and then go 6 steps clock-wise to get the addition result.

If the arrow goes beyond max. number (111(7)), then overflow occurs. From number wheel, we get
3 + 6 = 1 as well.
Parallel Adder
• A 4-bit Parallel adder to add two 4bit numbers can be designed using the same principle.
Adder Expansion
• If an n-bit adder IC is available, larger sized adders can be built by cascading multiple n-
bit adders.
• For instance, an 8-bit adder can be built from two 4-bit adders.
• A 4-bit is called a nibble.
• This is the concept of adder expansion.
Adder Expansion
• We can cascade two blocks of 4-bit parallel adder to add two numbers of 8-bits.
Example of Adder Expansion
Subtractor
• The logic equation for subtraction can be developed from truthtable. One can build half-
subtractor and full-subtractor from truthtable. Similar, to adders, multi-bit subtracters
can be built from full-subtractor.
• However, subtracters are typically realized with 2’s compliment addition in industrial
EDA tools. This is because, when 2’s compliment subtraction is used, adders can be used
for both addition and subtraction purposes.
• Subtraction of two numbers is defined as addition of 2’s compliment version of one of the
inputs with the other inputs kept unchanged. So, one input is kept unchanged, while the
other input is provided to the adder in its 2’s compliment form.

Ysub =A–B
= A + (-B)
= A + (2’s compliment of B)
Subtractor
• 2’s compliment is formed from addition of 1’s compliment with 1.
• 1’s compliment is the NOT operation performed on an input.
So, Ysub = A + (2’s compliment of B)
= A + (1’s compliment of B + 1)
=A+ +1
• Example,
• Subtract 3 from 5 in a 3-bit arithmetic.

• A = 101 (5)
• B = 011 (3) 1’sC of B = 100 2’s C of B = 100 + 1 = 101

• A = 101 (5)
• 2’sC of B = 101 (2’sC of B)
• Ysub = 1 010 (2), carryout is not part of the subtraction result.
Subtractor
• Example,
• Subtract 5 from 3 in a 3-bit arithmetic.

• A = 011 (3)
• B = 101 (5) 1’sC of B = 010 2’s C of B = 010 + 1 = 011

• A = 011 (3)
• 2’sC of B = 011 (2’sC of B)
• Ysub = 0 110 (6), carryout is not part of the subtraction result.
Overflow (Subtraction), Number Wheel
• In subtraction, LOW carryout indicates overflow.
• Subtraction Overflow or underflow means that the result could not be mapped within the
available number of bits. This happens when a large number is subtracted from a small number. In
integer arithmetic, there is no negative number. In other words, there is no number smaller than
zero.
• We can graphically represent the subtraction in a number wheel.
• One needs to go counter-clock-wise direction for subtraction.
• For this example, to get the result of 3 – 5, start at 3, and then go 5 steps counter-clock-wise to get
the subtraction result.
• If the arrow goes beyond min. number (000(0)), then overflow occurs. From number wheel, we
get 3 – 5 = 6 as well.
Adder-Subtractor
• Since both addition and subtraction uses addition, one can develop a common expression for
addition and subtraction provided there is a control signal that selects whether addition or
subtraction should be performed.
• Addition A + B
Subtraction A – B = A + (-B) = A + + 1
• If we can control the 2nd input to the adder (say, B_to_add), regarding whether it should
be B or , we can use the same adder to produce both addition and subtraction.
• Secondly, subtraction requires an extra 1, while the addition does not need any.
• So, if the control signal, say AS, is chosen in such a way that a AS = 0 ensures addition and
AS = 1 ensures subtraction, then the control signal itself can be added to the addition
process. This will provide that extra 1 for subtraction.
• So, the common equation for adder-subtractor becomes S = A + B_to_add + AS.
• In addition, this equation becomes A + B + 0. For subtraction, it becomes A + + 1.
AS B_to_add S S values
Addition 0 B A + B_to_add + AS A+B+0
Subtraction 1 A+ +1
Adder-Subtractor
• The common equation for adder-subtractor S = A + B_to_add + AS.
• For addition, this equation becomes A + B + 0. For subtraction, it becomes A + + 1.
• From the truthtable, B_to_add = . B + AS. = AS ⊕ B
• This XOR gate ensures that the adder receives B for addition and for subtraction.
AS B_to_add S S values

Addition 0 B A + B_to_add + AS A+B+0

Subtraction 1 A+ +1
Adder-Subtractor
• S = A + B_to_add + AS. B_to_add = . B + AS. = AS ⊕ B
• This XOR gate ensures that the adder receives B for addition and for subtraction.
• A 1-bit adder-subtracter utilizes a full adder and an XOR gate. The control signal AS would
be connected to the Cin port of the full adder.

B_to_add
Adder-Subtractor
• A 2-bit adder-subtracter would utilize two full adders and two XOR gates, as shown
below. The control signal AS would be connected to the Cin port of the full adder for the
LSB bit.
Digital Magnitude Comparator
• A comparator is a combinational circuit which
can be used to compare between two number. A A>B
• A magnitude comparator has three possible
1-bit A=B
outputs; A is greater than B, A is equal to B and
A is less than B. B Comparator A<B
• The truth-table for a 1-bit comparator can be
constructed as:

The Boolean expression for the outputs:

= +
=
=
Digital Magnitude Comparator
The Boolean expression for the outputs:
= + = ⊕
=
=
Digital Magnitude Comparator
• Note that FA>B, FA<B can be implemented by AND gates. The FA=B however requires an
XNOR gate, which is more expensive than AND gates.
• One option to reduce number of gates or area would be to implement FA>B, FA<B and
realize that FA=B will only be true when the other two comparisons are false.

• = .

• Using DeMorgan’s duality, one can represent the above logic (AND with inverted inputs)
with a NOR gate. . = +
Digital Magnitude Comparator
Digital Magnitude Comparator
• Two 1-bit comparators can be logically connected to make a 2-bit number comparator.
• The logic behind the connections are:
• Let = ( == ) and = ( == )
• For = , the Boolean expression is X X
• For > , the Boolean expression is + ( )
• For < , the Boolean expression is + ( )
References
1. Thomas L. Floyd, “Digital Fundamentals” 11th edition, Prentice Hall – Pearson Education.