RISC-V Reference Card

RISC-V Core Instruction Formats

31 ———————————- 25 24 —– 20 19 —– 15 14 —– 12 11 ——- 7 6 ——– 0
funct7 rs2 rs1 funct3 rd opcode R-type
imm[11:0] rs1 funct3 rd opcode I-type
imm[11:5] rs2 rs1 funct3 imm[4:0] opcode S-type
imm[12][10:5] rs2 rs1 funct3 imm[4:1][11] opcode B-type
imm[31:12] rd opcode U-type
imm[20][10:1][11][19:12] rd opcode J-type

RV32I Base Integer Instructions

Inst Name FMT Opcode funct3 funct7 Description
add ADD R 0110011 000 0000000 rd = rs1 + rs2
sub SUB R 0110011 000 0100000 rd = rs1 rs2
xor XOR R 0110011 100 0000000 rd = rs1 ˆ rs2
or OR R 0110011 110 0000000 rd = rs1 | rs2
and AND R 0110011 111 0000000 rd = rs1 & rs2
sll Shift Left Logical R 0110011 001 0000000 rd = rs1 << rs2
srl Shift Right Logical R 0110011 101 0000000 rd = rs1 >> rs2
sra Shift Right Arith. R 0110011 101 0100000 rd = rs1 >> rs2
slt Set Less Than R 0110011 010 0000000 rd = (rs1 < rs2) ? 1 : 0
sltu Set Less Than (U) R 0110011 011 0000000 rd = (rs1 < rs2) ? 1 : 0
addi ADD Immediate I 0010011 000 rd = rs1 + imm
xori XOR Immediate I 0010011 100 rd = rs1 ˆ imm
ori OR Immediate I 0010011 110 rd = rs1 | imm
andi AND Immediate I 0010011 111 rd = rs1 & imm
slli Shift Left Logical Imm I 0010011 001 0000000 rd = rs1 << imm[4:0]
srli Shift Right Logical Imm I 0010011 101 0000000 rd = rs1 >> imm[4:0]
srai Shift Right Arith. Imm I 0010011 101 0100000 rd = rs1 >> imm[4:0]
slti Set Less Than Imm I 0010011 010 rd = (rs1 < imm) ? 1 : 0
sltiu Set Less Than (U) Imm I 0010011 011 rd = (rs1 < imm) ? 1 : 0
lb Load Byte I 0000011 000 rd = M[rs1+imm][7:0]
lh Load Half I 0000011 001 rd = M[rs1+imm][15:0]
lw Load Word I 0000011 010 rd = M[rs1+imm][31:0]
lbu Load Byte (U) I 0000011 100 rd = M[rs1+imm][7:0]
lhu Load Half (U) I 0000011 101 rd = M[rs1+imm][15:0]
sb Store Byte S 0100011 000 M[rs1+imm][7:0] = rs2[7:0]
sh Store Half S 0100011 001 M[rs1+imm][15:0] = rs2[15:0]
sw Store Word S 0100011 010 M[rs1+imm][31:0] = rs2[31:0]
beq Branch == B 1100011 000 if(rs1 = rs2) PC += imm
bne Branch 6= B 1100011 001 if(rs1 6= rs2) PC += imm
blt Branch < B 1100011 100 if(rs1 < rs2) PC += imm
bge Branch B 1100011 101 if(rs1 rs2) PC += imm
bltu Branch < (U) B 1100011 110 if(rs1 < rs2) PC += imm
bgeu Branch (U) B 1100011 111 if(rs1 rs2) PC += imm
jal Jump And Link J 1101111 - rd = PC+4; PC += imm
jalr Jump And Link Reg I 1100111 000 rd = PC+4; PC = rs1 + imm
lui Load Upper Imm U 0110111 - rd = imm << 12
auipc Add Upper Imm to PC U 0010111 - rd = PC + (imm << 12)

Register Calling Convention

Register Name Description Saver
x0 zero Zero constant —
x1 ra Return address Caller
x2 sp Stack pointer Callee
x3 gp Global pointer —
x4 tp Thread pointer —
x5-x7 t0-t2 Temporaries Caller
x8 s0/fp Saved/frame pointer Callee
x9 s1 Saved register Callee
x10-x11 a0-a1 Arguments/return Caller
x12-x17 a2-a7 Function args Caller
x18-x27 s2-s11 Saved registers Callee
x28-x31 t3-t6 Temporaries Caller

1
Pseudo Instructions
Pseudoinstruction Base Instruction(s) Meaning
la rd, symbol addi rd, rd, symbol[11:0] Load address
l{b|h|w|d} rd, symbol l{b|h|w|d} rd, symbol[11:0](rd) Load global
s{b|h|w|d} rd, symbol, rt s{b|h|w|d} rd, symbol[11:0](rt) Store global
fl{w|d} rd, symbol, rt fl{w|d} rd, symbol[11:0](rt) Floating-point load global
fs{w|d} rd, symbol, rt fs{w|d} rd, symbol[11:0](rt) Floating-point store global
nop addi x0, x0, 0 No operation
li rd, immediate Myriad sequences Load immediate
mv rd, rs addi rd, rs, 0 Copy register
not rd, rs xori rd, rs, -1 One’s complement
neg rd, rs sub rd, x0, rs Two’s complement
seqz rd, rs sltiu rd, rs, 1 Set if = zero
snez rd, rs sltu rd, x0, rs Set if 6= zero
sltz rd, rs slt rd, rs, x0 Set if < zero
sgtz rd, rs slt rd, x0, rs Set if > zero
beqz rs, o↵set beq rs, x0, o↵set Branch if = zero
bnez rs, o↵set bne rs, x0, o↵set Branch if 6= zero
blez rs, o↵set bge x0, rs, o↵set Branch if  zero
bgez rs, o↵set bge rs, x0, o↵set Branch if zero
bltz rs, o↵set blt rs, x0, o↵set Branch if < zero
bgtz rs, o↵set blt x0, rs, o↵set Branch if > zero
bgt rs, rt, o↵set blt rt, rs, o↵set Branch if >
ble rs, rt, o↵set bge rt, rs, o↵set Branch if 
bgtu rs, rt, o↵set bltu rt, rs, o↵set Branch if >, unsigned
bleu rs, rt, o↵set bgeu rt, rs, o↵set Branch if , unsigned
j o↵set jal x0, o↵set Jump
jal o↵set jal x1, o↵set Jump and link
jr rs jalr x0, rs, 0 Jump register
jalr rs jalr x1, rs, 0 Jump and link register
ret jalr x0, x1, 0 Return from subroutine

ALU Control
ALU Control Lines Function
0000 AND
0001 OR
0010 add
0110 subtract

opcode ALUOp Operation funct7 funct3 ALU Action ALU Control Input
lw 00 load word xxxxxxx xxx add 0010
sw 00 store word xxxxxxx xxx add 0010
beq 01 branch if equal xxxxxxx xxx subtract 0110
R-Type 10 add 0000000 000 add 0010
R-Type 10 sub 0100000 000 subtract 0110
R-Type 10 and 0000000 - AND 0000
R-Type 10 or 0000000 110 OR 0001