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Unit 3

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12 views23 pages

Unit 3

Uploaded by

Comrade Venkata Harsha
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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moore machines

Q) construct a moore machine that print 'a' whenever the sequence '01' is encountered in
any input binary string.

Q) construct a moore machine that detects occurence of sequence 'abb' is encountered in


any input binary string.
Q) Design a positive transition detector ,system which gives output 1,whenever the input
to the system changes from 0 to 1.
Q) Design a mealy machine for the following state diagram

s0 s1 s2
pattern or sequence detector

-> The stream of bits has been feed as input,when the clk is high and a particular
pattern/sequence is detected
->As soon as sequence is detected the output becomes high and then again becomes
low

Two types :
1.non overlapping
2.overlapping x
sequence detector y

clk
Q1.Design a sequence detector to detect 010 in stringn of bits coming through an
input line using mealy model.
Q2.Design a sequence detector to detect 101 in stringn of bits coming through an
input line using moore model.
Q3.Design a sequence detector to detect three or more consecutive ones in stringn of bits
coming through an input line using mealy model.

step 1: state diagram step 3:state table

present input next out put


state x state y
QA QB QA+ QB+

step 2:state assignments

step 4: getting Expressions

step 5:circuit diagram


Q) Design a sequence detector to detect 101 in string of bits coming through an
input line using moore model(OL)

step 1: state diagram

step2:state table

O/P PS I/P NS O/P f/f i/p


PS I/P NS
Q1 Q0 x Q1+ Q0+ Z D1 D0

step 3:state assignment

k maps

00 01 11 10 00 01 11 10 00 01 11 10

0 0 0

1 1 1
circuit diagram:
State reduction and assignment

NS o/p
P.S a
x=0 x=1 x=0 x=1

a a b 0 0

b c d 0 0

c a d 0 0 b c

d e f 0 1

e a f 0 1

f g f 0 1
d e
g f 0 1 g
a

*** if NS and output of two PS are same then we can eliminate one state.

NS o/p
P.S
x=0 x=1 x=0 x=1

a a b 0 0

b c d 0 0

c a d 0 0

d e f 0 1

e a f 0 1

f g f 0 1

g f 0 1
a
STATE REDUCTION

a NS O/P NS O/P
PS PS

a b c 0 0
b c b d e 1 0
c c d 0 1
d a d 0 0
e e c d 0 1
d

DESIGH OF SERIAL ADDER (MEALY MODEL)


DESIGN OF SERIAL ADDER (MOORE MODEL)
Conversion of moore to mealy

moore:

moore state table

Conversion of mealy to moore


a/1
mealy: moore:
B
a/0
A
b/0 a/0
b/0
C

b/1
0/0
0/1
1/1 B
A
1/0

conversion using transition table :

NS,o/p
ps
a b
Q0 Q3,0 Q1,1
Q1 Q0,1 Q3,0

Q2 Q2,1 Q2,0

Q3 Q1,0 Q0,1
Parity generator
parity detector
mealy model

-> For non-OL, move the last bit to reset stste


->For 1-bit OL,compare the last bit to 1-bit state
->For 2-bit OL,compare the last 2bits to 2 bit state
then 1 bit to 1 bit state and so on

moore model

-> For non-OL, move the last bit to 1 bit state


->For 1-bit OL,compare the last 2 bits to 2-bit state then 1 bit to 1 bit state and so on
->For 2-bit OL,compare the last 3bits to 3 bit state
then 2 bit to 2 bit state and so on

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