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FSM Files DSD Verilog

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7 views24 pages

FSM Files DSD Verilog

Uploaded by

xawotaw126
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Finite State

CHAPTER 5 Machines
TEAM DSD @ SCHOOL OF
ELECTRONICS &
COMMUNICATION
CONTENTS

Finite State Machines in Verilog


• Moore machine
• Mealy machine

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 2


MOORE MACHINE
Output = f(Present state)
Next State = f(Present state, Inputs)

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 3


MEALY MACHINE
Output = f(Present state, Inputs)
Next State = f(Present state, Inputs)

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 4


IS IT MEALY OR MOORE MACHINE?

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 5


IS IT MEALY OR MOORE MACHINE?

Moore
machine

Moore
machine
SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 6
IS IT MEALY OR MOORE MACHINE?

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 7


IS IT MEALY OR MOORE MACHINE?

Mealy machine

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 8


IS IT MEALY OR MOORE MACHINE?

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 9


IS IT MEALY OR MOORE MACHINE?

Moore
machine

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 10


IS IT MEALY OR MOORE MACHINE?

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 11


IS IT MEALY OR MOORE MACHINE?

Moore
machine

Mealy
SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 12
STATE ENCODING
Common FSM encoding options:
• One-hot code
• Binary code
• Gray code
• Random code

One-hot encoding
• usually used in FPGA-based designs

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 13


A 0101 SEQUENCE DETECTOR
Design a sequence detector with one input din and one output y. The
detector should recognize the input sequence 0101. The detector should
keep checking for the appropriate sequence and should not reset to the
initial state after it has recognized the sequence. The detector should
initialize to a reset state only when input reset is activated.

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 14


A 0101 SEQUENCE DETECTOR:
MOORE MACHINE
1

S0 0 S1 1 S2 0 S3 1 S4
1
0 0 0 0 1

0
0

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 15


A 0101 SEQUENCE DETECTOR:
MOORE MACHINE
module moore_fsm(din, reset, clk, y);
input din, reset, clk;
output reg y;
reg [2:0] cst, nst;
parameter S0 = 3'b000, S1 = 3'b001,
S2 = 3'b010, S3 = 3'b011, S4=3’b100;
//all states

always @(cst or din)


begin
case (cst)
S0: begin y=1'b0 ;
if (din == 1'b1) nst = S0;
else nst = S1; end
S1: begin y=1'b0;
if (din == 1'b1) nst = S2;
else nst = S1; end

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 16


A 0101 SEQUENCE DETECTOR:
MOORE MACHINE
S2: begin y=1'b0;
if (din == 1'b1) nst = S0;
else nst = S3; end
S3: begin y=1'b0;
if (din == 1'b1) nst = S4;
else nst = S1; end
S4: begin y=1'b1;
if (din == 1'b1) nst = S0;
else nst = S3; end
default: nst = S0;
endcase
end

always@(posedge clk)
begin
if (reset) cst <= S0;
else cst <= nst;
end
endmodule
SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 17
A 0101 SEQUENCE DETECTOR:
MOORE MACHINE
S2: begin y=1'b0;
if (din == 1'b1) nst = S0;
else nst = S3; end
S3: begin y=1'b0;
if (din == 1'b1) nst = S4;
else nst = S1; end
S4: begin y=1'b1;
if (din == 1'b1) nst = S0;
else nst = S3; end
default: nst = S0;
endcase
end

always@(posedge clk)
begin
Test Bench: if (reset) cst <= S0;
data = 11'b10101001010; else cst <= nst;
end
for (i = 0; i<11; i=i+1)
endmodule
#10 din = data[i];
SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 18
A 0101 SEQUENCE DETECTOR:
MEALY MACHINE

0/0
1/0
0/0

0/0 1/0
S0 S1 S2 S3

1/1
1/0
0/0

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 19


A 0101 SEQUENCE DETECTOR:
MEALY MACHINE
module mealy_fsm(din, reset, clk, y);
input din, reset, clk;
output reg y;
reg [1:0] cst, nst;
parameter S0 = 2'b00, S1 = 2'b01, S2
= 2'b10, S3 = 2'b11; //all states

always @(cst or din)


begin
case (cst)
S0: if (din == 1'b1)
begin nst = S0; y=1'b0; end
else
begin nst = S1; y=1'b0; end
S1: if (din == 1'b1)
begin nst = S2; y=1'b0; end
else
begin nst = S1; y=1'b0; end

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 20


A 0101 SEQUENCE DETECTOR:
MEALY MACHINE
S2: if (din == 1'b1)
begin nst = S0; y=1'b0; end
else
begin nst = S3; y=1'b0; end
S3: if (din == 1'b1)
begin nst = S2; y=1'b1; end
else
begin nst = S1; y=1'b0; end
default: nst = S0;
endcase
end
always@(posedge clk)
begin
if (reset) cst <= S0;
Test Bench: else cst <= nst;
data = 11'b10101001010; end
endmodule
for (i = 0; i<11; i=i+1)
#10 din = data[i];
SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 21
A 0101 SEQUENCE DETECTOR:
MEALY MACHINE
S2: if (din == 1'b1)
begin nst = S0; y=1'b0; end
else
begin nst = S3; y=1'b0; end
S3: if (din == 1'b1)
begin nst = S2; y=1'b1; end
else
begin nst = S1; y=1'b0; end
default: nst = S0;
endcase
end
always@(posedge clk)
begin
if (reset) cst <= S0;
else cst <= nst;
end
endmodule

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 22


IS IT MEALY OR MOORE MACHINE?

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 23


IS IT MEALY OR MOORE MACHINE?

Moor
e

Mealy

SCHOOL OF ELECTRONICS & COMMUNICATION ENGINEERING 24

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