PATTERN(SEQUENCE)

DETECTOR
KRISHNAPRIYA M
EDT
 SEQUENCE DETECTOR
A stream of bit has been feed as input, when the clock is high and a
particular pattern/sequence is detected.
As soon as sequence is detected ,the output become high and then again
becomes low.
 OVERLAPPING AND NON OVERLAPPING

In overlapping sequence detector, the last bit of one sequence becomes the first
bit of the next sequence.
Example : Detect ‘1001’
Input : 100100100111
Output : 000100100100

In non-overlapping sequence detector, the last bit of one sequence does not
become the first bit of the next sequence.
Example : Detect ‘1001’
Input : 100100100111
Output : 000100000100
 1001 Sequence detector
MEALY MACHINE - OVERLAPPING

STATE DIAGRAM
 1001 Sequence detector
MEALY MACHINE - OVERLAPPING

STATE TABLE

STATE ASSIGNMENT

A -00
B - 01
C - 10
D - 11
 1001 Sequence detector
MEALY MACHINE - OVERLAPPING

Using K-map, _
QO+ = X + Q1 Q0
__ _ _
Q1+ = X Q1 Q0 + X Q1 QO

Y = X Q1 Q0
1001 Sequence detector
MEALY MACHINE - OVERLAPPING

_
DO = X + Q1 Q0
__ _ _
D1 = X Q1 Q0 + X Q1 QO

Y = X Q1 Q0
 1001 Sequence detector
VERILOG CODE

module 1001_detector (clk, reset, x, y); B:begin

input clk, reset, x; if(x==1'b1) next_state<=B;
output y; else next_state<=C;
parameter [1:0] A=2'b00; end
parameter [1:0] B=2'b01; C:begin
parameter [1:0] C=2'b10; if(x==1'b1) next_state<=B;
parameter [1:0] D=2'b11; else next_state<=D;
reg [3:0] state,next_state; end
always @(posedge clk or posedge reset) D:begin
begin if(x==1'b1) next_state<=B;
if(reset) state<=A; else next_state<=A;
else end
case(state) endcase
A:begin
end
if(x==1'b1) next_state<=B;
assign y=(state==D)&&(x==1)?1:0;
else next_state<=A;
endmodule
end
 1001 Sequence detector
MEALY MACHINE - NON-OVERLAPPING

STATE DIAGRAM
 1001 Sequence detector
MEALY MACHINE - NON-OVERLAPPING

STATE TABLE

STATE ASSIGNMENT

A -00
B - 01
C - 10
D - 11
 1001 Sequence detector
MEALY MACHINE - NON-OVERLAPPING

Using K-map,
_ _
QO+ = X Q1 + Q1 Q0
__ _ _
Q1+ = X Q1 Q0 + X Q1 QO

Y = X Q1 Q0
1001 Sequence detector
MEALY MACHINE - NON-OVERLAPPING

_ _
DO = X Q1 + Q1 Q0
__ _ _
D1 = X Q1 Q0 + X Q1 QO

Y = X Q1 Q0
 1001 Sequence detector
MOORE MACHINE - OVERLAPPING

STATE DIAGRAM
 1001 Sequence detector
MOORE MACHINE - OVERLAPPING

STATE TABLE

STATE ASSIGNMENT

A -000
B - 001
C - 010
E - 011
D - 100
 1001 Sequence detector
MOORE MACHINE - OVERLAPPING

_ _ _
Q2+ = X Q1 Q0 Q1+ = X Q0 + X Q2

Q0+ = X Y = Q1 Q0
1001 Sequence detector
MOORE MACHINE - OVERLAPPING

_ _
D2 = X Q1 Q0
_
D1 = X Q0 + X Q2
D0 = X
Y = Q1 Q0
VERILOG CODE
1001 Sequence detector
if(x==1'b1) next_state<=B;
module 1010_detector (clk, reset, x, y);
else next_state<=C;
input clk, reset, x;
end
output y;
C:begin
parameter [2:0] A=3'b000;
parameter [2:0] B=3'b001; if(x==1'b1) next_state<=B;
parameter [2:0] C=3'b010; else next_state<=D;
parameter [2:0] E=3'B011 end
parameter [2:0] D=3'b100; D:begin
reg [3:0] state,next_state; if(x==1'b1) next_state<=E
always @(posedge clk or posedge reset) else next_state<=A;
begin end
if(reset) state<=A; E:begin
else if(x==1'b1) next_state<=B;
case(state) else next_state<=C;
A:begin end
if(x==1'b1) next_state<=B; endcase
else next_state<=A; end
end assign y=(state==E)?1:0;
B:begin endmodule
 APPLICATIONS

Data Compression - Used in algorithms that need pattern identification

for specific sequences of data storage.

Control Systems - applied in control system that perform monitoring

and decision making based on patterns of the input signal observed.

Pattern Recognition - Applied to a vast amount of applications from

image and machine learning down to pattern recognition in datasets.

Embedded Systems - Applied in microcontrollers as well as digital

circuits with applications requiring control logic to identify sequences.
 QUESTIONS

1. Draw a single Moore FSM to detect the overlapping sequences either

1001 or 1101.
2. Draw a single Mealy or Moore FSM to detect the overlapping sequence
either 10110 or 11001.
3. Design the Mealy FSM that detects non overlapping sequence 101 and
realize using DFF and AND gate.
THANK YOU