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ECE234 Electronics-2 W3-4

The document provides an overview of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), detailing their types, characteristics, and operating regions. It distinguishes between depletion and enhancement types, explaining their operational principles and applications in electronic circuits. Additionally, the document covers biasing configurations and Q-point stability in JFETs, emphasizing the importance of biasing methods for stable operation.

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0% found this document useful (0 votes)
14 views34 pages

ECE234 Electronics-2 W3-4

The document provides an overview of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), detailing their types, characteristics, and operating regions. It distinguishes between depletion and enhancement types, explaining their operational principles and applications in electronic circuits. Additionally, the document covers biasing configurations and Q-point stability in JFETs, emphasizing the importance of biasing methods for stable operation.

Uploaded by

yuansalazar1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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You are on page 1/ 34

ECE234: Electronics 2

Electronic Circuit Analysis & Design


Prepared & Presented by
Engr. Stephanie B. Senomio, MT

MOSFET

2 Footer Text 4/8/2025

1
A. INTRODUCTION:
METAL OXIDE SEMICONDUCTOR FET (MOSFET)
Transistor (MOSFET) is one type of FET transistor.
In these transistors the
gate terminal is electrically
insulated from the current
carrying channel so that it is
also called as Insulated
Gate FET (IG-FET)
Due to the insulation
between gate and source
terminals the input resistance
of MOSFET may be very high
such as in mega ohms

A. INTRODUCTION

2
A. INTRODUCTION:

B. TYPES:

Depletion Type
The depletion type MOSFET transistor is equivalent to a “normally
closed” switch. The depletion type of transistors requires gate –
source voltage (VGS) to switch OFF the device. The depletion
mode MOSFET transistors are generally ON at zero gate-source
voltage (VGS). The conductivity of the channel in depletion MOSFETs
is less compared to the enhancement type of MOSFETs.

3
B. TYPES:
Enhancement Type
Enhancement type MOSFETS are normally off which means
when an enhancement- type MOSFET is connected, there will be
no flow of current from the terminal drain (D) to the source (S)
when no voltage is given to its gate terminal. This is the reason to
call this transistor a normally off device.

B. TYPES:

4
B. TYPES:

C. N Channel MOSFET

10

5
C. N Channel MOSFET

11

C. N Channel MOSFET

12

6
C. N Channel MOSFET

13

C. N Channel MOSFET

14

7
C. N Channel MOSFET

15

D. E-MOSFET

16

8
D. E-MOSFET

17

D. E-MOSFET

18

9
E. MOSFET CHAR. & PARAMETERS
 D-MOSFET Transfer Characteristics

19

E. MOSFET CHAR. & PARAMETERS


 D-MOSFET Transfer Characteristics

20

10
E. MOSFET CHAR. & PARAMETERS
 D-MOSFET Transfer Characteristics
 Example:

21

ENHANCEMENT MODE MOSFET


The equation for the parabolic transfer characteristic
curve of the E-MOSFET differs from that of the JFET and
the D-MOSFET because the curve starts at VGS(th)
rather than VGS(off) on the horizontal axis and never
intersects the vertical axis. The equation for the E-MOSFET
transfer characteristic curve is

22

11
ENHANCEMENT MODE MOSFET
The drain characteristics below reveal that for the device with
VGS = 8 V, saturation occurred at a level of VDS = 6 V. In fact,
the saturation level for VDS is related to the level of applied
VGS by

23

ENHANCEMENT MODE MOSFET

24

12
E. MOSFET CHAR. & PARAMETERS
 E-MOSFET Transfer Characteristics

25

E. MOSFET CHAR. & PARAMETERS


 E-MOSFET Transfer Characteristics

26

13
E. MOSFET CHAR. & PARAMETERS
 E-MOSFET Transfer Characteristics
 Example (Answer: ID = 98.7mA):

27

F. MOSFET OPERATING REGIONS


 The MOSFETs ability to change between these two states enables it to
have two basic functions: “switching” (digital electronics) or
“amplification” (analogue electronics).

28

14
F. MOSFET OPERATING REGIONS
 Then MOSFETs have the ability to operate within three
different regions:
 Cut-off Region – with VGS < Vthreshold the gate-source voltage is
much lower than the transistors threshold voltage so the MOSFET
transistor is switched “OFF” thus, ID = 0, with the transistor acting
like an open switch regardless of the value of VDS.
 Linear (Ohmic) Region – withVGS > Vthreshold and VDS < VGS
the transistor is in its constant resistance region behaving as a
voltage-controlled resistance whose resistive value is determined by
the gate voltage, VGS level.
 Saturation Region – with VGS > Vthreshold and VDS > VGS the
transistor is in its constant current region and is therefore “fully-ON”.
The Drain current ID = Maximum with the transistor acting as a
closed switch

29

F. MOSFET OPERATING REGIONS


 Depending on the magnitude of the negative bias established by VGS, a
level of recombination between electrons and holes will occur that will
reduce the number of free electrons in the n- channel available for
conduction.
 The more negative the bias, the higher the rate of recombination. The
resulting level of drain current is therefore reduced with increasing
negative bias for VGS as shown in the figure below for VGS = - 1 V, - 2 V,
and so on, to the pinch-off level of 6 V

30

15
F. MOSFET OPERATING REGIONS

31

F. MOSFET OPERATING REGIONS

32

16
OPERATING OF DEPLETION MODE MOSFET

33

OPERATING OF ENHANCEMENT MODE MOSFET

34

17
ENHANCEMENT MODE MOSFET

35

ENHANCEMENT MODE MOSFET

36

18
FET BIASING

37 Footer Text 4/8/2025

37

INTRODUCTION

38

19
A. FIXED BIAS CONFIGURATION

39

A. FIXED BIAS CONFIGURATION

40

20
A. FIXED BIAS CONFIGURATION

41

A. FIXED BIAS CONFIGURATION

42

21
A. FIXED BIAS CONFIGURATION
Example:

43

A. FIXED BIAS CONFIGURATION

44

22
B. SELF-BIAS CONFIGURATION

45

B. SELF-BIAS CONFIGURATION

46

23
B. SELF-BIAS CONFIGURATION

47

B. SELF-BIAS CONFIGURATION

48

24
B. SELF-BIAS CONFIGURATION

49

B. SELF-BIAS CONFIGURATION

50

25
C. VOLTAGE DIVIDER BIASING

51

C. VOLTAGE DIVIDER BIASING

52

26
C. VOLTAGE DIVIDER BIASING

53

C. VOLTAGE DIVIDER BIASING

54

27
C. VOLTAGE DIVIDER BIASING

55

C. VOLTAGE DIVIDER BIASING

56

28
C. VOLTAGE DIVIDER BIASING
Sample Problem
o Determine ID and VGS for the JFET with voltage-divider bias in
the figure below, given that for this particular JFET the
parameter values are such that VD = 7V.

57

C. VOLTAGE DIVIDER BIASING


Graphical Analysis of a JFET with Voltage-Divider Bias
o An approach similar to the one used for self-bias can be used
with voltage- divider bias to graphically determine the Q-point
of a circuit on the transfer characteristic curve.
o In a JFET with voltage-divider bias when ID = 0, VGS is not
zero, as in the self-biased case, because the voltage divider
produces a voltage at the gate independent of the drain
current. The voltage-divider dc load line is determined as
follows.
For I = 0
D

𝑉S = 𝐼D𝑅s = (0)𝑅s = 0𝑉
𝑉GS = 𝑉G — 𝑉S = 𝑉G — 0𝑉 = 𝑉G

58

29
C. VOLTAGE DIVIDER BIASING
Graphical Analysis of a JFET with Voltage-Divider Bias
o Therefore, at one point in the line is that ID = 0 and VGS = 0V
o For VGS 0,

o A second point on the line is at ID VG/RS and VGS 0. The generalized


dc load line is shown below.
o The point at which the load line intersects the transfer characteristic
curve is the Q-point.

59

C. VOLTAGE DIVIDER BIASING


Sample Problem
o Determine the approximate Q-point for the JFET with voltage-
divider bias in the Figure below.

60

30
C. VOLTAGE DIVIDER BIASING
Sample Problem
o The load line is drawn below, and the approximate Q-point
values of ID = 1.8mA and VGS = -1.8 are picked off the graph,
as indicated.

61

Q POINT STABILITY
o The transfer characteristic of a JFET can differ considerably from
one device to another of the same type.
o If, for example, a 2N5459 JFET is replaced in a given bias circuit
with another 2N5459, the transfer characteristic curve can vary
greatly, as illustrated below.

62

31
Q POINT STABILITY
o In this case, the max IDSS is 16 mA & the min IDSS is 4 mA.
o The max VGS(off ) -8V is and the min VGS(off ) is -2V This means
that if you have a selection of 2N5459s and you randomly pick
one out, it can have values anywhere within these ranges

63

Q POINT STABILITY
o If a self-bias dc load line is drawn as illustrated on the figure
above, the same circuit using a 2N5459 can have a Q-point
anywhere along the line from Q1, the minimum bias point, to Q2,
the maximum bias point.
o Accordingly, the drain current can be any value between ID1 and
ID2, as shown by the shaded area.

64

32
Q POINT STABILITY
o This means that the dc voltage at the drain can have a range of
values depending on ID.
o Also, the gate- to-source voltage can be any value between VGS1
and VGS2, as indicated.

65

Q POINT STABILITY
o Figure below illustrates Q-point stability for a self-biased JFET and
for a JFET with voltage divider bias. With voltage-divider bias, the
dependency of ID on the range of Q-points is reduced because
the slope of the load line is less than for self-bias for a given JFET.
o Although VGS varies quite a bit for both self-bias and voltage-
divider bias, ID is much more stable with voltage-divider bias.

66

33
Q POINT STABILITY
o A current-source bias circuit like Figure 8–29 has the following
values: VDD = 9V VEE = -6V, and RG = 10MΩ. To produce a 10
mA drain current and a 5 V drain voltage, determine the values of
RE and RD.

67

EXERSICE

1. Using the characteristics curve of the JFET


1. Given the characteristics of the figure above:
above, determine ID for the following
(a) Sketch the transfer characteristics directly
levels of VGS (with VDS > VP). from the drain characteristics.
(a) VGS = 0 V. (d) VGS=-1.8 V. (b) Using the figure above to establish
the values of IDSS and VP, sketch the
(b) VGS=-1 V. (e) VGS=-4 V.
transfer characteristics using
(c) VGS=-1.5 V. (f) VGS=-6 V. Shockley’s equation.

Chapter 2 68

68

34

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