'---..,. ---IR l'!ll lllll l!l!! ll!

III
.
•. ...\ ~-~✓-,-·- ~re, .
~ ., !~ ·
. . ~~
· ar.rs, ... ·
,a..
. .~ , .,.~. ·2 lt<i.i1~~:~ ~
' . . "' . ,:,;,
~ · . .;;• • ·-' ·', ,• , ···'·. -.•• , ~ ", -
JE ~\
. ~. . ·· ~· 0 I• .. - ~• ·• . .,t , . • ~- .,- ~ .,_ ,} ':~ • -." -~e:•~~ ·. l._. '\
lriStrUcfi'ori Format~ v lf,~ 1
\Ill ~~
. d.
AA lnstrudion format is
~~ r~ o~
\
0 binary for ma t hic hsp eci fies ~o mp ut: r
□ The bits of the instructions ar~ div ide d into gro ups
cal led fields.
□ The most com mo n fields in ins tru dio n for ma t
are :
l. Opcode (Op
perf orm ed such as a<!d , sub !rac t, mul tiply , shif
-
eration Code): An opc ode (op era tion cod e) fiel
t, com plem
d spe
ent, etc.
cifi
;.;,--
es the ope rati on to be
,--- -
~
✓
,
y Address : An add ress field spec ifie s a i£em o".X ,
a ddr ess or'p °roc esso r re~ isfe r, whe re ope ran j
is stor ed ,, -:: ~ - > --
/. Mo d; A_ ~de field sp;_cifies the w~y the oge ron
d or ~ ive o dd r1ass Qf the ': fj~
-.•
\ IS
-
dete rmi ned {or loca ted) .
V
. ✓ . -
\
rx - l
n'" /1\ Mo de Opc ode
,~
Add ress (or _Ope ran d)
/' . rIJ
Q)
,1reHl:its:,w ·· ,, ln.s.tr.u.~ ion i fo.n n · 1
• ~I a ,:_,• ~{-;
Y'." py ·/&~-r-"- .J>i-- A~~r
1" ~ )\ ()\7) 1 / ... ......_,_
·et (._~ vJ &,+twy-..,{
 ~ · . . ~ .. , ~-,i,, ~
~~~-
· 7;',s, \\.H1J'. · .~· ~ . .. . ,, · "'"~ , ·'
)• . . . ;_. ~*·--~·. , . ." ·.: : . ', ,,,·.,, . ~- .,:- ~~ ... ···• 0 \ '\G))i\
CPU Org aniz atio ns & Typ es of lnstr_~ction5~ \
- . z t..E
~ ~".:
. ·..:."t'St~;,.:~ ·~-.-!•,;~·:t.
!',,...4.'-c,...• ·?·-!'.t.~.J';- ~~~~¥~,.,•,-·
~"1-1?1t;•;:_~~--- ~%.£.~~g-;-;;,.?7¥1(»Z,··~.·,~.~\:J f~',':,2~):,~,iK·.'.~ll~1-']•-:-.s]~:1" 1J;~~~;.ii'.,_l.faJli:i.,r.,;;_;,;,.~;_~~~~~.;}~~;;,:~:;•.t.:.i...~~t
~:' ~ e..-~ "I---~ - ,1 • ~'"1~tj_\.:,, ~
- - ~ -~ ... -.,~<';.., ~ ~ ~ ~ ~ l i : ~ ~ 4 ' \ - , , . - 1 . i o , ~ ~ , . '&4 L • ~_,..,_-/~~~~
I~
-.....,,.~ •~~~ ~ -•.J• ~ ,
• Co1npute rs may have i.!!,_struc:tions of several diffe,r ent lengths containin g varying number of
q.._ddresses {aclclress field may be ~, 2, l_ or Q). ' -
V The nu1nber of address field in the instructio n format of a compute r depends on the internal
organizat io-;;-of its registers . ' ~ ~ - -·~
□ Most compute rs fall into o q e of the three types of CPU organiza tions / \ / I
- - . ·-· .
l. Single Accu1nula tor Organi~a tio
2. General Register Org anization,
""
3. Stac\< Organizca tion
a Tvpes----of Instructio n formats ss instructio ns:
. -
....
l. Three-add ress instrudion for1nat
2. Two-a~ ress instrudion foranat
3. One-aclclr es~ insfrudion for1nat r:::::::J============================:::;===================--==-=---=-=
I

m
~ L-J1 ~
k·ricid•w?·# z ·•;.~:;,, ·_•'( ,....
• • f t · 8 .- ::_,;
, · ,l t,
i ~~9,~!.~ !'1-s!!;u,.d Lqn o a:an<L.::-- ~ ;
 ~
JSSification of Ins,'--t_r_u_c_ti_o_n_s_b_a_s_e_d_ _-----.tP(-=,~
.~,;St.-aotkOrrqan'~at·~,on~.sat~~n~ \'.,
••l Singl e Accu mula tor Orga nh.at ion: (ii) Gene ral Regi ster Orga nisat ion: , _ A _ .....
V All opera tions are e on an o
r
It uses s_e t of gene ral purpo se regis ters {RO,
\ . , ; ( , 1
'.\

~ e d ccum ulalo r AC Tegis ter. o The op.era nd, are pul into the stack and
R1, R~ ...), q~e ofthe most wide ly accep ted lhe
.· ,l · op~ra tions ore ca:.ne d out
on th e tc:.ip of
V
1
m'o de\s for mach ine or~h ectur e today the
With one opera nd i~ci tly In the Slack.. (l'OS). The op,ero ndi a.~ implic itly
~ , . , \ - ,-
accum ulator regis ter minimi:z:es the ,pecif ied on TOS.
□ \ , Spec ifies all, operd ndsle xplici t
intern al comp lexity of them achin e l , ; '
0 It do~s not u~• an ~ddre ss fi•ld for the
and allow for"';h orl iniliuc~ons✓ ~ h e instruction form at need s ln1truc tlont nle
ADD, MUL, etc. (i.e. zero -
~ s fields accor ding to the ow_>erationr addr• ss -instru di~n forma t).
·/ The instru ction form at uses only one ,,,.-
f/ addre ss field (i.e. one-a ddre ss -
(i.e. Two or lhree -addr ess in.sh udion
--r-:------ 0 PUSH and P&P. ln1tru<tion1 a ~e med lo

I
f~rrn a!). 1
ins~c tion form at). V
,,.,_,,.
1
comm unicat e with stack, which require on
/
□
I \ ' /
For exam ple: /
1 addre ss field.
0 For exam ple: , >l \ , ',I 1
\ \. \ I
11 ·1 V ADD IN, Ri, R3 \ U R1 - R2 + R3 ( I (
\
I
/~ MlX) . - +-- - ~,. - \
This can be reduc ed from three to 'tWo ( \
( I
/~ -~+ MlX 1 addre-sses if tbe c;testination regis
c- -
ter is the
·'·1iM [Y) ~ 'AC ~
I, I,
,' (
same as one of the \Ourt e\reg i•sters.
J
(
\
' I
\) \ \
'\
JiD D Rl, R2 //R_;_ - R1. + ~ \' \ /\
\ \ ( \I
MOV Rl, R2 // Rl - R2
ADD R1, X // R l - R l + M [X) .-. .
•• ; .,,.. "'=' , \, 1 l ,
- 1 '
a Each addr ess field may speci fy a
\ gJ
l __ _~_,_o_c_e_s_s_~_'_;e_g_i_s_,e_,_~ 0
...:.''-~_m'---'~-
-;-m_, .,_,_r_'Q_P_e_~_~_d_~,_' _, 1 -1 ~--,-'-\ · ,-,-,-
 .Qn1iiiii~~~~~ -~~~:~,:~•-'"' f'~Q .,
-
.,;i
(!)Jlj{!J
I om le: EVALUATE_ C ~ (u- s_i,_1g__ Three address instructionsT
=......~~ +~1i
_.... \
p ........ ~
1-:. i,-;:cs:::
0
,.. ~&
•y;.:·:-.:o.~~c&.a. .t..:-. io--.n-s.i..;A
-. . r.~
...~1!9; ,.c~ ~~~:u::,:::t:t:;~i;li-,w,;, :. .;~o ~a~re fe~hed from mep10ry f'"I
~B \ \
j ► Transferred into the pr~essor where their Su.,!!!. is computed Yb ~
i ► The Result is then sent back to the memory & stored in location [
- - p ---
I
@pcJ,e_~ ~"40., Md) f;\JYU -P-£)4 I \ C:,o~ M~ 2-
I ./
(AL
•y ~ ~ {~ -
I AD,D C, A, B // M[C] < M[A]+M[B]
I' '.
I
" --~ S\ i;:_
c.. ~~~
~
~ -
-- --
~
< •
~ - ~; · }!-;
lci.\.'.~ l.i!~ttoi.!llit?'
f" ° ~ \ ~~~ ... ~ji,. _ ... . , ~ ·- _ 1 rs a-., iti1
 ~ ~ @
Two addr ess 1nstru ct1on s
- m,t®3

~ ..~~-~ ~ll'.~lt:l..~ ~ ~ , : • ~ ~~ ~"."t".::iffi'""'x~ ,.)",-.~.,..'";!:P.f;2, ·-~~ ..... , r._.___.,,..,,,~,.........~-~ . ........... , - •

. , .,•!'_
' ' - •• . --,
...... ,- ,.."T'"l'.-,t;i;:.,.. a.-: ~ '.. _.... :.:_--...,... •.+.·· ~--...;. l~J.,;_ ;,.;.- .. ::.- .. -
.,,. ' ~.,, -,·.
• ,...~Jt·
...-~"'l'f""..·-·~' -~-;:.·.-'1_ .,.- ......,~-• -...
~~~~~ -;[,:.~~~~~--. -~-..;;..~~':-' . .-.l..JT>...~,,..>t-:-,"•,ef-;..,L:.. -~~ ·•
■ .,_
v l'l!Ra \
L . ~~~.~ ~_,, ,,;,.,., ____L ~-,,,..;.'}"~ ...~ " " '
-~E ififl i rs~;.:~t-.. •. -'-/4~1taiai~~-~ :_.:~. "-
Two-addres s instruction for1nat

> Two address instruction s are most common in commercia l cor:nputers

► It has two address fields
> Each address field may specify a processor register or a memory operand.
~

a===
I\ L -- "'S
• =ga6 ~ .
> Example Instruction : ADD R 1, R2 //Rl _~Rl+R2
- ·, .

MOVR1,R 2 // Rl ~ R2
.... ·':: ~
~ -
- - --- -- ---- - -- -- -- - - -·
IAJ !..J). .:' :.it;.:..:! ,: ~; 4\!.'~,1
,.. lJLJ~ . . _. .. ·' ~, : ,__ . . -· · ::...;.:~...~i..Ji.•.,.;,~;_.•~., ,;,.,,'::;,. . ,. , ....... ....,..JJk.;;"L::,. ~:.;• .. ,, i u.: ;,,,.. .• ~,..,, 4 ·,:.,_., s.-·~,.;.ss ·::rilb&li:::-s► }4§ .~ ,. ___&
 I ' ' I
X ,.
Q -

_g
(t)
!l
••

" -. . ..............
" -. . ..............

\ ~ ~
n n
.. .. .. L -- '

i i
,..3...,
~\...~..... )>
a- -, 1

)~ r -- ,

~
 .,.,,,.., I ' •
('\-
~ \:
One-a ddress instru ction forma t
> It has only one address field. The oper ~d speci fied in the ins~ruction may be
source
or destination, depen ding on instruction
../ One addre ss instructions use a f plied ACCUMULATOR (t.C~ ister for all~ a
manipulation. - · "'
-----. s in accumµlg_tor so there is no need to
► Implied means that the CPU ,1!regdy kgaw that one operan dj
-- -------
•
I •
• ""'
specify it.
-~
> All operations done betwe e accu or regist er an~ mory gper~ j
✓ It is also called Single Accumulator Orga nizat ion
~
> ---■---~,•~••• ADD
-••--••~ ctiet,·
E>u~1Mple h,stru ---=._ X-
- // AC
II t AC + M[X)
,~,rW
;t.. -- ~-w;;il\"
1 .• l
'b\ ~J~~lj.-:.t-i:
-·· -► ~d:tMrtfr1:lit;.e;•4
.,· ,. ,;;r£1M_, ~t:-•,f-~;'ii..:;-~:tl-....
-~.fP
..~ ~-~-- .:;;..-....~~-~-~--
,:. ;~/t~;.';~;.,,...,._l,;·
1
4 _• L .~~..,.· •
- •·- • • J H !"
 .. ~~ ~,, \
c::A+S
·y ' ·'
(using One address inStructions I
iii ;i?if); ~
\ ' . ( '

~ ADA /

ADD -B
~ REC

LOAD and STORE instrudion : used for transfers to and fror.) memory to AC regi ster

• LOAD instruction: Operand (like A) specifies the source operand and the destination
location is AC register. Eg: LOAD A // AC +-- M[A)
• STORE instruction: Operand {like C) specifies the destinatio n location and the source i{
1M£t~!f1¥tr~. iA~1ei¥HZ atte #,9inS1(2J!~- ~ ~a·
m //M{C] +-- A~rat . 7 0J ~ ~-
 2o.o - / 4 LW1
9--f-q c k _
30 ~ q d d, ~ .
C : > ~ ~ ~ ~
-~
~ A ~ t i ' J. e}_J_ ...i_n --1-4 . l , . ~ d-o M
c/t fA}y(_ qr, a_ f
[ hlce ~? nvL)
~ p ~ g f,r;p
f t · ~ ~ r/i~
_____,..--i ~ d -
 {J
-z.Ello . .~ "-~
4,fip
J ~ ~.,:_'EJJ :\ ;2:
~~
.,-, '&
...
■■
~-~
1
- .. , ., , .
. EVALUATE
d d r e s s instructions
c.;=A + B (using~@•ne~am e :>llmAf/#1/ffi;ggrar@
l
'X a m p e. ~
.....·r-R":,• ...--:...:.._·,. • . ;./ t : 1
/Q@
ish N o ta ti o n : A B +
V
Postfix /R ev er se Pol
vi PUSH, A ~.~ I I TOS ~ A rr>< >-.'I\
PUSH B I I TOS ~ B
ADD I I TOS ~ (A+B) ➔ \
POPC II MCCJ ~ ros
~
~ eJ
~ - I
 ide:
Key D D
PipelningtarpepiiErempiejSpace
Pipelining? What
What is
Overlap is
way A
Pipelining?
of
execution speeding
of up me
multiple execution DieyemiACA
instructions of
instructionsPPGied-23jSauukut
 PipeiiDroLHEeRHEXAmpetSpace ine niaLyeHACAPPOtect23Sien
What is Pipelining?
O Key idea: break big computation up into
pieces
Non-pipelined: 1operatio
finishes every Ins
1ns

O Separate each piece with a pipeline register

Pipelined: 1 operation
finishes every 200ps
200ps 200ps 200ps 200ps 200ps
Pipeline
K D 218/ Peatster
 teCanaepEempieSpeseDigremAD

Pipelining: Definition
o Pipelining is a technique of decomposing a sequential process into sub
operations, with each sub-operation being executed in a special
dedicated segments that operates concurrently with all other segments.
DEach segment performs partial processing dictated by the way task is
partitioned.

aThe result obtained from each segment is transferred to next segment.

a The final result is obtained when data have passed through allsegments.
 4COeegiDempiejs
Pipelining Analogy: An Industrial Assembly Line
o The concept of pipelining in computer organization is analogous to an industrial assembly line.
As in industry there different division like:
1. Manufacturing division,
2 Packing division
3. Delivery division
Aproduct is manufactured by manufacturing division,
While it is packed by packing division a new product is manufacturedby manufacturing unit.
While this product is delivered by delivery unit a third product is manufactured by
manufacturing unit and second product has been packed. Thus pipeline results in speeding the
overall process. Produc/Time Time 1 Time 2 Time 3 Time4 Time 5...

Manufacturing P1 P2 P3 P4 P5

Packing P1 P2 P3 P4
D) 6.06/21.36 P1 P2 Pas
K DeliverV
 peiineCURLepxepa Speue meD
Example:
O
Suppose the following expression is to be evaluated for i =1, 2, 3, ....., 7
A,* B+C for i=1, 2, 3, ..., 7 V
O Within Pipeline, each
sub-operation is to be implemented in a
Each segment has one or two registers & a segment.
combinational circuit.
D This operation requires three segments. The
sub-operations in each segment of
pipeline are as follows:
R1 -A, R2 - B Load A,and BË
R3 -R1* R2, R4 -C; Multiply and load C;
B
RoRù + R4 Add
 A,*B+ C
for0=1,2, 3, ...,7 |R3 4- R1 * R2, R4 4-C
R5 R3 + R4 Multiply and load C
Add
Pipeline Processing:
B, Memory C
Segment 1
R1 R2

Multiplier
Segment 2
R3 R4

Adder
Segment 3

R5
CC
Contents of Registers in Pipeline:
Clock Segment3
Pulse Segment 1 Segment 2
Number R1 R2 R3 R4 R5
AT B1
2 A2 B2 A1'B1 C1
3 A3 B3 A2 B2 C2 A1'B1 + C1
4 A4 B4 A3* B3 C3 A2* B2 +C2
5 A5 B5 A4B4 C4 A3* B3 + C3
6 A6
A B6 A5 B5 C5 A4 B4+ C4
7 A7 B7 A6 B6 C6 A5* B5 +C5
A7B7 C7 A6 B6 +C6
A7*B7 + C7
 Example:
Clock
General Structure of 3 Segment Pipeline

Input S1 S2 S3

" Each segmnent consists of acombinational circuit S, that

stre am flowing through the pipe. performs a sub-operation over the data
" The segments are separated by registers R; that
hold the intermediate results between the stages.
" Information flows between adjacent stages
under the control of acommon clock applied to all the
registers simultaneously.
We cetine d iask as ihe total operaiion pertormed going through all the
1641/2136 segments in the |Ccpipeline.
 Space Time Diagram:
The behavior of a|I
pipeline can be illustrated with a space-time diagram. It
the segment utilization shows
as a function of time.
C
OIf Ti be the execution time for i = 1.2.3.... 7 then space
time diagram is:

1 2 3 | 4 |55|6 6 |78 Clockcycles

Segment 1 T1 T2 | T3 T4 T5 T6 T7
2 T1 T2 | T3 T4 T5 T6 T7
3 T1 T2 T3 T4 T5 T6T7
ning in, cornptiterarchitecture Whatis arithmeticpipelining
www.prudenc
mantissA
Expt

ih order to
perfom aHtmahe operhans Heen it s
Shed- uþ exeutien frorer,
he Pieit?
Called "Ait hutmkeSeg Subtrachen
Exa-þle: Muli}liCatem of fred þcit

SuLtnciy:
Flosing þoint addiie & exhoht R
() Compare tea
x+y Li) Aligh ter hantiss
OX=A X 24) Ali9 manticra
Y= B X2
We hecd 4 Segments R
X= o lolo X 2 Seghtnt add| Su tract
y=0o||oxg3 Jü) chere lar_r harra
expont& alig mhtin.
S
X= o:loloX 2 ’ o ooo|| X2 tmahissg R
y= ooo l1 X21 X25’(i)add Normahie ResH
tu Ai4st
o lol|| ( )Normalis mntevbenetr
|·olo|||x 2
R

Saraswat Arithmeti Plpelining

914 stage instrlcton plnrtrtICibampipeining
Conselative |FZDA|FCEX
An Ihstuchey bibelie Yeadr
Ihstuci fnm memoy wite preuior Fz/DelcEx
FLDA
executed /h Qa hos seyht 2
Ihstnchoh ave
Ex
of þi~elin FE DA Fc|
ieine 3
Instucien l(Brd
FI||E
Exa-þle: 4-Segment FI
each lhstmciey s
of
The bcerihg Seqmestr.
diuided into y- fetches an Ihctnei
Segmnt Rat F DAFoEX
DFI s tei decode Ihstck 5
segment tRat
2DA_ s tee efective address.
Calculate
and fetcherta 6
seghest tCat
OFos fea FDA
oerand. cuts7
segnent tat exe
Fx s tee
Ihstnchh

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