ADM1026 ONSemiconductor
ADM1026 ONSemiconductor
PIN ASSIGNMENT
GPIO16/THERM
AIN0(0V – 3V)
AIN1(0V – 3V)
AIN2(0V – 3V)
AIN3(0V – 3V)
AIN4(0V – 3V)
GPIO10
GPIO12
GPIO13
GPIO14
GPIO15
GPIO11
48
47
46
45
44
43
42
41
40
39
38
37
GPIO9 1 PIN 1 36 AIN5(0V – 3V)
GPIO8 2 35 AIN6(0V – 2.5V)
FAN0/GPIO0 3 34 AIN7(0V – 2.5V)
FAN1/GPIO1 4 33 +VCCP
FAN2/GPIO2 5 32 +12 VIN
FAN3/GPIO3 6 ADM1026 31 –12 VIN
TOP VIEW
3.3V MAIN 7 30 +5 VIN
DGND 8 29 VBAT
FAN4/GPIO4 9 28 D2+/AIN8(0V – 2.5V)
FAN5/GPIO5 10 27 D2–/AIN9(0V – 2.5V)
FAN6/GPIO6 11 26 D1+
FAN7/GPIO7 12 25 D1-/NTESTIN
SCL 13
SDA 14
ADD/NTESTOUT 15
CI 16
INT 17
PWM 18
RESETSTBY 19
RESETMAIN 20
AGND 21
3.3V STBY 22
DAC 23
VREF 24
ADD/ NTESTOUT SDA SCL 3.3V STBY 3.3V MAIN
VCC
GPIO15 RESET IN
GPIO14
GPIO13 3.3V MAIN
RESETMAIN
RESET
GPIO12 SERIAL BUS
GPIO GENERATOR VCC
GPIO11 INTERFACE
REGISTERS
GPIO10
100k
GPIO9
GPIO8 3.3V STBY RESETSTBY
VCC RESET
GENERATOR
FAN 7/GPIO7
FAN 6/GPIO6 PWM REGISTER
PWM
FAN 5/GPIO5 AND CONTROLLER
FAN 4/GPIO4 FAN
FAN 3/GPIO3 SPEED VALUE AND
COUNTER LIMIT
FAN 2/GPIO2 REGISTERS
FAN 1/GPIO1
ADDRESS
FAN 0/GPIO0
POINTER
LIMIT
VBAT REGISTER
COMPARATORS
+5 VIN
8k BYTES
–12 VIN EEPROM INTERRUPT
+12 VIN STATUS CI
AUTOMATIC REGISTERS VCC
+VCCP
FAN SPEED
AIN0 (0V - +3V) CONTROL 100k
INT MASK
AIN1 (0V - +3V) REGISTERS
AIN2 (0V - +3V) INT
INPUT
AIN3 (0V - +3V) ADM1026
ATTENUATORS
AIN4 (0V - +3V) AND INTERRUPT VCC
ANALOG MASKING
AIN5 (0V - +3V)
MULTIPLEXER
AIN6 (0V - +2.5V) 100k
8−BIT
AIN7 (0V - +2.5V) ADC GPIO16/THERM
D2+/AIN8 (0V - +2.5V)
CONFIGURATION
D2–/AIN9 (0V - +2.5V) REGISTERS
TO GPIO
D1+ BAND GAP REGISTERS
D1–/NTESTIN REFERENCE ANALOG
OUTPUT REGISTER DAC
BAND GAP
TEMPERATURE AND 8−BIT DAC
SENSOR
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ADM1026
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ADM1026
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ADM1026
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Supply Voltage, 3.3 V STBY 3.0 3.3 5.5 V
Supply Current, ICC Interface Inactive, ADC Active − 2.5 4.0 mA
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy − − 3.0 C
Resolution − 1.0 − C
External Diode Sensor Accuracy 0C < TD < 100C − − 3.0 C
Resolution − 1.0 − C
Remote Sensor Source Current High Level − 90 − mA
Low Level − 5.5 −
ANALOG-TO-DIGITAL CONVERTER
(Including MUX and ATTENUATORS)
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ADM1026
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter Test Conditions/Comments Min Typ Max Unit
FAN RPM-TO-DIGITAL CONVERTER (Note 6)
Accuracy − − 12 %
Full-scale Count − − 255
FAN0 to FAN7 Nominal Input RPM (Note 5) Divisor = 1, fan count = 153 − 8800 − RPM
Divisor = 2, fan count = 153 − 4400 −
Divisor = 4, fan count = 153 − 2200 −
Divisor = 8, fan count = 153 − 1100 −
Internal Clock Frequency 20 22.5 25 kHz
OPEN DRAIN O/Ps, PWM, GPIO0 to 16
Output High Voltage, VOH IOUT = 3.0 mA, VCC = 3.3 V 2.4 − − V
High Level Output Leakage Current, IOH VOUT = VCC − 0.1 1.0 mA
Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 3.3 V − − 0.4 V
PWM Output Frequency − 75 − Hz
DIGITAL OUTPUTS (INT, RESETMAIN, RESETSTBY)
Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 3.3 V − − 0.4 V
RESET Pulse Width 140 180 240 ms
OPEN DRAIN SERIAL DATABUS OUTPUT (SDA)
Output Low Voltage, VOL IOUT = –3.0 mA, VCC = 3.3 V − − 0.4 V
High Level Output Leakage Current, IOH VOUT = VCC − 0.1 1.0 mA
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.2 − − V
Input Low Voltage, VIL − − 0.8 V
Hysteresis − 500 − mV
DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16) (Note 7 and 8)
Input High Voltage, VIH VCC = 3.3 V 2.4 − − V
Input Low Voltage, VIL VCC = 3.3 V 0.8 − − V
Hysteresis (Fan 0 to 7) VCC = 3.3 V − 250 − mV
RESETMAIN, RESETSTBY
RESETMAIN Threshold Falling Voltage 2.89 2.94 2.97 V
RESETSTBY Threshold Falling Voltage 3.01 3.05 3.10 V
RESETMAIN Hysteresis − 60 − mV
RESETSTBY Hysteresis − 70 − mV
DIGITAL INPUT CURRENT
Input High Current, IIH VIN = VCC –1.0 − − mA
Input Low Current, IIL VIN = 0 − − 1.0 mA
Input Capacitance, CIN − 20 − pF
EEPROM RELIABILITY
Endurance (Note 9) 100 700 − kcycles
Data Retention (Note 10) 10 − − Years
SERIAL BUS TIMING
Clock Frequency, fSCLK See Figure 2 for All Parameters. − − 400 kHz
Glitch Immunity, tSW − − 50 ns
Bus Free Time, tBUF 4.7 − − ms
Start Setup Time, tSU; STA 4.7 − − ms
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ADM1026
Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter Test Conditions/Comments Min Typ Max Unit
SERIAL BUS TIMING
Start Hold Time, tHD; STA 4.0 − − ms
SCL Low Time, tLOW 4.7 − − ms
SCL High Time, tHIGH 4.0 − − ms
SCL, SDA Rise Time, tr − − 1000 ns
SCL, SDA Fall Time, tf − − 300 ns
Data Setup Time, tSU; DAT 250 − − ns
Data Hold Time, tHD; DAT 300 − − ns
1. All voltages are measured with respect to GND, unless otherwise specified.
2. Typicals are at TA = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
4. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate
only for VBAT voltages greater than 1.5 V (see Figure 14).
5. Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms 11.38 ms measurements on analog input and internal
temperature channels, and 2 ms 34.13 ms measurements on external temperature channels.
6. The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number
of fans connected and the fan speed. See the Fan Speed Measurement section for more details.
7. ADD is a three-state input that may be pulled high, low, or left open circuit.
8. Logic inputs accept input high voltages up to 5.0 V even when device is operating at supply voltages below 5.0 V.
9. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40C, +25C, and +85C. Typical endurance
at +25C is 700,000 cycles.
10. Retention lifetime equivalent at junction temperature (TJ ) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on activation
energy of 0.6 V derates with junction temperature as shown in Figure 15.
t LOW tF
t HD; STA
tR
SCL
SDA
t BUF
P S S P
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ADM1026
25 14
20
12
15
10
10
D+ TO GND
5 8
0 250mV
6
–5
D+ TO VCC
–10 4
–15 100mV
2
–20
0
–25
0 30 60 90 120 0 100 200 300 400 500 600
LEAKAGE RESISTANCE (M) FREQUENCY (MHz)
Figure 3. Temperature Error vs. PCB Track Figure 4. Temperature Error vs. Power Supply
Resistance Noise Frequency
12 110
100mV
100
60mV
10
40mV 90
TEMPERATURE ERROR (5C)
80
8
70
READING (5C)
60
6
50
4 40
30
2 20
10
0 0
0 100 200 300 400 500 600 0 10 20 30 40 50 60 70 80 90 100 110
FREQUENCY (MHz) PIII TEMPERATURE (5C)
Figure 5. Temperature Error vs. Common-mode Figure 6. Pentium) III Temperature vs. ADM1026
Noise Frequency Reading
5 80
70
0
TEMPERATURE ERROR (5C)
TEMPERATURE ERROR (5C)
60
–5
50
–10 40
30
–15 100mV
20
–20 60mV
40mV
10
–25 0
0 10 20 30 40 50 100 200 300 400 500 600
CAPACITANCE (nF) FREQUENCY (MHz)
Figure 7. Temperature Error vs. Capacitance Figure 8. Temperature Error vs. Differential-mode
Between D+ and D– Noise Frequency
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ADM1026
450 3.0
400
2.5
350
RESET TIMEOUT (ms)
300 2.0
IDD (mA)
250
1.5
200
150 1.0
100
0.5
50
0
0
–40 –20 0 20 40 60 80 100 120 140 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
TEMPERATURE (5C) VCC (V)
Figure 9. Powerup Reset Timeout vs. Temperature Figure 10. Supply Current vs. Supply Voltage
1.8 1.0
1.6
0.5
1.4
TEMPERATURE ERROR (5C)
1.2 0
1.0
–0.5
0.8
0.6 –1.0
0.4
–1.5
0.2
0 –2.0
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (5C) TEMPERATURE (5C)
Figure 11. Local Sensor Temperature Error Figure 12. Remote Sensor Temperature Error
3.5
120
3.0
100
2.5
VBAT MEASUREMENT
TEMPERATURE (5C)
80
2.0
60
1.5
40
1.0
20
0.5
0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 1 2 3 4
TIME (s) VBAT VOLTAGE
Figure 13. Response to Thermal Shock Figure 14. VBAT Measurement vs. Voltage
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ADM1026
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ADM1026
ADM1026 is powered down, unlike the data in the volatile Serial Bus Interface
registers. Although referred to as read-only memory, the Control of the ADM1026 is carried out via the serial
EEPROM can be written to (as well as read from) via the system management bus (SMBus). The ADM1026 is
serial bus in exactly the same way as the other registers. The connected to this bus as a slave device, under the control of
main differences between the EEPROM and other registers a master device.
are: The ADM1026 has a 7-bit serial bus slave address. When
An EEPROM location must be blank before it can be the device is powered on, it does so with a default serial bus
written to. If it contains data, it must first be erased. address. The 5 MSBs of the address are set to 01011, and the
Writing to EEPROM is slower than writing to RAM. 2 LSBs are determined by the logical states of Pin 15
ADD/NTESTOUT. This pin is a three-state input that can be
Writing to the EEPROM should be restricted because grounded, connected to VCC, or left open-circuit to give
its typical cycle life is 100,000 write operations, due to three different addresses.
the usual EEPROM wear-out mechanisms.
Table 6. ADDRESS PIN TRUTH TABLE
The EEPROM in the ADM1026 has been qualified for
two key EEPROM memory characteristics: memory cycling ADD Pin A1 A0
endurance and memory data retention. GND 0 0
Endurance qualifies the ability of the EEPROM to be No Connect 1 0
cycled through many program, read, and erase cycles. In real VCC 0 1
terms, a single endurance cycle is composed of four
independent, sequential events, as follows: If ADD is left open-circuit, the default address is 0101110
1. Initial page erase sequence (5Ch). ADD is sampled only at powerup on the first valid
2. Read/verify sequence SMBus transaction, so any changes made while the power
3. Program sequence is on (and the address is locked) have no effect.
4. Second read/verify sequence The facility to make hardwired changes to device
addresses allows the user to avoid conflicts with other
In reliability qualification, every byte is cycled from 00h devices sharing the same serial bus, for example if more than
to FFh until a first fail is recorded, signifying the endurance one ADM1026 is used in a system.
limit of the EEPROM memory.
Retention quantifies the ability of the memory to retain its General SMBus Timing
programmed data over time. The EEPROM in the ADM1026 Figure 16 and Figure 17 show timing diagrams for general
has been qualified in accordance with the formal JEDEC read and write operations using the SMBus. The SMBus
Retention Lifetime Specification (A117) at a specific junction specification defines specific conditions for different types
temperature (TJ = 55C) to guarantee a minimum of 10 years of read and write operations, which are discussed later in this
retention time. As part of this qualification procedure, the section. The general SMBus protocol* operates as follows:
EEPROM memory is cycled to its specified endurance limit 1. The master initiates data transfer by establishing a
described above before data retention is characterized. This start condition, defined as a high-to-low transition
means that the EEPROM memory is guaranteed to retain its on the serial data line (SDA) while the serial clock
data for its full specified retention lifetime every time the line SCL remains high. This indicates that a data
EEPROM is reprogrammed. Note that retention lifetime stream follows. All slave peripherals connected to
based on an activation energy of 0.6 V derates with TJ, as the serial bus respond to the start condition and
shown in Figure 15. shift in the next 8 bits, consisting of a 7-bit slave
300 address (MSB first) and an R/W bit, which
determine the direction of the data transfer, that is,
250 whether data is written to or read from the slave
device (0 = write, 1 = read).
The peripheral whose address corresponds to the
RETENTION (Years)
200
trans-mitted address responds by pulling the data
150 line low during the low period before the ninth
clock pulse, known as the acknowledge bit, and
100 holding it low during the high period of this clock
pulse. All other devices on the bus remain idle
50 while the selected device waits for data to be read
from or written to it. If the R/W bit is 0, the master
0 writes to the slave device. If the R/W bit is 1, the
40 50 60 70 80 90 100 110 120
JUNCTION TEMPERATURE (5C) master reads from the slave device.
Figure 15. Typical EEPROM Memory Retention
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ADM1026
2. Data is sent over the serial bus in sequences of nine Before doing a read operation, it may first be
clock pulses, 8 bits of data followed by an necessary to do a write operation to tell the slave
acknowledge bit from the slave device. Data what type of read operation to expect and/or the
transitions on the data line must occur during the address from which data is to be read.
low period of the clock signal and remain stable 3. When all data bytes have been read or written, stop
during the high period, because a low-to-high conditions are established. In write mode, the master
transition when the clock is high may be interpreted pulls the data line high during the 10th clock pulse
as a stop signal. to assert a stop condition. In read mode, the master
If the operation is a write operation, the first data device releases the SDA line during the low period
byte after the slave address is a command byte. before the ninth clock pulse, but the slave device
This tells the slave device what to expect next. It does not pull it low (called No Acknowledge). The
may be an instruction telling the slave device to master takes the data line low during the low period
expect a block write, or it may simply be a register before the 10th clock pulse, then high during the
address that tells the slave where subsequent data is 10th clock pulse to assert a stop condition.
to be written.
*If it is required to perform several read or write operations in
Because data can flow in only one direction as succession, the master can send a repeat start condition instead
defined by the R/W bit, it is not possible to send a of a stop condition to begin a new operation.
command to a slave device during a read operation.
1 9 1 9
SCL
SDA 0 1 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE SLAVE
FRAME 1 FRAME 2
SLAVE ADDRESS COMMAND CODE
1 9 1 9
SCL
(CONTINUED)
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY ACK. BY STOP BY
SLAVE SLAVE MASTER
FRAME 3 FRAME N
DATA BYTE DATA BYTE
1 9 1 9
SCL
SDA 0 1 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE MASTER
FRAME 1 FRAME 2
SLAVE ADDRESS DATA BYTE
1 9 1 9
SCL
(CONTINUED)
SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY NO ACK. STOP BY
MASTER MASTER
FRAME 3 FRAME N
DATA BYTE DATA BYTE
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ADM1026
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ADM1026
In the ADM1026, the write byte/word protocol is used for byte is the actual data. Bit 1 of EEPROM Register 3 must be
four purposes. The ADM1026 knows how to respond by the set. This is illustrated in Figure 22.
value of the command byte and EEPROM Register 3. 1 2 3 4 5 6 7 8 9 10
The first purpose is to write a single byte of data to RAM. EEPROM EEPROM
SLAVE ADDRESS ADDRESS
In this case, the command byte is the RAM address from 00h S
ADDRESS
W A
HIGH BYTE
A
LOW BYTE
A DATA A Y
(80h TO 9Fh) (00h TO FFh)
to 6Fh and the (only) data byte is the actual data. This is
illustrated in Figure 19. Figure 22. Single-Byte Write to EEPROM
1 2 3 4 5 6 7 8
S
SLAVE
W A
RAM
ADDRESS A DATA A P
Block Write
ADDRESS
(00h TO 6Fh) In this operation, the master device writes a block of data
to a slave device. The start address for a block write must
Figure 19. Single Byte Write to RAM
have been set previously. In the case of the ADM1026, this
The protocol is also used to set up a 2-byte EEPROM is done by a Send Byte operation to set a RAM address or by
address for a subsequent read or block read. In this case, the a write byte/word operation to set an EEPROM address.
command byte is the high byte of the EEPROM address 1. The master device asserts a start condition on the
from 80h to 9Fh. The (only) data byte is the low byte of the SDA.
EEPROM address. This is illustrated in Figure 20. 2. The master sends the 7-bit slave address followed
1 2 3 4 5 6 7 8 by the write bit (low).
SLAVE
EEPROM
ADDRESS
EEPROM 3. The addressed slave device asserts an ACK on the
S W A A ADDRESS A P
ADDRESS HIGH BYTE LOW BYTE SDA.
(80h TO 9Fh) (00h TO FFh)
4. The master sends a command code that tells the
Figure 20. Setting an EEPROM Address slave device to expect a block write. The
ADM1026 command code for a block write is A0h
If it is required to read data from the EEPROM
(10100000).
immediately after setting up the address, the master can
5. The slave asserts an ACK on the SDA.
assert a repeat start condition immediately after the final
6. The master sends a data byte (20h) that tells the
ACK and carry out a single-byte read or block read operation
slave device that 32 data bytes are being sent to it.
without asserting an intermediate stop condition. In this
The master should always send 32 data bytes to
case, Bit 0 of EEPROM Register 3 should be set.
the ADM1026.
The third use is to erase a page of EEPROM memory.
7. The slave asserts an ACK on the SDA.
EEPROM memory can be written to only if it is previously
8. The master sends 32 data bytes.
erased. Before writing to one or more EEPROM memory
9. The slave asserts an ACK on the SDA after each
locations that are already programmed, the page or pages
data byte.
containing those locations must first be erased. EEPROM
10. The master sends a packet error checking (PEC)
memory is erased by writing an EEPROM page address plus
byte.
an arbitrary byte of data with Bit 2 of EEPROM Register 3
11. The ADM1026 checks the PEC byte and issues an
set to 1.
ACK if correct. If incorrect (NACK), the master
Because the EEPROM consists of 128 pages of 64 bytes,
resends the data bytes.
the EEPROM page address consists of the EEPROM
12. The master asserts a stop condition on the SDA to
address high byte (from 80h to 9Fh) and the two MSBs of the
end the transaction.
low byte. The lower six bits of the EEPROM address (low
byte only) specify addresses within a page and are ignored
during an erase operation. S SLAVE W A
COMMAND
A0h BLOCK A BYTE A DATA 1 A DATA 2 A
DATA A PEC A P
ADDRESS COUNT 32
WRITE
1 2 3 4 5 6 7 8 9 10
EEPROM EEPROM
S
SLAVE
W A
ADDRESS
A
ADDRESS
A
ARBITRARY A Y Figure 23. Block Write to EEPROM or RAM
ADDRESS HIGH BYTE LOW BYTE DATA
(80h TO 9Fh) (00h TO FFh)
When performing a block write to EEPROM, Bit 1 of
Figure 21. EEPROM Page Erasure EEPROM Register 3 must be set. Unlike some EEPROM
devices that limit block writes to within a page boundary,
Page erasure takes approximately 20 ms. If the EEPROM
there is no limitation on the start address when performing
is accessed before erasure is complete, the ADM1026
a block write to EEPROM, except:
responds with No Acknowledge.
Last, this protocol is used to write a single byte of data to There must be at least 32 locations from the start
EEPROM. In this case, the command byte is the high byte address to the highest EEPROM address (9FF) to avoid
of the EEPROM address from 80h to 9Fh. The first data byte writing to invalid addresses.
is the low byte of the EEPROM address, and the second data If the addresses cross a page boundary, both pages must
be erased before programming.
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ADM1026
ADM1026 Read Operations ADM1026 always returns 32 data bytes (20h), the
The ADM1026 uses the SMBus read protocols described maximum allowed by the SMBus 1.1 specification.
here. 10. The master asserts an ACK on the SDA.
11. The master receives 32 data bytes.
Receive Byte
12. The master asserts an ACK on the SDA after each
In this operation, the master device receives a single byte data byte.
from a slave device as follows: 13. The ADM1026 issues a PEC byte to the master.
1. The master device asserts a start condition on the The master should check the PEC byte and issue
SDA. another block read if the PEC byte is incorrect.
2. The master sends the 7-bit slave address followed 14. A NACK is generated after the PEC byte to signal
by the read bit (high). the end of the read.
3. The addressed slave device asserts an ACK on the 15. The master asserts a stop condition on the SDA to
SDA. end the transaction.
4. The master receives a data byte.
5. The master asserts a NO ACK on the SDA.
COMMAND
6. The master asserts a stop condition on the SDA to S SLAVE
ADDRESS
W A A1h BLOCK A S SLAVE
ADDRESS
R
READ
end the transaction.
In the ADM1026, the receive byte protocol is used to read
a single byte of data from a RAM or EEPROM location A
BYTE
A DATA 1 A
DATA
A PEC A P
COUNT 32
whose address has previously been set by a send byte or
write byte/word operation. Figure 24 shows this. When
reading from EEPROM, Bit 0 of EEPROM Register 3 must Figure 25. Block Read from EEPROM or RAM
be set.
1 2 3 4 5 6 When block reading from EEPROM, Bit 0 of EEPROM
SLAVE
Register 3 must be set.
S R A DATA A P
ADDRESS Note that although the ADM1026 supports Packet Error
Checking (PEC), its use is optional. The PEC byte is
Figure 24. Single-Byte Read from EEPROM or RAM calculated using CRC-8. The Frame Check Sequence (FCS)
conforms to CRC-8 by the polynomial:
Block Read
In this operation, the master device reads a block of data C(x) + x 8 ) x 2 ) x ) 1 (eq. 1)
from a slave device. The start address for a block read must Consult the SMBus 1.1 Specification for more information.
have been set previously. In the case of the ADM1026 this
is done by a send byte operation to set a RAM address, or by Measurement Inputs
a write byte/word operation to set an EEPROM address. The The ADM1026 has 17 external analog measurement pins
block read operation consists of a send byte operation that that can be configured to perform various functions. It also
sends a block read command to the slave, immediately measures two supply voltages, 3.3 V MAIN and 3.3 V
followed by a repeated start and a read operation that reads STBY, and the internal chip temperature.
out multiple data bytes as follows: Pins 25 and 26 are dedicated to remote temperature
1. The master device asserts a start condition on the measurement, while Pins 27 and 28 can be configured as
SDA. analog inputs with a range of 0 V to 2.5 V, or as inputs for
2. The master sends the 7-bit slave address followed a second remote temperature sensor.
by the write bit (low). Pins 29 to 33 are dedicated to measuring VBAT, +5.0 V,
3. The addressed slave device asserts an ACK on the −12 V, +12 V supplies, and the processor core voltage VCCP.
SDA. The remaining analog inputs, Pins 34 to 41, are
4. The master sends a command code that tells the general-purpose analog inputs with a range of 0 V to 2.5 V
slave device to expect a block read. The (Pins 34 and 35) or 0 V to 3.0 V (Pins 36 to 41).
ADM1026 command code for a block read is A 1h
(10100001). A-to-D Converter (ADC)
5. The slave asserts an ACK on the SDA. These inputs are multiplexed into the on-chip, successive
6. The master asserts a repeat start condition on the approximation, analog-to-digital converter. The ADC has a
SDA. resolution of 8 bits. The basic input range is 0 V to 2.5 V,
7. The master sends the 7-bit slave address followed which is the input range of AIN6 to AIN9, but five of the
by the read bit (high). inputs have built-in attenuators to allow measurement of
8. The slave asserts an ACK on the SDA. VBAT, +5.0 V, -12 V, +12 V, and the processor core voltage
9. The ADM1026 sends a byte count data byte that VCCP, without any external components. To allow the
tells the master how many data bytes to expect. The tolerance of these supply voltages, the ADC produces an
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ADM1026
output of 3/4 full scale (decimal 192) for the nominal input averaged to reduce noise, so the total conversion time for each
voltage, and so has adequate headroom to cope with over input is 11.38 ms.
voltages. Table 7 shows the input ranges of the analog inputs Measurements on the remote temperature (D1 and D2)
and output codes of the ADC. inputs take 2.13 ms. These are also measured 16 times and
When the ADC is running, it samples and converts an are averaged, so the total conversion time for a remote
analog or local temperature input every 711 ms (typical value). temperature input is 34.13 ms.
Each input is measured 16 times and the measurements are
−
−
−
8.000−8.063 −6.750−6.678 3.333−3.359 2.000−2.016 2.000−2.016 1.500−1.512 1.500−1.512 1.250−1.260 128 10000000
(1⁄2 scale)
−
−
−
12.000−12.063 −2.125−2.053 5−5.026 3.330−3.347 3.000−3.016 2.250−2.262 2.250−2.262 1.875−1.885 192 11000000
(3⁄4 scale)
−
−
−
15.313−15.375 1.705−1.777 6.38−6.406 4.249−4.267 3.828−3.844 2.871−2.883 2.871−2.883 2.392−2.402 245 11110101
15.375−15.437 1.777−1.850 6.406−6.432 4.267−4.284 3.844−3.860 2.883−2.895 2.883−2.895 2.402−2.412 246 11110110
15.437−15.500 1.850−1.922 6.432−6.458 4.284−4.301 3.860−3.875 2.895−2.906 2.895−2.906 2.412−2.422 247 11110111
15.500−15.563 1.922−1.994 6.458−6.484 4.301−4.319 3.875−3.890 2.906−2.918 2.906−2.918 2.422−2.431 248 11111000
15.562−15.625 1.994−2.066 6.484−6.51 4.319−4.336 3.890−3.906 2.918−2.930 2.918−2.930 2.431−2.441 249 11111001
15.625−15.688 2.066−2.139 6.51−6.536 4.336−4.353 3.906−3.921 2.930−2.941 2.930−2.941 2.441−2.451 250 11111010
15.688−15.750 2.139−2.211 6.536−6.563 4.353−4.371 3.921−3.937 2.941−2.953 2.941−2.953 2.451−2.460 251 11111011
15.750−15.812 2.211−2.283 6.563−6.589 4.371−4.388 3.937−3.953 2.953−2.965 2.953−2.965 2.460−2.470 252 11111100
15.812−15.875 2.283−2.355 6.589−6.615 4.388−4.405 3.953−3.969 2.965−2.977 2.965−2.977 2.470−2.480 253 11111101
15.875−15.938 2.355−2.428 6.615−6.641 4.405−4.423 3.969−3.984 2.977−2.988 2.977−2.988 2.480−2.490 254 11111110
>15.938 >2.428 >6.634 >4.423 >3.984 >2.988 >2.988 >2.490 255 11111111
1. * VBAT is not accurate for voltages under 1.5 V (see Figure 14).
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ADM1026
Voltage Measurement Inputs However, when scaling AIN0 to AIN5, it should be noted
The internal structure for all the analog inputs is shown in that these inputs already have an on-chip attenuator, because
Figure 26. Each input circuit consists of an input protection their primary function is to monitor SCSI termination
diode, an attenuator, plus a capacitor to form a first-order voltages. This attenuator loads any external attenuator. The
low-pass filter that gives each voltage measurement input input resistance of the on-chip attenuator can be between
immunity to high frequency noise. The −12 V input also has 100 kW and 200 kW. For this tolerance not to affect the
a resistor connected to the on-chip reference to offset the accuracy, the output resistance of the external attenuator
negative voltage range so that it is always positive and can should be very much lower than this, that is, 1 kW in order
be handled by the ADC. This allows most popular power to add not more than 1% to the total unadjusted error (TUE).
supply voltages to be monitored directly by the ADM1026 Alternatively, the input can be buffered using an op amp.
without requiring any additional resistor scaling.
ǒVfs * 3.0Ǔ
AIN0 – A IN5
21.9k R1 + ǒfor A IN0 through A IN5Ǔ (eq. 2)
(0V – 3V) R2 3.0
109.4k 4.6pF
ǒVfs * 2.5Ǔ
R1 + ǒfor A IN6 through A IN9Ǔ (eq. 3)
AIN6 – A IN9
52.5k R2 2.5
(0V – 2.5V)
4.6pF Negative and bipolar input ranges can be accommodated
by using a positive reference voltage to offset the input
113.5k voltage range so that it is always positive. To monitor a
+12V
negative input voltage, an attenuator can be used as shown
21k 9.3pF
in Figure 28.
VREF
R2
17.5k MUX AIN(0–9)
R1
114.3k VIN
–12V
9.3pF
83.5k
+5V
50k 4.6pF Figure 28. Scaling and Offsetting AIN0 − AIN9
for Negative Inputs
VBAT
49.5k This offsets the negative voltage so that the ADC always
sees a positive voltage. R1 and R2 are chosen so that the
82.7k
4.5pF
ADC input voltage is zero when the negative input voltage
* SEE TEXT is at its maximum (most negative) value, that is:
+VCCP
21.9k
R1 +
R2
Ť Ť
Vf *
s
V OS (eq. 4)
109.4k 18.5pF
This is a simple and low cost solution, but note the
following:
Because the input signal is offset but not inverted, the
Figure 26. Voltage Measurement Inputs
input range is transposed. An increase in the magnitude
Setting Other Input Ranges of the negative voltage (going more negative) causes the
AIN0 to AIN9 can easily be scaled to voltages other than input voltage to fall and give a lower output code from
2.5 V or 3.0 V. If the input voltage range is zero to some the ADC. Conversely, a decrease in the magnitude of the
positive voltage, all that is required is an input attenuator, as negative voltage causes the ADC code to increase. The
shown in Figure 27. maximum negative voltage corresponds to zero output
from the ADC. This means that the upper and lower
limits are transposed.
AIN(0–9)
VIN
R1
For the ADC output to be full scale when the negative
voltage is zero, VOS must be greater than the full−scale
R2
voltage of the ADC, because VOS is attenuated by R1 and
R2. If VOS is equal to or less than the full−scale voltage
of the ADC, the input range is bipolar but not necessarily
Figure 27. Scaling AIN0 − AIN9 symmetrical.
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ADM1026
ǒVfs * 2.5Ǔ
4.5pF
82.7k
R1 + ǒfor A IN6 through A IN9Ǔ (eq. 7)
R3 2.5
Also, note that R2 has no effect as the input voltage at the
device pin is equal to VOS when VIN = positive full scale. Figure 30. Equivalent VBAT Input Protection Circuit
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ADM1026
If the VREF output is not being used, it should be left by clearing Bit 3 of Configuration Register 1 (Address 00h)
unconnected. Do not connect VREF to GND using a to 0. If this bit is 1, then Pins 27 and 28 are AIN8 and AIN9.
capacitor. The internal output buffer on the voltage reference The forward voltage of a diode or diode-connected
is capacitively loaded, which can cause the voltage reference transistor, operated at a constant current, exhibits a negative
to oscillate. This affects temperature readings reported back temperature coefficient of about −2 mV/C. Unfortunately,
by the ADM1026. The recommended interface circuit for the absolute value of Vbe varies from device to device, and
the VREF output is shown in Figure 32. individual calibration is required to null this out, so the
technique is unsuitable for mass production.
+12V
The technique used in the ADM1026 is to measure the
change in Vbe when the device is operated at two different
ADM1026 currents, given by:
24
10k
VREF
NDT3055 DV be + K q T log n (N) (eq. 10)
VDD
I NxI IBIAS
D+
VOUT+
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ADM1026
The results of external temperature measurements are thermocouple voltages are about 3 mV/C of temperature
stored in 8-bit, twos complement format, as illustrated in difference. Unless there are two thermocouples with a
Table 8. big temperature differential between them, thermocouple
voltages should be much less than 200 mV.
Table 8. TEMPERATURE DATA FORMAT
Place a 0.1 mF bypass capacitor close to the ADM1026.
Temperature Digital Output Hex
If the distance to the remote sensor is more than eight
−128C 1000 0000 80 inches, the use of twisted-pair cable is recommended.
−125C 1000 0011 83 This works from about 6 to 12 feet.
−100C 1001 1100 9C For very long distances (up to 100 feet), use shielded
−75C 1011 0101 B5 twisted pair such as Belden #8451 microphone cable.
−50C 1100 1110 CE Connect the twisted pair to D+ and D− and the shield to
−25C 1110 0111 E7 GND close to the ADM1026. Leave the remote end of
−10C 1111 0110 F6 the shield unconnected to avoid ground loops.
0C 0000 0000 00 Because the measurement technique uses switched
10C 0000 1010 0A current sources, excessive cable and/or filter capacitance
25C 0001 1001 19 can affect the measurement. When using long cables, the
50C 0011 0010 32
filter capacitor may be reduced or removed. Cable resistance
can also introduce errors. A 1 W series resistance introduces
75C 0100 1011 4B
about 0.5C error.
100C 0110 0100 64
125C 0111 1101 7D Limit Values
Limit values for analog measurements are stored in the
127C 0111 1111 7F
appropriate limit registers. In the case of voltage
Layout Considerations measurements, high and low limits can be stored so that an
Digital boards can be electrically noisy environments. interrupt request is generated if the measured value goes
Take these precautions to protect the analog inputs from above or below acceptable values. In the case of
noise, particularly when measuring the very small voltages temperature, a hot temperature or high limit can be
from a remote diode sensor. programmed, and a hot temperature hysteresis or low limit
can be programmed, which is usually some degrees lower.
Place the ADM1026 as close as possible to the remote
This can be useful because it allows the system to be shut
sensing diode. Provided that the worst noise sources
down when the hot limit is exceeded, and restarted
such as clock generators, data/address buses, and CRTs
automatically when it has cooled down to a safe
are avoided, this distance can be 4 to 8 inches.
temperature.
Route the D+ and D− tracks close together, in parallel,
with grounded guard tracks on each side. Provide a Analog Monitoring Cycle Time
ground plane under the tracks if possible. The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the
Use wide tracks to minimize inductance and reduce noise
configuration register. INT_Enable (Bit 1) should be set to
pickup. A 10 mil track minimum width and spacing is
1 to enable the INT output. The ADC measures each analog
recommended.
input in turn, starting with Remote Temperature Channel 1
GND 10MIL and ending with local temperature. As each measurement is
10MIL
completed, the result is automatically stored in the
appropriate value register. This round-robin monitoring
D+ 10MIL
cycle continues until it is disabled by writing a 0 to Bit 0 of
10MIL
the configuration register. Because the ADC is typically left
D– 10MIL to free-run in this way, the most recently measured value of
10MIL any input can be read out at any time.
GND 10MIL For applications where the monitoring cycle time is
important, it can easily be calculated.
Figure 34. Arrangement of Signal Tracks The total number of channels measured is:
Try to minimize the number of copper/solder joints, Five Dedicated Supply Voltage Inputs
which can cause thermocouple effects. Where copper/ Ten General-purpose Analog Inputs
solder joints are used, make sure that they are in both 3.3 V MAIN
the D+ and D− paths and are at the same temperature. 3.3 V STBY
Thermocouple effects should not be a major problem Local Temperature
because 1C corresponds to about 240 mV, and Two Remote Temperature
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ADM1026
Pins 28 and 27 are measured both as analog inputs To amplify the 2.5 V range of the analog output up to
AIN8/AIN9 and as remote temperature input D2+/D2−, 12 V, the gain of these circuits needs to be about 4.8.
irrespective of which configuration is selected for these pins. Take care when choosing the op amp to ensure that its
If Pins 28 and 27 are configured as AIN8/AIN9, the input common-mode range and output voltage swing
measurements for these channels are stored in Registers 27h are suitable.
and 29h, and the invalid temperature measurement is
discarded. On the other hand, if Pins 28 and 27 are configured
The op amp may be powered from the +12 V rail alone
or from 12 V. If it is powered from +12 V, the input
as D2+/D2−, the temperature measurement is stored in
Register 29h, and there is no valid result in Register 27h. common-mode range should include ground to
As mentioned previously, the ADC performs a conversion accommodate the minimum output voltage of the DAC,
every 711 ms on the analog and local temperature inputs and and the output voltage should swing below 0.6 V to
every 2.13 ms on the remote temperature inputs. Each input ensure that the transistor can be turned fully off.
is measured 16 times and averaged to reduce noise. If the op amp is powered from −12 V, precautions such
The total monitoring cycle time for voltage and as a clamp diode to ground may be needed to prevent
temperature inputs is therefore nominally: the base-emitter junction of the output transistor being
reverse-biased in the unlikely event that the output of
(18 16 0.711) ) (2 16 2.13) + 273 ms (eq. 11)
the op amp should swing negative for any reason.
The ADC uses the internal 22.5 kHz clock, which has a In all these circuits, the output transistor must have an
tolerance of 6%, so the worst-case monitoring cycle time ICMAX greater than the maximum fan current, and be
is 290 ms. The fan speed measurement uses a completely capable of dissipating power due to the voltage dropped
separate monitoring loop, as described later. across it when the fan is not operating at full speed.
Input Safety If the fan motor produces a large back EMF when
Scaling of the analog inputs is performed on-chip, so switched off, it may be necessary to add clamp diodes
external attenuators are typically not required. However, to protect the output transistors in the event that the
because the power supply voltages appear directly at the output goes from full scale to zero very quickly.
pins, it is advisable to add small external resistors (that is, 12 V
500 W) in series with the supply traces to the chip to prevent 1/4
LM324
damaging the traces or power supplies should an accidental
DAC
short such as a probe connect two power supplies together. Q1
2N2219A
Because the resistors form part of the input attenuators,
they affect the accuracy of the analog measurement if their
value is too high. The worst such accident would be
connecting −12 V to +12 V where there is a total of 24 V
difference. With the series resistors, this would draw a
maximum current of approximately 24 mA. R1
10k
Analog Output
The ADM1026 has a single analog output from an
unsigned 8-bit DAC that produces 0 V to 2.5 V Figure 35. Fan Drive Circuit with Op Amp and
(independent of the reference voltage setting). The input Emitter-follower
data for this DAC is contained in the DAC control register 12 V
(Address 04h). The DAC control register defaults to FFh
R4
during a power-on reset, which produces maximum fan 1/4
LM324 1kW
speed. The analog output may be amplified and buffered DAC Q1
with external circuitry such as an op amp and a transistor to BD136
R3 2SA968
provide fan speed control. During automatic fan speed 1kW
control, described later, the four MSBs of this register set the
minimum fan speed. R2
39kW
Suitable fan drive circuits are shown in Figure 35 through
Figure 39. When using any of these circuits, note the
following: R1
10k
All of these circuits provide an output range from 0 V
to almost +12 V, apart from Figure 35, which loses the
base-emitter voltage drop of Q1 due to the Figure 36. Fan Drive Circuit with Op Amp and PNP
emitter-follower configuration. Transistor
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ADM1026
R1
10k 3.3 V 5.0 V OR 12 V
FAN
10k TYP
Figure 37. Fan Drive Circuit with Op Amp and
P-channel MOSFET PWM
Q1
NDT3055L
12 V
R2 R2
100kW 100kW Figure 40. PWM Fan Drive Circuit Using an
Q3
IRF9620
N-channel MOSFET
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ADM1026
When the temperature measured by any of the sensors SPIN UP FOR 2 SECONDS
exceeds the corresponding TMIN, the fan is spun up for 255
2 seconds with the fan drive set to maximum (full scale from 240
the DAC or 100% PWM duty cycle). The fan speed is then
set to the minimum as previously defined. As the DAC
temperature increases, the fan drive increases until the OUTPUT
T ACTUAL * T MIN
PWM + PWM MIN ) ǒ100 * PWM MINǓ
20
(eq. 13)
TMIN - 45C TMIN TMIN + 205C
or TEMPERATURE
PWM
OUTPUT PULLUP
4.7k
TYP FAN(0–7) FAN SPEED
COUNTER
MIN
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ADM1026
12 V VCC 22.5kHz
CLOCK
PULLUP CONFIGURATION
4.7k REG. 1 BIT 0
TYP FAN(0–7) FAN SPEED
COUNTER 1 2 3 4
FAN0
INPUT
1 2 3 4
* CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x VCC
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ADM1026
Table 9 shows the relationship between fan speed and time initialization or before the fourth tach pulse during
per revolution at 60%, 70%, and 100% of nominal RPM for measurement, the measurement is terminated. This also
fan speeds of 1100, 2200, 4400, and 8800 RPM, and the occurs if an input is configured as GPIO instead of fan. Any
divisor that would be used for each of these fans, based on channels connected in this manner time out after 255 clock
two tach pulses per revolution. pulses.
The worst-case measurement time for a fan−configured
Limit Values
channel occurs when the counter reaches 254 from start to
Fans generally do not over-speed if run from the correct
the second tach pulse and reaches 255 after the second tach
voltage, so the failure condition of interest is under speed
pulse. Taking into account the tolerance of the oscillator
due to electrical or mechanical failure. For this reason, only
frequency, the worst-case measurement time is:
low speed limits are programmed into the limit registers for
the fans. It should be noted that because fan period rather 509 D 0.05 ms (eq. 17)
than speed is being measured, a fan failure interrupt occurs where:
when the measurement exceeds the limit value. 509 is the total number of clock pulses.
D is the divisor: 1, 2, 4, or 8.
Fan Monitoring Cycle Time
0.05 ms is the worst-case oscillator period in ms.
The fan speeds are measured in sequence from 0 to 7. The
monitoring cycle time depends on the fan speed, the number The worst-case fan monitoring cycle time is the sum of the
of tach output pulses per revolution, and the number of fans worst-case measurement time for each fan.
being monitored. Although the fan monitoring cycle and the analog input
If a fan is stopped or running so slowly that the fan speed monitoring cycle are started together, they are not
counter reaches 255 before the second tach pulse after synchronized in any other way.
Chassis Intrusion Input The chassis intrusion input can also be used for other types
The chassis intrusion input is an active high input intended of alarm input. Figure 48 shows a temperature alarm circuit
for detection and signaling of unauthorized tampering with using an AD22105 temperature switch sensor. This
the system. When this input goes high, the event is latched produces a low-going output when the preset temperature is
in Bit 6 of Status Register 4, and an interrupt is generated. exceeded, so the output is inverted by Q1 to make it
The bit remains set until cleared by writing a 1 to CI clear, compatible with the CI input. Q1 can be almost any
Bit 1 of Configuration Register 3 (05h), as long as battery small-signal NPN transistor, or a TTL or CMOS inverter
voltage is connected to the VBAT input. The CI clear bit itself gate may be used if one is available.
is cleared by writing a 0 to it. VCC
The CI input detects chassis intrusion events even when 6 7
R1
10k CI
the ADM1026 is powered off (provided battery voltage is RSET
AD22105
TEMPERATURE
18
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25
ADM1026
INT
INT RE−ASSERTED
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ADM1026
START OF ANALOG OUT-OF-LIMIT LOCAL TEMPEREATURE START OF ANALOG LOCAL TEMPERATURE START OF ANALOG
MONITORING CYCLE MEASUREMENT MEASUREMENT MONITORING CYCLE MEASUREMENT MONITORING CYCLE
INT INT
CLEARED CLEARED GPIO DE−ASSERTED
Status Register 4 also stores inputs from two other Registers 5 and 6, or Bit 7 of Status Register 4 (GPIO16). A
interrupt sources that operate in a different way from the chassis intrusion event sets Bit 6 of Status Register 4.
other status bits. If automatic fan speed control (AFC) is The GPIO and CI status bits, after mask gating, are OR’ed
enabled, Bit 4 of Status Register 4 is set whenever a fan starts together and OR’ed with other interrupt sources to produce
or stops. This bit causes a one-off INT output as shown in the INT output. GPIO and CI interrupts are not latched and
Figure 51. It is cleared during the next monitoring cycle and cannot be cleared by normal interrupt clearing. They can
if INT has been cleared, it does not cause INT to be only be cleared by masking the status bits or by removing the
reasserted. source of the interrupt.
FAN ON
Enabling and Clearing Interrupts
FAN OFF
The INT output is enabled when Bit 1 of Configuration
INT Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is
low. INT may be cleared if:
INT CLEARED BY STATUS REGULAR 1 READ, BIT 2 Status Register 1 is read. Ideally, if polling the status
OF CONFIGURATION REGULAR 1 SET, OR ARA
registers trying to identify interrupt sources, Status
Figure 51. Assertion of INT Due to AFC Event Register 1 should be polled last, because a read of Status
In a similar way, a change of state at the THERM output Register 1 clears all the other interrupt status registers.
(described in more detail later), sets Bit 3 of Status The ADM1026 receives the alert response address
Register 4 and causes a one-off INT output. A change of (ARA) (0001 100) over the SMBus.
state at the THERM output also causes Bit 0 of Status Bit 2 of Configuration Register 1 is set.
Register 1, Bit 1 of Status Register 1, or Bit 0 of Status
Register 4 to be set, depending on which temperature Bidirectional THERM Pin
channel caused the THERM event. This bit is reset during The ADM1026 has a second interrupt pin (GPIO16/
the next monitoring cycle, provided the temperature channel THERM Pin 42) that responds only to critical thermal
is within the normal high and low limits. events. The THERM pin goes low whenever a THERM limit
is exceeded. This function is useful for CPU throttling or
Fan Inputs system shutdown. In addition, whenever THERM is
Fan inputs generate interrupts in a similar way to activated, the PWM and DAC outputs go full scale to
analog/temperature inputs, but as the analog/temperature provide fail-safe system cooling. This output is enabled by
inputs and fan inputs have different monitoring cycles, they setting Bit 4 of Configuration Register 1 (Register 00h).
have separate interrupt circuits. As the speed of each fan is Whenever a THERM limit is exceeded, Bit 3 of Status
measured, the output of the fan speed counter is stored in a Register 4 (Reg 23h) is set, even if the THERM function is
value register. The result is compared to the fan speed limit disabled (Bit 4 of Configuration Register 1 = 0). In this case,
and is used to set or clear a bit in Status Register 3. In this the THERM status bit is set, but the PWM and DAC outputs
case, the fan is monitored only for underspeed (fan counter are not forced to full scale.
> fan speed limit). Mask Register 3 is used to mask fan Three thermal limit registers are provided for the three
interrupts. After mask gating, the fan status bits are OR’ed temperature sensors at Addresses 0Dh to 0Fh. These registers
together and used to set a latch, whose output is OR’ed with are dedicated to the THERM function and none of the other
other interrupt sources to produce the INT output. limit registers have any effect on the THERM output.
Like the analog/temp interrupt, an INT output caused by an If any of the temperature measurements exceed the
out−of−limit fan speed measurement, once cleared, is not corresponding limit, THERM is asserted (low) and the DAC
reasserted until the end of the next monitoring cycle, although and PWM outputs go to maximum to drive any cooling fans
other interrupt sources may cause INT to be asserted. to full speed.
GPIO and CI Pins. When GPIO pins are configured as To avoid cooling fans cycling on and off continually when
inputs, asserting a GPIO input (high or low, depending on the temperature is close to the limit, a fixed hysteresis of 5C
polarity) sets the corresponding GPIO status bit in Status
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ADM1026
is provided. THERM is only deasserted when the measured if INT is subsequently cleared by one of the methods
temperature of all three sensors is 5C below the limit. previously described, it is not reasserted, even if THERM
Whenever the THERM output changes, INT is asserted, remains asserted. THERM causes INT to be reasserted only
as shown in Figure 53. However, this is edge-triggered, so when it changes state.
EXT1 TEMP
0 MASK GATING
EXT 2 TEMP
1
3.3V STBY
2
REGISTER
3.3V MAIN STATUS
STATUS
3
+5V BIT
1
4
VCCP
5
+12V
6
–12V
7 MASK
BIT
MASK DATA FROM
MASK
SMBus (SAME BIT
REGISTER
FROM ANALOG/TEMP NAMES AND ORDER
1
VALUE AND LIMIT AS STATUS BITS)
REGISTERS
AIN0
0 MASK GATING
HIGH LIMIT AIN1
DEMULTIPLEXER
1
COMPARATORS
AIN2
1 = OUT
LOW LIMIT
2
HIGH AND
AIN3 STATUS
REGISTER
OF LIMIT
DATA
STATUS
3 BIT
VALUE AIN4
2
4
AIN5
5 IN OUT
AIN6
LOW LIMIT 6
AIN7 LATCH
7 MASK
BIT
MASK DATA FROM RESET
SMBus (SAME BIT MASK
NAMES AND ORDER REGISTER
AS STATUS BITS) 2
INT TEMP
VBAT 0 MASK GATING
AIN8 1
2
THERM
REGISTER
STATUS
STATUS
3 BIT
AFC
4
4
RESERVED
5
CI
6
GPIO16
7 MASK
BIT
MASK DATA FROM
MASK CI
SMBus (SAME BIT
REGISTER
NAMES AND ORDER GPIO16
4
AS STATUS BITS)
FAN0
0 MASK GATING
FAN1
VALUE
DEMULTIPLEXER
1
COMPARATOR
1 = OUT FAN2
HIGH LIMIT
2
REGISTER
LIMIT REGISTERS 4
FAN5
5 IN OUT INT
FAN6
HIGH LIMIT 6
FAN7 LATCH
7 MASK
BIT
MASK DATA FROM RESET
MASK
SMBus (SAME BIT INT ENABLE
REGISTER
NAMES AND ORDER
AS STATUS BITS) 3
MASK GATING
GPIO8 TO GPIO15 STATUS REGISTER 6 STATUS
BIT
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ADM1026
Note that the THERM pin is bidirectional, so THERM NAND Tree Tests
may be pulled low externally as an input. This causes the A NAND tree is provided in the ADM1026 for automated
PWM and DAC outputs to go to full scale until THERM is test equipment (ATE) board-level connectivity testing. This
returned high again. To disable THERM as an input, set Bit 0 allows the functionality of all digital inputs to be tested in a
of Configuration Register 3 (Reg. 07h). This configures simple manner and any pins that are nonfunctional or
Pin 42 as GPIO16 and prevents a low on Pin 42 from driving shorted together to be identified. The structure of the NAND
the fans at full speed. tree is shown in Figure 55. The device is placed into NAND
TEMPERATURE tree test mode by powering up with Pin 25 held high. This
THERM LIMIT pin is sampled automatically after powerup, and if it is
THERM LIMIT - 55C connected high, then the NAND test mode is invoked.
GPIO8
THERM GPIO9
FAN0
GPIO10
INT FAN1
GPIO11
FAN2
3.3VMAIN ~1.0 V
RESETSTBY
RESETMAIN
180ms 180ms
POWER−ON RESET
Figure 54. Operation of Offset Outputs
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ADM1026
Notes: INT
GPIO16 FAN0
GPIO15 GPIO8
GPIO14 GPIO9
GPIO13 GPIO10
GPIO12
GPIO11
GPIO11
GPIO12
GPIO10
GPIO13
GPIO9
GPIO14
GPIO8
GPIO15
FAN0
GPIO16
FAN1
NTESTOUT
FAN2
FAN3 Figure 57. NAND Tree Test Taking Inputs Low in Turn
FAN4
FAN5
GPIO16
FAN6
GPIO15
FAN7
GPIO14
SCL
GPIO13
SDA
GPIO12
CI
GPIO11
INT
GPIO10
GPIO9
NTESTOUT
GPIO8
FAN0
Figure 56. NAND Tree Test Taking Inputs High in Turn FAN1
NTESTOUT
In the event of an input being nonfunctional (stuck high or
low) or two inputs shorted together, the output pattern is Figure 58. NAND Tree Test with GPIO11 Stuck Low
different. Some examples are given in Figure 58 through
Figure 60. Figure 59 shows the effect of one input being stuck high.
Figure 58 shows the effect of one input being stuck low. Taking GPIO12 high should take the output high. However,
The output pattern is normal until the stuck input is reached. the next input up the tree, GPIO11, is already high, so the
Because that input is permanently low, neither it nor any output immediately goes low again, causing a missing pulse
inputs further up the tree can have any effect on the output. in the output pattern.
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ADM1026
GPIO16
Setting the fan divisors using the fan divisor registers
GPIO15
(Addresses 02h and 03h).
GPIO14
Configuring the GPIO pins for input/output polarity, using
GPIO13
GPIO Configuration Registers 1 to 4 (Addresses 08h to
GPIO12 0Bh) and Bits 6 and 7 of Configuration Register 3.
GPIO11
Setting mask bits in Mask Registers 1 to 6 (Addresses
GPIO10 18h to 1Dh) for any inputs that are to be masked out.
GPIO9
Setting up Configuration Registers 1 and 3, as
GPIO8 described in Table 10 and Table 11.
FAN0
FAN1
Table 10. CONFIGURATION REGISTER 1
NTESTOUT Bit Description
Figure 59. NAND Tree Test with One Input Stuck High 0 Controls the monitoring loop of the ADM1026. Setting
Bit 0 low stops the monitoring loop and puts the
ADM1026 into low power mode and reduces power
A similar effect occurs if two adjacent inputs are shorted consumption. Serial bus communication is still
together. The example in Figure 60 assumes that the current possible with any register in the ADM1026 while in
sink capability of the circuit driving the inputs is low power mode. Setting bit 0 high starts the
monitoring loop.
considerably higher than the source capability, so the inputs
are low if either is low, but high only if both are high. 1 Enables or disables the INT interrupt output. Setting
Bit 1 high enables the INT output, setting Bit 1 low
When GPIO12 goes high the output should go high. But disables the output.
because GPIO12 and GPIO11 are shorted, they both go high
2 Used to clear the INT interrupt output when set high.
together, causing a missing pulse in the output pattern. GPIO pins and interrupt status register contents are
not affected.
GPIO16
3 Configures Pins 27 and 28 as the second external
GPIO15
temperature channel when 0, and as AIN8 and AIN9
GPIO14 when set to 1.
GPIO13 4 Enables the THERM output when set to 1.
GPIO12 5 Enables automatic fan speed control on the DAC
GPIO11
output when set to 1.
FAN0
Table 11. CONFIGURATION REGISTER 3
FAN1
Bit Description
NTESTOUT
0 Configures Pin 42 as GPIO when set to 1 or as
Figure 60. NAND Tree Test with Two Inputs Shorted THERM when cleared to 0.
1 Clears the CI latch when set to 1. Thereafter, a 0
Using the ADM1026 must be written to allow subsequent CI detection.
When power is first applied, the ADM1026 performs a
2 Selects VREF as 2.5 V when set to 1 or as 1.82 V
power−on reset on all its registers (not EEPROM), which when cleared to 0.
sets them to default conditions as shown in Table 13. In 3–5 Unused.
particular, note that all GPIO pins are configured as inputs
6, 7 Set up GPIO16 for direction and polarity.
to avoid possible conflicts with circuits trying to drive these
pins. Starting Conversion
The ADM1026 can also be initialized at any time by The monitoring function (analog inputs, temperature, and
writing a 1 to Bit 7 of Configuration Register 1, which sets fan speeds) in the ADM1026 is started by writing to
some registers to their default power−on conditions. This bit Configuration Register 1 and setting Start (Bit 0) high. The
should be cleared by writing a 0 to it. INT_Enable (Bit 1) should be set to 1, and INT Clear (Bit 2)
After power−on, the ADM1026 must be configured to the set to 0 to enable interrupts. The THERM enable bit (Bit 4)
user’s specific requirements. This consists of: should be set to 1 to enable temperature interrupts at the
Writing values to the limit registers. THERM pin. Apart from initially starting together, the
Configuring Pins 3 to 6, and 9 to 12 as fan inputs or analog measurements and fan speed measurements proceed
GPIO, using Configuration Register 2 (Address 01h). independently, and are not synchronized in any way.
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Reduced Power Mode Note that the limit registers (0Dh to 12h, 40h to 6Dh) are
The ADM1026 can be placed in a low power mode by not reset by the software reset function. This can be useful
setting Bit 0 of the configuration register to 0. This disables if one needs to reset the part but does not want to reprogram
the internal ADC. all parameters again. Note that a power-on reset initializes
all registers on the ADM1026, including the limit registers.
Software Reset Function
As previously mentioned, the ADM1026 can be reset in Application Schematic
software by setting Bit 7 of Configuration Register 1 Figure 61 shows how the ADM1026 could be used in an
(Reg. 00h) to 1. Configuration Register 1, 00h, should then application that requires system management of a PC or
be manually cleared. Note that the software reset differs server. Several GPIOs are used to read the VID codes of the
from a power-on reset in that only some of the ADM1026 CPU. Up to two CPU temperature measurements can be read
registers are reinitialized to their power-on default values. back. All power supply voltages are monitored in the
The registers that are initialized to their default values by the system. Up to eight fan speeds can be measured, irrespective
software reset are of whether they are controlled by the ADM1026 or
Configuration Registers (Registers 01h to 0Bh) hardwired to a system supply. The VREF output includes the
Mask Registers 1 to 6, internal temperature offset, and recommended filtering circuitry.
Status Registers 4, 5, and 6 (Registers 18h to 25h)
All value registers (Registers 1Fh, 20h to 3Fh)
External 1 and External 2 Offset Registers (6Eh, 6Fh)
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CPU1_VID4 SYS_THERM
CPU1_VID3
CPU1_VID2
CPU1_VID1
CPU1_VID0
+12V +12V
X1 X2
1 1
41 A
40 A
39 A
38 A
37 A
IN0
IN1
IN2
IN3
IN4
42 THERM
48 GPIO10
47 GPIO11
46 GPIO12
45 GPIO13
44 GPIO14
43 GPIO15
1 GPIO9 AIN5 36
2 2
2 GPIO8 AIN6 35
3 FAN0/GPIO0 AIN7 34
3 3 CPU2_VCCP
4 FAN1/GPIO1 +VCCP 33
FAN FAN +12 VIN 32 CPU1_VCCP
5 FAN2/GPIO2 +12 VIN
–12V IN 31
6 FAN3/GPIO3 –12 VIN
+5 VIN 30
7 3.3VMAIN U1 +5 VIN
+VBAT 29
ADM1026_SKT
+12V +12V 8 DGND
X4 D2+/A IN8 28
X3 9 FAN4/GPIO4 CPU2_THERMDA
1 1
D2–/A IN9 27
10 FAN5/GPIO5 CPU2_THERMDC
D1+ 26 +
CPU1_THERMDA
33
2 2 11 FAN6/GPIO6 B1
D1– 25
FAN7/GPIO7 CPU1_THERMDC
12
3 3
ADM1026
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FAN FAN
4
SCL 13
SDA 14
ADD 15
CI 16
INT 17
PWM 18
RESETSTBY 19
RESETMAIN 20
AGND 21
3.3V STBY 22
DAC 23
VREF 24
3.3V STDY
S1
VREF_OUT
R6
1
470k
SCLOCK
3 SDATA
FAN R5 R4
10k 10k
POWER_GOOD
Q1 SMB_ALERT
CPURESET
ADM1026
Registers
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23 Status Register 4 00h Interrupt status register for local temp, VBAT, AIN8, THERM, AFC, CI, and GPIO16.
24 Status Register 5 00h Interrupt status register for GPIO0 to GPIO7.
25 Status Register 6 00h Interrupt status register for GPIO8 to GPIO15.
26 VBAT Value 00h Measured value of VBAT.
27 AIN8 Value 00h Measured value of AIN8.
28 TDM1 Value 00h Measured value of remote temperature channel 1 (D1).
29 TDM2/AIN9 Value 00h Measured value of remote temperature channel 2 (D2) or AIN9.
2A 3.3 V STBY Value 00h Measured value of 3.3 V STBY.
2B 3.3 V MAIN Value 00h Measured value of 3.3 V MAIN.
2C +5.0 V Value 00h Measured value of +5.0 V supply.
2D VCCP Value 00h Measured value of processor core voltage.
2E +12 V Value 00h Measured value of +12 V supply.
2F −12 V Value 00h Measured value of -12 V supply.
30 AIN0 Value 00h Measured value of AIN0.
31 AIN1 Value 00h Measured value of AIN1
32 AIN2 Value 00h Measured value of AIN2.
33 AIN3 Value 00h Measured value of AIN3.
34 AIN4 Value 00h Measured value of AIN4.
35 AIN5 Value 00h Measured value of AIN5.
36 AIN6 Value 00h Measured value of AIN6.
37 AIN7 Value 00h Measured value of AIN7.
38 FAN0 Value 00h Measured speed of Fan 0.
39 FAN1 Value 00h Measured speed of Fan 1.
3A FAN2 Value 00h Measured speed of Fan 2.
3B FAN3 Value 00h Measured speed of Fan 3.
3C FAN4 Value 00h Measured speed of Fan 4.
3D FAN5 Value 00h Measured speed of Fan 5.
3E FAN6 Value 00h Measured speed of Fan 6.
3F FAN7 Value 00h Measured speed of Fan 7.
40 TDM1 High Limit 64h (100C) High limit for Remote Temperature Channel 1 (D1) measurement.
41 TDM2/AIN9 High Limit 64h (100C) High limit for Remote Temperature Channel 2 (D2) or AIN9 measurement.
42 3.3 V STBY High Limit FFh High limit for 3.3 V STBY measurement.
43 3.3 V MAIN High Limit FFh High limit for 3.3 V MAIN measurement.
44 +5.0 V High Limit FFh High limit for +5.0 V supply measurement.
45 VCCP High Limit FFh High limit for processor core voltage measurement.
46 +12 V High Limit FFh High limit for +12 V supply measurement.
47 −12 V High Limit FFh High limit for -12 V supply measurement.
48 TDM1 Low Limit 80h Low limit for Remote Temperature Channel 1 (D1) measurement.
49 TDM2/AIN9 Low Limit 80h Low limit for Remote Temperature Channel 2 (D2) or AIN9 measurement.
4A 3.3 V STBY Low Limit 00h Low limit for 3.3 V STBY measurement.
4B 3.3 V MAIN Low Limit 00h Low limit for 3.3 V MAIN measurement.
4C +5.0 V Low Limit 00h Low limit for +5.0 V supply.
4D VCCP Low Limit 00h Low limit for processor core voltage measurement.
4E +12 V Low Limit 00h Low limit for +12 V supply measurement.
4F −12 V Low Limit 00h Low limit for -12 V supply measurement.
50 AIN0 High Limit FFh High limit for AIN0 measurement.
51 AIN1 High Limit FFh High limit for AIN1 measurement.
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Table 16. REGISTER 02H, FANS 0 TO 3 FAN DIVISOR REGISTER (POWER-ON DEFAULT 55H)
Bit Name R/W Description
1–0 Fan 0 Divisor R/W Sets the oscillator prescaler division ratio for Fan 0 speed measurement. The
division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach
pulses per revolution) are as follows:
Divide Oscillator
Code Fan Speed (RPM)
By: Frequency (kHz)
00 1 22.5 8800, nominal, for count of 153
01 2 11.25 4400, nominal, for count of 153
10 4 5.62 2200, nominal, for count of 153
11 8 2.81 1100, nominal, for count of 153
3–2 Fan 1 Divisor R/W Same as Fan 0
5–4 Fan 2 Divisor R/W Same as Fan 0
7–6 Fan 3 Divisor R/W Same as Fan 0
Table 17. REGISTER 03H, FANS 4 TO 7 FAN DIVISOR REGISTER (POWER-ON DEFAULT 55H)
Bit Name R/W Description
1–0 Fan 4 Divisor R/W Sets the oscillator prescaler division ratio for Fan 4 speed measurement. The
division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach
pulses per revolution) are as follows:
Oscillator
Code Divide By: Fan Speed (RPM)
Frequency (kHz)
00 1 22.5 8800, nominal, for count of 153
01 2 11.25 4400, nominal, for count of 153
10 4 5.62 2200, nominal, for count of 153
11 8 2.81 1100, nominal, for count of 153
3–2 Fan 5 Divisor R/W Same as Fan 4
5–4 Fan 6 Divisor R/W Same as Fan 4
7–6 Fan 7 Divisor R/W Same as Fan 4
Table 18. REGISTER 04H, DAC CONFIGURATION REGISTER (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 DAC Control R/W This register contains the value to which the fan speed DAC is programmed in
normal mode, or the 4 MSBs contain the minimum fan speed in auto fan speed
control mode.
Table 19. REGISTER 05H, PWM CONTROL REGISTER (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–4 PWM Control R/W This register contains the value to which the PWM fan speed is programmed in
normal mode, or the 4 MSBs contain the minimum fan speed in auto fan speed
control mode.
0000 = 0% Duty Cycle
0001 = 7% Duty Cycle
0101 = 33% Duty Cycle
0110 = 40% Duty Cycle
0111 = 47% Duty Cycle
1110 = 93% Duty Cycle
1111 = 100% Duty Cycle
3–0 Unused R Undefined
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Table 22. REGISTER 08H, GPIO CONFIGURATION REGISTER 1 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO0 Direction R/W When this bit is 0, GPIO0 is configured as an input; otherwise, it is an output.
1 GPIO0 Polarity R/W When this bit is 0, GPIO0 is active low; otherwise it is active high.
2 GPIO1 Direction R/W When this bit is 0, GPIO1 is configured as an input; otherwise, it is an output.
3 GPIO1 Polarity R/W When this bit is 0, GPIO1 is active low; otherwise it is active high.
4 GPIO2 Direction R/W When this bit is 0, GPIO2 is configured as an input; otherwise, it is an output.
5 GPIO2 Polarity R/W When this bit is 0, GPIO2 is active low; otherwise, it is active high.
6 GPIO3 Direction R/W When this bit is 0, GPIO3 is configured as an input; otherwise, it is an output.
7 GPIO3 Polarity R/W When this bit is 0, GPIO3 is active low; otherwise, it is active high.
Table 23. REGISTER 09H, GPIO CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO4 Direction R/W When this bit is 0, GPIO4 is configured as an input; otherwise, it is an output.
1 GPIO4 Polarity R/W When this bit is 0, GPIO4 is active low; otherwise, it is active high.
2 GPIO5 Direction R/W When this bit is 0, GPIO5 is configured as an input; otherwise, it is an output.
3 GPIO5 Polarity R/W When this bit is 0, GPIO5 is active low; otherwise, it is active high.
4 GPIO6 Direction R/W When this bit is 0, GPIO6 is configured as an input; otherwise, it is an output.
5 GPIO6 Polarity R/W When this bit is 0, GPIO6 is active low; otherwise, it is active high.
6 GPIO7 Direction R/W When this bit is 0, GPIO7 is configured as an input; otherwise, it is an output.
7 GPIO7 Polarity R/W When this bit is 0, GPIO7 is active low; otherwise, it is active high.
Table 24. REGISTER 0AH, GPIO CONFIGURATION REGISTER 3 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO8 Direction R/W When this bit is 0, GPIO8 is configured as an input; otherwise, it is an output.
1 GPIO8 Polarity R/W When this bit is 0, GPIO8 is active low; otherwise, it is active high.
2 GPIO9 Direction R/W When this bit is 0, GPIO9 is configured as an input; otherwise, it is an output.
3 GPIO9 Polarity R/W When this bit is 0, GPIO9 is active low; otherwise, it is active high.
4 GPIO10 Direction R/W When this bit is 0, GPIO10 is configured as an input; otherwise, it is an output.
5 GPIO10 Polarity R/W When this bit is 0, GPIO10 is active low; otherwise, it is active high.
6 GPIO11 Direction R/W When this bit is 0, GPIO11 is configured as an input; otherwise, it is an output.
7 GPIO11 Polarity R/W When this bit is 0, GPIO11 is active low; otherwise, it is active high.
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Table 25. REGISTER 0BH, GPIO CONFIGURATION REGISTER 4 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO12 Direction R/W When this bit is 0, GPIO12 is configured as an input; otherwise, it is an output.
1 GPIO12 Polarity R/W When this bit is 0, GPIO12 is active low; otherwise, it is active high.
2 GPIO13 Direction R/W When this bit is 0, GPIO13 is configured as an input; otherwise, it is an output.
3 GPIO13 Polarity R/W When this bit is 0, GPIO13 is active low; otherwise, it is active high.
4 GPIO14 Direction R/W When this bit is 0, GPIO14 is configured as an input; otherwise, it is an output.
5 GPIO14 Polarity R/W When this bit is 0, GPIO14 is active low; otherwise, it is active high.
6 GPIO15 Direction R/W When this bit is 0, GPIO15 is configured as an input; otherwise, it is an output.
7 GPIO15 Polarity R/W When this bit is 0, GPIO15 is active low; otherwise, it is active high.
Table 26. REGISTER 0CH, EEPROM CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 Factory Use R For factory use only. Do not write to this register.
Table 27. REGISTER 0DH, INTERNAL TEMPERATURE THERM LIMIT (POWER-ON DEFAULT, 37H 555C)
Bit Name R/W Description
7–0 Int Temp THERM Limit R/W This register contains the THERM limit for the internal temperature channel.
Exceeding this limit causes the THERM output pin to be asserted.
Table 28. REGISTER 0EH, TDM1 THERM LIMIT (POWER-ON DEFAULT, 50H 805C)
Bit Name R/W Description
7–0 TDM1 THERM Limit R/W This register contains the THERM limit for the TDM1 temperature channel.
Exceeding this limit causes the THERM output pin to be asserted.
Table 29. REGISTER 0FH, TDM2 THERM LIMIT (POWER-ON DEFAULT, 50H 805C)
Bit Name R/W Description
7–0 TDM2 THERM Limit R/W This register contains the THERM limit for the TDM2 temperature channel.
Exceeding this limit causes the THERM output pin to be asserted.
Table 30. REGISTER 10H, INTERNAL TEMPERATURE TMIN (POWER-ON DEFAULT, 28H 405C)
Bit Name R/W Description
7–0 Internal Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the
internal temperature channel.
Table 31. REGISTER 11H, TDM1 TEMPERATURE TMIN (POWER-ON DEFAULT, 40H 645C)
Bit Name R/W Description
7–0 TDM1 Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the
TDM1 temperature channel.
Table 32. REGISTER 12H, TDM2 TEMPERATURE TMIN (POWER-ON DEFAULT, 40H 645C)
Bit Name R/W Description
7–0 TDM2 Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the
TDM2 temperature channel.
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Table 34. REGISTER 14H, MANUFACTURER’S TEST REGISTER 1 (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Manufacturer’s Test 1 R/W This register is used by the manufacturer for test purposes. It should not be read
from or written to in normal operation.
Table 35. REGISTER 15H, MANUFACTURER’S TEST REGISTER 2 (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Manufacturer’s Test 2 R/W This register is used by the manufacturer for test purposes. It should not be read
from or written to in normal operation.
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Table 44. REGISTER 1EH, INT TEMP OFFSET (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Int Temp Offset R/W This register contains the offset value for the internal temperature channel, a twos
complement result before it is stored or compared to limits. In this way, a sort of
one-point calibration can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel if the thermal
characteristics change for any reason (for instance from one chassis to another), if
the measurement point is moved, if a plug-in card is inserted or removed, and so on.
Table 45. REGISTER 1FH, INT TEMP MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Int Temp Value R This register contains the measured value of the internal temperature channel.
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0 GPIO0 Status = 0 R When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 1.)
R/W When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 1.)
1 GPIO1 Status = 0 R When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
R/W Configuration Register 1.)
When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 1.)
2 GPIO2 Status = 0 R When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 1.)
R/W When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 1.)
3 GPIO3 Status = 0 R When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 1.)
R/W When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 1.)
4 GPIO4 Status = 0 R When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 2.)
R/W When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 2.)
5 GPIO5 Status = 0 R When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 2.)
R/W When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 2.)
6 GPIO6 Status = 0 R When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 2.)
R/W When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 2.)
7 GPIO7 Status = 0 R When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 2.)
R/W When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 2.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
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ADM1026
0 GPIO8 Status = 0 R When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 3.)
R/W When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 3.)
1 GPIO9 Status = 0 R When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 3.)
R/W When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 3.)
2 GPIO10 Status = 0 R When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 3.)
R/W When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 3.)
3 GPIO11 Status = 0 R When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 3.)
R/W When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 3.)
4 GPIO12 Status = 0 R When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 4.)
R/W When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 4.)
5 GPIO13 Status = 0 R When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 4.)
R/W When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 4.)
6 GPIO14 Status = 0 R When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 4.)
R/W When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 4.)
7 GPIO15 Status = 0 R When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 4.)
R/W When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 4.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
Table 52. REGISTER 26H, VBAT MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 VBAT Value R This register contains the measured value of the VBAT analog input channel.
Table 53. REGISTER 27H, AIN8 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN8 Value R This register contains the measured value of the AIN8 analog input channel.
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Table 54. REGISTER 28H, EXT1 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Ext1 Value R This register contains the measured value of the Ext1 Temp channel.
Table 55. REGISTER 29H, EXT2/AIN9 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Ext2 Temp/ R This register contains the measured value of the Ext2 Temp/AIN9 channel depending
AIN9 Low Limit on which bit is configured.
Table 56. REGISTER 2AH, 3.3 V STBY MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 3.3 V STBY Value R This register contains the measured value of the 3.3 V STBY voltage.
Table 57. REGISTER 2BH, 3.3 V MAIN MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 3.3 V MAIN Value R This register contains the measured value of the 3.3 V MAIN voltage.
Table 58. REGISTER 2CH, +5.0 V MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 +5.0 V Value R This register contains the measured value of the +5.0 V analog input channel.
Table 59. REGISTER 2DH, VCCP MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 VCCP Value R This register contains the measured value of the VCCP analog input channel.
Table 60. REGISTER 2EH, +12 V MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 +12 V Value R This register contains the measured value of the +12 V analog input channel.
Table 61. REGISTER 2FH, −12 V MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 –12 V Value R This register contains the measured value of the -12 V analog input channel.
Table 62. REGISTER 30H, AIN0 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN0 Value R This register contains the measured value of the AIN0 analog input channel.
Table 63. REGISTER 31H, AIN1 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN1 Value R This register contains the measured value of the AIN1 analog input channel.
Table 64. REGISTER 32H, AIN2 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN2 Value R This register contains the measured value of the AIN2 analog input channel.
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Table 65. REGISTER 33H, AIN3 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN3 Value R This register contains the measured value of the AIN3 analog input channel.
Table 66. REGISTER 34H, AIN4 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN4 Value R This register contains the measured value of the AIN4 analog input channel.
Table 67. REGISTER 35H, AIN5 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN5 Value R This register contains the measured value of the AIN5 analog input channel.
Table 68. REGISTER 36H, AIN6 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN6 Value R This register contains the measured value of the AIN6 analog input channel.
Table 69. REGISTER 37H, AIN7 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN7 Value R This register contains the measured value of the AIN7 analog input channel.
Table 70. REGISTER 38H, FAN0 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN0 Value R This register contains the measured value of the FAN0 tach input channel.
Table 71. REGISTER 39H, FAN1 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN1 Value R This register contains the measured value of the FAN1 tach input channel.
Table 72. REGISTER 3AH, FAN2 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN2 Value R This register contains the measured value of the FAN2 tach input channel.
Table 73. REGISTER 3BH, FAN3 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN3 Value R This register contains the measured value of the FAN3 tach input channel.
Table 74. REGISTER 3CH, FAN4 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN4 Value R This register contains the measured value of the FAN4 tach input channel.
Table 75. REGISTER 3DH, FAN5 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN5 Value R This register contains the measured value of the FAN5 tach input channel.
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Table 76. REGISTER 3EH, FAN6 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN6 Value R This register contains the measured value of the FAN6 tach input channel.
Table 77. REGISTER 3FH, FAN7 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN7 Value R This register contains the measured value of the FAN7 tach input channel.
Table 78. REGISTER 40H, EXT1 HIGH LIMIT (POWER-ON DEFAULT 64H/1005C)
Bit Name R/W Description
7–0 Ext1 High Limit R/W This register contains the high limit of the Ext1 Temp channel.
Table 79. REGISTER 41H, EXT2/AIN9 HIGH LIMIT (POWER-ON DEFAULT 64H/1005C)
Bit Name R/W Description
7–0 Ext2 Temp/ R/W This register contains the high limit of the Ext2 Temp/AIN9 channel depending on
AIN9 High Limit which one is configured.
Table 80. REGISTER 42H, 3.3 V STBY HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 3.3 V STBY High Limit R/W This register contains the high limit of the 3.3 V STBY analog input channel.
Table 81. REGISTER 43H, 3.3 V MAIN HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 3.3 V MAIN High Limit R/W This register contains the high limit of the 3.3 V MAIN analog input channel.
Table 82. REGISTER 44H, +5.0 V HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 +5.0 V High Limit R/W This register contains the high limit of the +5.0 V analog input channel.
Table 83. REGISTER 45H, VCCP HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 VCCP High Limit R/W This register contains the high limit of the VCCP analog input channel.
Table 84. REGISTER 46H, +12 V HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 +12 V High Limit R/W This register contains the high limit of the +12 V analog input channel.
Table 85. REGISTER 47H, −12 V HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 −12 V High Limit R/W This register contains the high limit of the -12 V analog input channel.
Table 86. REGISTER 48H, EXT1 LOW LIMIT (POWER-ON DEFAULT 80H)
Bit Name R/W Description
7–0 Ext1 Low Limit R/W This register contains the low limit of the Ext1 Temp channel.
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Table 87. REGISTER 49H, EXT/AIN9 LOW LIMIT (POWER-ON DEFAULT 80H)
Bit Name R/W Description
7–0 Ext2 Temp /AIN9 Low R/W This register contains the low limit of the Ext2 Temp/AIN9 channel depending on
Limit which bit is configured.
Table 88. REGISTER 4AH, 3.3 V STBY LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 3.3 V STBY Low Limit R/W This register contains the low limit of the 3.3 V STBY analog input channel.
Table 89. REGISTER 4BH, 3.3 V MAIN LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 3.3 V MAIN Low Limit R/W This register contains the low limit of the 3.3 V MAIN analog input channel.
Table 90. REGISTER 4CH, +5.0 V LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 +5.0 V Low Limit R/W This register contains the low limit of the +5.0 V analog input channel.
Table 91. REGISTER 4DH, VCCP LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 VCCP Low Limit R/W This register contains the low limit of the VCCP analog input channel.
Table 92. REGISTER 4EH, +12 V LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 +12 V Low Limit R/W This register contains the low limit of the +12 V analog input channel.
Table 93. REGISTER 4FH, −12 V LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 −12 V Low Limit R/W This register contains the low limit of the -12 V analog input channel.
Table 94. REGISTER 50H, AIN0 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN0 High Limit R/W This register contains the high limit of the AIN0 analog input channel.
Table 95. REGISTER 51H, AIN1 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN1 High Limit R/W This register contains the high limit of the AIN1 analog input channel.
Table 96. REGISTER 52H, AIN2 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN2 High Limit R/W This register contains the high limit of the AIN2 analog input channel.
Table 97. REGISTER 53H, AIN3 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN3 High Limit R/W This register contains the high limit of the AIN3 analog input channel.
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Table 98. REGISTER 54H, AIN4 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN4 High Limit R/W This register contains the high limit of the AIN4 analog input channel.
Table 99. REGISTER 55H, AIN5 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN5 High Limit R/W This register contains the high limit of the AIN5 analog input channel.
Table 100. REGISTER 56H, AIN6 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN6 High Limit R/W This register contains the high limit of the AIN6 analog input channel.
Table 101. REGISTER 57H, AIN7 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN7 High Limit R/W This register contains the high limit of the AIN7 analog input channel.
Table 102. REGISTER 58H, AIN0 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN0 Low Limit R/W This register contains the low limit of the AIN0 analog input channel.
Table 103. REGISTER 59H, AIN1 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN1 Low Limit R/W This register contains the low limit of the AIN1 analog input channel.
Table 104. REGISTER 5AH, AIN2 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN2 Low Limit R/W This register contains the low limit of the AIN2 analog input channel.
Table 105. REGISTER 5BH, AIN3 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN3 Low Limit R/W This register contains the low limit of the AIN3 analog input channel.
Table 106. REGISTER 5CH, AIN4 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN4 Low Limit R/W This register contains the low limit of the AIN4 analog input channel.
Table 107. REGISTER 5DH, AIN5 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN5 Low Limit R/W This register contains the low limit of the AIN5 analog input channel.
Table 108. REGISTER 5EH, AIN6 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN6 Low Limit R/W This register contains the low limit of the AIN6 analog input channel.
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Table 109. REGISTER 5FH, AIN7 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN7 Low Limit R/W This register contains the low limit of the AIN7 analog input channel.
Table 110. REGISTER 60H, FAN0 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN0 High Limit R/W This register contains the high limit of the FAN0 tach channel.
Table 111. REGISTER 61H, FAN1 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN1 High Limit R/W This register contains the high limit of the FAN1 tach channel.
Table 112. REGISTER 62H, FAN2 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN2 High Limit R/W This register contains the high limit of the FAN2 tach channel.
Table 113. REGISTER 63H, FAN3 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN3 High Limit R/W This register contains the high limit of the FAN3 tach channel.
Table 114. REGISTER 64H, FAN4 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN4 High Limit R/W This register contains the high limit of the FAN4 tach channel.
Table 115. REGISTER 65H, FAN5 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN5 High Limit R/W This register contains the high limit of the FAN5 tach channel.
Table 116. REGISTER 66H, FAN6 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN6 High Limit R/W This register contains the high limit of the FAN6 tach channel.
Table 117. REGISTER 67H, FAN7 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN7 High Limit R/W This register contains the high limit of the FAN7 tach channel.
Table 118. REGISTER 68H, INT TEMP HIGH LIMIT (POWER-ON DEFAULT, 50H 805C)
Bit Name R/W Description
7–0 Int Temp High Limit R/W This register contains the high limit of the internal temperature channel.
Table 119. REGISTER 69H, INT TEMP HIGH LIMIT (POWER-ON DEFAULT 80H)
Bit Name R/W Description
7–0 Int Temp Low Limit R/W This register contains the low limit of the internal temperature channel.
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Table 120. REGISTER 6AH, VBAT HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 VBAT High Limit R/W This register contains the high limit of the VBAT analog input channel.
Table 121. REGISTER 6BH, VBAT LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 VBAT Low Limit R/W This register contains the low limit of the VBAT analog input channel.
Table 122. REGISTER 6CH, AIN8 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN8 High Limit R/W This register contains the high limit of the AIN8 analog input channel.
Table 123. REGISTER 6DH, AIN8 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN8 Low Limit R/W This register contains the low limit of the AIN8 analog input channel.
Table 124. REGISTER 6EH, EXT1 TEMP OFFSET (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 Ext1 Temp Offset R/W This register contains the offset value for the external 1 temperature channel. A twos
complement number can be written to this register, which is then added to the
measured result before it is stored or compared to limits. In this way, a sort of
one-point calibration can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel if the thermal
characteristics change for any reason (for instance from one chassis to another), if the
measurement point is moved, if a plug-in card is inserted or removed, and so on.
Table 125. REGISTER 6FH, EXT2 TEMP OFFSET (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 Ext2 Temp Offset R/W This register contains the offset value for the external 2 temperature channel. A twos
complement number can be written to this register, which is then added to the
measured result before it is stored or compared to limits. In this way, a sort of
one-point calibration can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel if the thermal
characteristics change for any reason (for instance from one chassis to another), if the
measurement point is moved, if a plug-in card is inserted or removed, and so on.
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PACKAGE DIMENSIONS
ÇÇÇÇ
ÉÉÉ
PLATING b1 0.17 0.23
0.2 H T-U Z DETAIL F c 0.09 0.20
ÇÇÇÇ
ÉÉÉ
H c1 0.09 0.16
0.08 Y D 9.0 BSC
c1 c
ÇÇÇÇ
ÉÉÉ
D1 7.0 BSC
e 0.5 BSC
E 9.0 BSC
E1 7.0 BSC
e/2 L 0.5 0.7
48 X b b1 L1 1.0 REF
Y 44 X e
b R 0.15 0.25
SEATING S 0.2 REF
PLANE 0.08 M Y T-U Z q 1_ 5_
q1 12 REF
SECTION G−G
q1
TOP & BOTTOM
A A2
(S) 0.250
A1 L q GAUGE PLANE
DETAIL F (L1)
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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