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ADM1026 ONSemiconductor

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25 views55 pages

ADM1026 ONSemiconductor

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Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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ADM1026

Complete Thermal System


Management Controller
The ADM1026 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and limit
comparison of various system parameters. The ADM1026 has up to 19
analog measurement channels. Fifteen analog voltage inputs are http://onsemi.com
provided, five of which are dedicated to monitoring +3.3 V, +5.0 V,
and 12 V power supplies, and the processor core voltage. The
ADM1026 can monitor two other power supply voltages by
measuring its own VCC and the main system supply. One input (two
pins) is dedicated to a remote temperature-sensing diode. Two
additional pins can be configured as general-purpose analog inputs to
measure 0 V to 2.5 V, or as a second temperature sensing input. The
eight remaining inputs are general-purpose analog inputs with a range LQFP−48
of 0 V to 2.5 V or 0 V to 3.0 V. The ADM1026 also has an on-chip CASE 932
temperature sensor.
The ADM1026 has eight pins that can be configured for fan speed MARKING DIAGRAM
measurement or as general-purpose logic I/O pins. Another eight pins are
dedicated to general-purpose logic I/O. An additional pin can be
configured as a general-purpose I/O or as the bidirectional THERM pin.
Measured values can be read out via a 2-wire serial system
ADM1026
management bus, and values for limit comparisons can be JSTZ
programmed over the same serial bus. The high speed, successive #YYWW
approximation ADC allows frequent sampling of all analog channels
to ensure a fast interrupt response to any out-of-limit measurement.
1
Features
 Up to 19 Analog Measurement Channels ADM1026JSTZ = Special Device Code
(Including Internal Measurements) # = Pb-Free Package
 Up to 8 Fan Speed Measurement Channels YYWW = Date Code
 Up to 17 General-Purpose Logic I/O Pins
 Remote Temperature Measurement with Remote Diode (Two Channels) ORDERING INFORMATION
 On-Chip Temperature Sensor See detailed ordering and shipping information in the package
dimensions section on page 54 of this data sheet.
 Analog and PWM Fan Speed Control Outputs
 2-Wire Serial System Management Bus (SMBus)
 8 kB On-Chip EEPROM
 Full SMBus 1.1 Support Includes Packet Error Checking (PEC)
 Chassis Intrusion Detection
 Interrupt Output (SMBAlert)
 Reset Input, Reset Outputs
 Thermal Interrupt (THERM) Output
 Limit Comparison of All Monitored Values
 This is a Pb-Free Device*
Applications
 Network Servers and Personal Computers
 Telecommunications Equipment
 Test Equipment and Measuring Instruments
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.

 Semiconductor Components Industries, LLC, 2012 1 Publication Order Number:


April, 2012 − Rev. 4 ADM1026/D
ADM1026

PIN ASSIGNMENT

GPIO16/THERM
AIN0(0V – 3V)
AIN1(0V – 3V)
AIN2(0V – 3V)
AIN3(0V – 3V)
AIN4(0V – 3V)
GPIO10

GPIO12
GPIO13
GPIO14
GPIO15
GPIO11
48
47
46
45
44
43
42
41
40
39
38
37
GPIO9 1 PIN 1 36 AIN5(0V – 3V)
GPIO8 2 35 AIN6(0V – 2.5V)
FAN0/GPIO0 3 34 AIN7(0V – 2.5V)
FAN1/GPIO1 4 33 +VCCP
FAN2/GPIO2 5 32 +12 VIN
FAN3/GPIO3 6 ADM1026 31 –12 VIN
TOP VIEW
3.3V MAIN 7 30 +5 VIN
DGND 8 29 VBAT
FAN4/GPIO4 9 28 D2+/AIN8(0V – 2.5V)
FAN5/GPIO5 10 27 D2–/AIN9(0V – 2.5V)
FAN6/GPIO6 11 26 D1+
FAN7/GPIO7 12 25 D1-/NTESTIN
SCL 13
SDA 14
ADD/NTESTOUT 15
CI 16
INT 17
PWM 18
RESETSTBY 19
RESETMAIN 20
AGND 21
3.3V STBY 22
DAC 23
VREF 24
ADD/ NTESTOUT SDA SCL 3.3V STBY 3.3V MAIN
VCC
GPIO15 RESET IN
GPIO14
GPIO13 3.3V MAIN
RESETMAIN
RESET
GPIO12 SERIAL BUS
GPIO GENERATOR VCC
GPIO11 INTERFACE
REGISTERS
GPIO10
100k
GPIO9
GPIO8 3.3V STBY RESETSTBY
VCC RESET
GENERATOR
FAN 7/GPIO7
FAN 6/GPIO6 PWM REGISTER
PWM
FAN 5/GPIO5 AND CONTROLLER
FAN 4/GPIO4 FAN
FAN 3/GPIO3 SPEED VALUE AND
COUNTER LIMIT
FAN 2/GPIO2 REGISTERS
FAN 1/GPIO1
ADDRESS
FAN 0/GPIO0
POINTER
LIMIT
VBAT REGISTER
COMPARATORS
+5 VIN
8k BYTES
–12 VIN EEPROM INTERRUPT
+12 VIN STATUS CI
AUTOMATIC REGISTERS VCC
+VCCP
FAN SPEED
AIN0 (0V - +3V) CONTROL 100k
INT MASK
AIN1 (0V - +3V) REGISTERS
AIN2 (0V - +3V) INT
INPUT
AIN3 (0V - +3V) ADM1026
ATTENUATORS
AIN4 (0V - +3V) AND INTERRUPT VCC
ANALOG MASKING
AIN5 (0V - +3V)
MULTIPLEXER
AIN6 (0V - +2.5V) 100k
8−BIT
AIN7 (0V - +2.5V) ADC GPIO16/THERM
D2+/AIN8 (0V - +2.5V)
CONFIGURATION
D2–/AIN9 (0V - +2.5V) REGISTERS
TO GPIO
D1+ BAND GAP REGISTERS
D1–/NTESTIN REFERENCE ANALOG
OUTPUT REGISTER DAC
BAND GAP
TEMPERATURE AND 8−BIT DAC
SENSOR

AGND DGND VREF (1.82V OR 2.5V)

Figure 1. Functional Block Diagram

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ADM1026

Table 1. ABSOLUTE MAXIMUM RATINGS


Parameter Rating Unit
Positive Supply Voltage (VCC) 6.5 V
Voltage on +12 VIN Pin +20 V
Voltage on −12 VIN Pin −20 V
Voltage on Analog Pins −0.3 to (VCC + 0.3) V
Voltage on Open-drain Digital Pins −0.3 to +6.5 V
Input Current at Any Pin 5 mA
Package Input Current 20 mA
Maximum Junction Temperature (TJMAX) 150 C
Storage Temperature Range −65 to +150 C
Lead Temperature, Soldering C
Vapor Phase (60 sec) 215
Infrared (15 sec) 200
ESD Rating V
−12 VIN Pin 1000
All Other Pins 2000
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.

Table 2. THERMAL CHARACTERISTICS


Package Type qJA qJC Unit
48-lead LQFP 50 10 C/W

Table 3. PIN ASSIGNMENT


Pin No. Mnemonic Type Description
1 GPIO9 Digital I/O† General-purpose I/O pin that can be configured as digital inputs or outputs.
2 GPIO8 Digital I/O† General-purpose I/O pin that can be configured as digital inputs or outputs.
3 FAN0/GPIO0 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
4 FAN1/GPIO1 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
5 FAN2/GPIO2 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
6 FAN3/GPIO3 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
7 3.3 V MAIN Analog Input Monitors the main 3.3 V system supply. Does not power the device.
8 DGND Ground Ground pin for digital circuits.
9 FAN4/GPIO4 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
10 FAN5/GPIO5 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
11 FAN6/GPIO6 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
12 FAN7/GPIO7 Digital I/O Fan tachometer input with internal 10 kW pullup resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.
13 SCL Digital Input Open Drain Serial Bus Clock. Requires a 2.2 kW pullup resistor.
14 SDA Digital I/O Serial Bus Data. Open drain I/O. Requires a 2.2 kW pullup resistor.
15 ADD/NTESTOUT Digital Input This is a three-state input that controls the two LSBs of the serial bus address. It
also functions as the output for NAND tree testing.
16 CI Digital Input An active high input that captures a chassis intrusion event in Bit 6 of Status
Register 4. This bit remains set until cleared, as long as battery voltage is applied
to the VBAT input, even when the ADM1026 is powered off.

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ADM1026

Table 3. PIN ASSIGNMENT


Pin No. Mnemonic Type Description
17 INT Digital Output Interrupt Request (Open Drain). The output is enabled when Bit 1 of the
configuration register is set to 1. The default state is disabled. It has an on-chip
100 kW pullup resistor.
18 PWM Digital Output Open drain pulse width modulated output for control of the fan speed. This pin
defaults to high for the 100% duty cycle for use with NMOS drive circuitry. If a
PMOS device is used to drive the fan, the PWM output may be inverted by setting
Bit 1 of Test Register 1 = 1.
19 RESETSTBY Digital Output Power-on Reset. 5 mA driver (weak 100 kW pullup), active low output (100 kW
pullup) with a 180 ms typical pulse width. RESETSTBY is asserted whenever
3.3 V STBY is below the reset threshold. It remains asserted for approximately
180 ms after 3.3 V STBY rises above the reset threshold.
20 RESETMAIN Digital I/O Power-on Reset. 5 mA driver (weak 100 kW pullup), active low output (100 kW
pullup) with a 180 ms typical pulse width. RESETMAIN is asserted whenever 3.3 V
MAIN is below the reset threshold. It remains asserted for approximately 180 ms
after 3.3 V MAIN rises above the reset threshold. If, however, 3.3 V STBY rises with
or before 3.3 V MAIN, then RESETMAIN remains asserted for 180 ms after
RESETSTBY is deasserted. Pin 20 also functions as an active low RESET input.
21 AGND Ground Ground pin for analog circuits.
22 3.3 V STBY Power Supply Supplies 3.3 V power. Also monitors the 3.3 V standby power rail.
23 DAC Analog Output 0 V to 2.5 V output for analog control of the fan speed.
24 VREF Analog Output Reference Voltage Output. Can be selected as 1.8 V (default) or 2.5 V.
25 D1–/NTESTIN Analog Input Connected to a cathode of the first remote temperature sensing diode. If it is held
high at power-on, it activates the NAND tree test mode.
26 D1+ Analog Input Connected to the anode of the first remote temperature sensing diode.
27 D2–/AIN9 Programmable Connected to the cathode of the second remote temperature sensing diode or the
analog input may be reconfigured as a 0 V − 2.5 V analog input.
28 D2+/AIN8 Programmable Connected to the anode of the second remote temperature sensing diode, or the
analog input may be reconfigured as a 0 V − 2.5 V analog input.
29 VBAT Analog Input Monitors battery voltage, nominally +3.0 V.
30 +5.0 VIN Analog Input Monitors the +5.0 V supply.
31 −12 VIN Analog Input Monitors the −12 V supply.
32 +12 VIN Analog Input Monitors the +12 V supply.
33 +VCCP Analog Input Monitors the processor core voltage (0 V to 3.0 V).
34 AIN7 Analog Input General-purpose 0 V to 2.5 V analog inputs.
35 AIN6 Analog Input General-purpose 0 V to 2.5 V analog inputs.
36 AIN5 Analog Input General-purpose 0 V to 3.0 V analog inputs.
37 AIN4 Analog Input General-purpose 0 V to 3.0 V analog inputs.
38 AIN3 Analog Input General-purpose 0 V to 3.0 V analog inputs.
39 AIN2 Analog Input General-purpose 0 V to 3.0 V analog inputs.
40 AIN1 Analog Input General-purpose 0 V to 3.0 V analog inputs.
41 AIN0 Analog Input General-purpose 0 V to 3.0 V analog inputs.
42 GPIO16/THERM Digital I/O† General-purpose I/O pin that can be configured as a digital input or output. Can
also be configured as a bidirectional THERM pin (100 kW pullup).
43 GPIO15 Digital I/O† General-purpose I/O pin that can be configured as a digital input or output.
44 GPIO14 Digital I/O† General-purpose I/O pin that can be configured as a digital input or output.
45 GPIO13 Digital I/O† General-purpose I/O pin that can be configured as a digital input or output.
46 GPIO12 Digital I/O† General-purpose I/O pin that can be configured as a digital input or output.
47 GPIO11 Digital I/O† General-purpose I/O pin that can be configured as a digital input or output.
48 GPIO10 Digital I/O† General-purpose I/O pin that can be configured as a digital input or output.
†GPIO pins are open drain and require external pullup resistors. Fan inputs have integrated 10 kW pullups, but these pins become open drain
when reconfigured as GPIOs.

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ADM1026

Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter Test Conditions/Comments Min Typ Max Unit
POWER SUPPLY
Supply Voltage, 3.3 V STBY 3.0 3.3 5.5 V
Supply Current, ICC Interface Inactive, ADC Active − 2.5 4.0 mA
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy − − 3.0 C
Resolution − 1.0 − C
External Diode Sensor Accuracy 0C < TD < 100C − − 3.0 C
Resolution − 1.0 − C
Remote Sensor Source Current High Level − 90 − mA
Low Level − 5.5 −
ANALOG-TO-DIGITAL CONVERTER
(Including MUX and ATTENUATORS)

Total Unadjusted Error (TUE) (Note 4) − − 2.0 %


Differential Non-linearity (DNL) − − 1.0 LSB
Power Supply Sensitivity − 0.1 %/V
Conversion Time − 11.38 12.06 ms
(Analog Input or Internal Temperature) (Note 5)
Conversion Time (External Temperature) (Note 5) − 34.13 36.18 ms
Input Resistance (+5.0 VIN, VCCP, AIN0 − AIN5) 80 100 120 kW
Input Resistance of +12 VIN pin 70 100 115 kW
Input Resistance of −12 VIN pin 8.0 10 12 kW
Input Resistance (AIN6 − AIN9) 5.0 − − MW
Input Resistance of VBAT pin (Note 4) 80 100 120 kW
VBAT Current Drain (when measured) CR2032 Battery Life >10 Years − 80 100 nA
VBAT Current Drain (when not measured) − 6.0 − nA
ANALOG OUTPUT (DAC)
Output Voltage Range 0 –2.5 − V
Total Unadjusted Error (TUE) IL = 2 mA − − 5.0 %
Zero Error No Load − 1.0 − LSB
Differential Non-linearity (DNL) Monotonic by Design − − 1.0 LSB
Integral Non-linearity − 0.5 − LSB
Output Source Current − 2.0 − mA
Output Sink Current − 1.0 − mA
REFERENCE OUTPUT
Output Voltage Bit 2 of Register 07h = 0 1.8 1.82 1.84 V
Bit 2 of Register 07h = 1 2.47 2.50 2.53
Load Regulation (ISINK = 2 mA) − 0.15 − %
Load Regulation (ISOURCE = 2 mA) − 0.15 − %
Short Circuit Current VCC = 3.3 V − 25 − mA
Output Current Source − 2.0 − mA
Output Current Sink − 2.0 − mA

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ADM1026

Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter Test Conditions/Comments Min Typ Max Unit
FAN RPM-TO-DIGITAL CONVERTER (Note 6)
Accuracy − − 12 %
Full-scale Count − − 255
FAN0 to FAN7 Nominal Input RPM (Note 5) Divisor = 1, fan count = 153 − 8800 − RPM
Divisor = 2, fan count = 153 − 4400 −
Divisor = 4, fan count = 153 − 2200 −
Divisor = 8, fan count = 153 − 1100 −
Internal Clock Frequency 20 22.5 25 kHz
OPEN DRAIN O/Ps, PWM, GPIO0 to 16
Output High Voltage, VOH IOUT = 3.0 mA, VCC = 3.3 V 2.4 − − V
High Level Output Leakage Current, IOH VOUT = VCC − 0.1 1.0 mA
Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 3.3 V − − 0.4 V
PWM Output Frequency − 75 − Hz
DIGITAL OUTPUTS (INT, RESETMAIN, RESETSTBY)
Output Low Voltage, VOL IOUT = −3.0 mA, VCC = 3.3 V − − 0.4 V
RESET Pulse Width 140 180 240 ms
OPEN DRAIN SERIAL DATABUS OUTPUT (SDA)
Output Low Voltage, VOL IOUT = –3.0 mA, VCC = 3.3 V − − 0.4 V
High Level Output Leakage Current, IOH VOUT = VCC − 0.1 1.0 mA
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH 2.2 − − V
Input Low Voltage, VIL − − 0.8 V
Hysteresis − 500 − mV
DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16) (Note 7 and 8)
Input High Voltage, VIH VCC = 3.3 V 2.4 − − V
Input Low Voltage, VIL VCC = 3.3 V 0.8 − − V
Hysteresis (Fan 0 to 7) VCC = 3.3 V − 250 − mV
RESETMAIN, RESETSTBY
RESETMAIN Threshold Falling Voltage 2.89 2.94 2.97 V
RESETSTBY Threshold Falling Voltage 3.01 3.05 3.10 V
RESETMAIN Hysteresis − 60 − mV
RESETSTBY Hysteresis − 70 − mV
DIGITAL INPUT CURRENT
Input High Current, IIH VIN = VCC –1.0 − − mA
Input Low Current, IIL VIN = 0 − − 1.0 mA
Input Capacitance, CIN − 20 − pF
EEPROM RELIABILITY
Endurance (Note 9) 100 700 − kcycles
Data Retention (Note 10) 10 − − Years
SERIAL BUS TIMING
Clock Frequency, fSCLK See Figure 2 for All Parameters. − − 400 kHz
Glitch Immunity, tSW − − 50 ns
Bus Free Time, tBUF 4.7 − − ms
Start Setup Time, tSU; STA 4.7 − − ms

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ADM1026

Table 4. ELECTRICAL CHARACTERISTICS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1, 2, and 3))
Parameter Test Conditions/Comments Min Typ Max Unit
SERIAL BUS TIMING
Start Hold Time, tHD; STA 4.0 − − ms
SCL Low Time, tLOW 4.7 − − ms
SCL High Time, tHIGH 4.0 − − ms
SCL, SDA Rise Time, tr − − 1000 ns
SCL, SDA Fall Time, tf − − 300 ns
Data Setup Time, tSU; DAT 250 − − ns
Data Hold Time, tHD; DAT 300 − − ns
1. All voltages are measured with respect to GND, unless otherwise specified.
2. Typicals are at TA = 25C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.
4. Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. VBAT is accurate
only for VBAT voltages greater than 1.5 V (see Figure 14).
5. Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms  11.38 ms measurements on analog input and internal
temperature channels, and 2 ms  34.13 ms measurements on external temperature channels.
6. The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number
of fans connected and the fan speed. See the Fan Speed Measurement section for more details.
7. ADD is a three-state input that may be pulled high, low, or left open circuit.
8. Logic inputs accept input high voltages up to 5.0 V even when device is operating at supply voltages below 5.0 V.
9. Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40C, +25C, and +85C. Typical endurance
at +25C is 700,000 cycles.
10. Retention lifetime equivalent at junction temperature (TJ ) = 55C as per JEDEC Std. 22 method A117. Retention lifetime based on activation
energy of 0.6 V derates with junction temperature as shown in Figure 15.

t LOW tF
t HD; STA
tR

SCL

t HD; STA t HIGH t SU; STA t SU; STO


t HD; DAT t SU; DAT

SDA
t BUF
P S S P

Figure 2. Serial Bus Timing Diagram

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ADM1026

TYPICAL PERFORMANCE CHARACTERISTICS

25 14

20
12
15

TEMPERATURE ERROR (5C)


TEMPERATURE ERROR (5C)

10
10
D+ TO GND
5 8

0 250mV
6
–5
D+ TO VCC
–10 4

–15 100mV
2
–20
0
–25
0 30 60 90 120 0 100 200 300 400 500 600
LEAKAGE RESISTANCE (M) FREQUENCY (MHz)

Figure 3. Temperature Error vs. PCB Track Figure 4. Temperature Error vs. Power Supply
Resistance Noise Frequency

12 110
100mV
100
60mV
10
40mV 90
TEMPERATURE ERROR (5C)

80
8
70
READING (5C)

60
6
50

4 40

30

2 20

10
0 0
0 100 200 300 400 500 600 0 10 20 30 40 50 60 70 80 90 100 110
FREQUENCY (MHz) PIII TEMPERATURE (5C)

Figure 5. Temperature Error vs. Common-mode Figure 6. Pentium) III Temperature vs. ADM1026
Noise Frequency Reading

5 80

70
0
TEMPERATURE ERROR (5C)
TEMPERATURE ERROR (5C)

60
–5
50

–10 40

30
–15 100mV
20
–20 60mV
40mV
10

–25 0
0 10 20 30 40 50 100 200 300 400 500 600
CAPACITANCE (nF) FREQUENCY (MHz)

Figure 7. Temperature Error vs. Capacitance Figure 8. Temperature Error vs. Differential-mode
Between D+ and D– Noise Frequency

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ADM1026

TYPICAL PERFORMANCE CHARACTERISTICS

450 3.0

400
2.5
350
RESET TIMEOUT (ms)

300 2.0

IDD (mA)
250
1.5
200

150 1.0

100
0.5
50

0
0
–40 –20 0 20 40 60 80 100 120 140 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50
TEMPERATURE (5C) VCC (V)

Figure 9. Powerup Reset Timeout vs. Temperature Figure 10. Supply Current vs. Supply Voltage

1.8 1.0

1.6
0.5
1.4
TEMPERATURE ERROR (5C)

TEMPERATURE ERROR (5C)

1.2 0

1.0
–0.5
0.8

0.6 –1.0

0.4
–1.5
0.2

0 –2.0
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
TEMPERATURE (5C) TEMPERATURE (5C)

Figure 11. Local Sensor Temperature Error Figure 12. Remote Sensor Temperature Error

3.5
120

3.0
100

2.5
VBAT MEASUREMENT
TEMPERATURE (5C)

80

2.0
60
1.5

40
1.0

20
0.5

0 0
0 2 4 6 8 10 12 14 16 18 20 22 24 26 0 1 2 3 4
TIME (s) VBAT VOLTAGE

Figure 13. Response to Thermal Shock Figure 14. VBAT Measurement vs. Voltage

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ADM1026

Functional Description Chassis Intrusion


The ADM1026 is a complete system hardware monitor for A chassis intrusion input (Pin 16) is provided to detect
microprocessor-based systems. The device communicates unauthorized tampering with the equipment. This event is
with the system via a serial system management bus. The latched in a battery-backed register bit.
serial bus controller has a hardwired address line for device
selection (ADD, Pin 15), a serial data line for reading and Resets
writing addresses and data (SDA, Pin 14), and an input line The ADM1026 has two power-on reset outputs,
for the serial clock (SCL, Pin 13). All control and RESETMAIN and RESETSTBY, that are asserted when
programming functions of the ADM1026 are performed over 3.3 V MAIN or 3.3 V STBY fall below the reset threshold.
the serial bus. These give a 180 ms reset pulse at powerup. RESETMAIN
also functions as an active-low RESET input.
Measurement Inputs
Programmability of the analog and digital measurement Fan Speed Control Outputs
inputs makes the ADM1026 extremely flexible and The ADM1026 has two outputs intended to control fan
versatile. The device has an 8-bit A/D converter, and 17 speed, though they can also be used for other purposes.
analog measurement input pins that can be configured in Pin 18 is an open drain, Pulse Width Modulated (PWM)
different ways. output with a programmable duty cycle and an output
Pins 25 and 26 are dedicated temperature inputs and may frequency of 75 Hz. Pin 23 is connected to the output of an
be connected to the cathode and anode of a remote on-chip, 8-bit, digital-to-analog converter with an output
temperature sensing diode. range of 0 V to 2.5 V.
Pins 27 and 28 may be configured as temperature inputs Either or both of these outputs may be used to implement
and connected to a second temperature-sensing diode, or may a temperature-controlled fan by controlling the speed of a
be reconfigured as analog inputs with a range of 0 V to 2.5 V. fan using the temperature measured by the on-chip
Pins 29 to 33 are dedicated analog inputs with on-chip temperature sensor or remote temperature sensors.
attenuators configured to monitor VBAT, +5.0 V, −12 V, Internal Registers
+12 V, and the processor core voltage VCCP, respectively. Table 5 describes the principal registers of the ADM1026.
Pins 34 to 41 are general-purpose analog inputs with a For more detailed information, see Table 12 to Table 125.
range of 0 V to 2.5 V or 0 V to 3.0 V. These are mainly
intended for monitoring SCSI termination voltages, but may Table 5. PRINCIPLE REGISTERS
be used for other purposes. Type Description
The ADC also accepts input from an on-chip band gap
Address Contains the address that selects one of
temperature sensor that monitors system ambient Pointer the other internal registers. When writing to
temperature. the ADM1026, the first byte of data is
In addition, the ADM1026 monitors the supply from always a register address, and is written to
the address pointer register.
which it is powered, 3.3 V STBY, so there is no need for a
separate pin to monitor the power supply voltage. Configuration Provide control and configuration for
Registers various operating parameters.
The ADM1026 has eight pins that are general-purpose
Fan Divisor Contain counter prescaler values for fan
logic I/O pins (Pins 1, 2, and 43 to 48), a pin that can be Registers speed measurement.
configured as GPIO or as a bidirectional thermal interrupt DAC/PWM Contain speed values for PWM and DAC
(THERM) pin (Pin 42), and eight pins that can be configured Control fan drive outputs.
for fan speed measurement or as general-purpose logic pins Registers
(Pins 3 to 6 and Pins 9 to 12). GPIO Configure the GPIO pins as input or output
Configuration and for signal polarity.
Sequential Measurement Registers
When the ADM1026 monitoring sequence is started, it Value and Store the results of analog voltage inputs,
cycles sequentially through the measurement of analog Limit temperature, and fan speed measurements,
Registers along with their limit values.
inputs and the temperature sensor, while at the same time the
fan speed inputs are independently monitored. Measured Status Store events from the various interrupt
Registers sources.
values from these inputs are stored in value registers. These
Mask Allow masking of individual interrupt
can be read over the serial bus, or can be compared with Registers sources.
programmed limits stored in the limit registers. The results
of out-of-limit comparisons are stored in the interrupt status EEPROM
registers. An out-of-limit event generates an interrupt on the The ADM1026 has 8 kB of non-volatile, electrically
INT line (Pin 17). erasable, programmable read-only memory (EEPROM)
Any or all of the interrupt status bits can be masked by from register Addresses 8000h to 9FFFh. This may be used
appropriate programming of the interrupt mask registers. for permanent storage of data that is not lost when the

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ADM1026

ADM1026 is powered down, unlike the data in the volatile Serial Bus Interface
registers. Although referred to as read-only memory, the Control of the ADM1026 is carried out via the serial
EEPROM can be written to (as well as read from) via the system management bus (SMBus). The ADM1026 is
serial bus in exactly the same way as the other registers. The connected to this bus as a slave device, under the control of
main differences between the EEPROM and other registers a master device.
are: The ADM1026 has a 7-bit serial bus slave address. When
 An EEPROM location must be blank before it can be the device is powered on, it does so with a default serial bus
written to. If it contains data, it must first be erased. address. The 5 MSBs of the address are set to 01011, and the
 Writing to EEPROM is slower than writing to RAM. 2 LSBs are determined by the logical states of Pin 15
ADD/NTESTOUT. This pin is a three-state input that can be
 Writing to the EEPROM should be restricted because grounded, connected to VCC, or left open-circuit to give
its typical cycle life is 100,000 write operations, due to three different addresses.
the usual EEPROM wear-out mechanisms.
Table 6. ADDRESS PIN TRUTH TABLE
The EEPROM in the ADM1026 has been qualified for
two key EEPROM memory characteristics: memory cycling ADD Pin A1 A0
endurance and memory data retention. GND 0 0
Endurance qualifies the ability of the EEPROM to be No Connect 1 0
cycled through many program, read, and erase cycles. In real VCC 0 1
terms, a single endurance cycle is composed of four
independent, sequential events, as follows: If ADD is left open-circuit, the default address is 0101110
1. Initial page erase sequence (5Ch). ADD is sampled only at powerup on the first valid
2. Read/verify sequence SMBus transaction, so any changes made while the power
3. Program sequence is on (and the address is locked) have no effect.
4. Second read/verify sequence The facility to make hardwired changes to device
addresses allows the user to avoid conflicts with other
In reliability qualification, every byte is cycled from 00h devices sharing the same serial bus, for example if more than
to FFh until a first fail is recorded, signifying the endurance one ADM1026 is used in a system.
limit of the EEPROM memory.
Retention quantifies the ability of the memory to retain its General SMBus Timing
programmed data over time. The EEPROM in the ADM1026 Figure 16 and Figure 17 show timing diagrams for general
has been qualified in accordance with the formal JEDEC read and write operations using the SMBus. The SMBus
Retention Lifetime Specification (A117) at a specific junction specification defines specific conditions for different types
temperature (TJ = 55C) to guarantee a minimum of 10 years of read and write operations, which are discussed later in this
retention time. As part of this qualification procedure, the section. The general SMBus protocol* operates as follows:
EEPROM memory is cycled to its specified endurance limit 1. The master initiates data transfer by establishing a
described above before data retention is characterized. This start condition, defined as a high-to-low transition
means that the EEPROM memory is guaranteed to retain its on the serial data line (SDA) while the serial clock
data for its full specified retention lifetime every time the line SCL remains high. This indicates that a data
EEPROM is reprogrammed. Note that retention lifetime stream follows. All slave peripherals connected to
based on an activation energy of 0.6 V derates with TJ, as the serial bus respond to the start condition and
shown in Figure 15. shift in the next 8 bits, consisting of a 7-bit slave
300 address (MSB first) and an R/W bit, which
determine the direction of the data transfer, that is,
250 whether data is written to or read from the slave
device (0 = write, 1 = read).
The peripheral whose address corresponds to the
RETENTION (Years)

200
trans-mitted address responds by pulling the data
150 line low during the low period before the ninth
clock pulse, known as the acknowledge bit, and
100 holding it low during the high period of this clock
pulse. All other devices on the bus remain idle
50 while the selected device waits for data to be read
from or written to it. If the R/W bit is 0, the master
0 writes to the slave device. If the R/W bit is 1, the
40 50 60 70 80 90 100 110 120
JUNCTION TEMPERATURE (5C) master reads from the slave device.
Figure 15. Typical EEPROM Memory Retention

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ADM1026

2. Data is sent over the serial bus in sequences of nine Before doing a read operation, it may first be
clock pulses, 8 bits of data followed by an necessary to do a write operation to tell the slave
acknowledge bit from the slave device. Data what type of read operation to expect and/or the
transitions on the data line must occur during the address from which data is to be read.
low period of the clock signal and remain stable 3. When all data bytes have been read or written, stop
during the high period, because a low-to-high conditions are established. In write mode, the master
transition when the clock is high may be interpreted pulls the data line high during the 10th clock pulse
as a stop signal. to assert a stop condition. In read mode, the master
If the operation is a write operation, the first data device releases the SDA line during the low period
byte after the slave address is a command byte. before the ninth clock pulse, but the slave device
This tells the slave device what to expect next. It does not pull it low (called No Acknowledge). The
may be an instruction telling the slave device to master takes the data line low during the low period
expect a block write, or it may simply be a register before the 10th clock pulse, then high during the
address that tells the slave where subsequent data is 10th clock pulse to assert a stop condition.
to be written.
*If it is required to perform several read or write operations in
Because data can flow in only one direction as succession, the master can send a repeat start condition instead
defined by the R/W bit, it is not possible to send a of a stop condition to begin a new operation.
command to a slave device during a read operation.

1 9 1 9

SCL

SDA 0 1 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE SLAVE
FRAME 1 FRAME 2
SLAVE ADDRESS COMMAND CODE

1 9 1 9
SCL
(CONTINUED)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY ACK. BY STOP BY
SLAVE SLAVE MASTER
FRAME 3 FRAME N
DATA BYTE DATA BYTE

Figure 16. General SMBus Write Timing Diagram

1 9 1 9

SCL

SDA 0 1 0 1 1 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0
START BY ACK. BY ACK. BY
MASTER SLAVE MASTER
FRAME 1 FRAME 2
SLAVE ADDRESS DATA BYTE

1 9 1 9
SCL
(CONTINUED)

SDA D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
(CONTINUED)
ACK. BY NO ACK. STOP BY
MASTER MASTER
FRAME 3 FRAME N
DATA BYTE DATA BYTE

Figure 17. General SMBus Read Timing Diagram

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ADM1026

SMBus Protocols for RAM and EEPROM S − START


The ADM1026 contains volatile registers (RAM) and W − WRITE
non-volatile EEPROM. RAM occupies Addresses 00h to P − STOP
6Fh, while EEPROM occupies Addresses 8000h to 9FFFh. A − ACKNOWLEDGE
Data can be written to and read from both RAM and R −READ
EEPROM as single data bytes and as block (sequential) read A − NO ACKNOWLEDGE
or write operations of 32 data bytes, the maximum block size
allowed by the SMBus specification. ADM1026 Write Operations
Data can only be written to unprogrammed EEPROM Send Byte
locations. To write new data to a programmed location, it is In this operation, the master device sends a single
first necessary to erase it. EEPROM erasure cannot be done command byte to a slave device, as follows:
at the byte level; the EEPROM is arranged as 128 pages of 1. The master device asserts a start condition on the
64 bytes, and an entire page must be erased. Note that of SDA.
these 128 pages, only 124 pages are available to the user. The 2. The master sends the 7-bit slave address followed
last four pages are reserved for manufacturing purposes and by the write bit (low).
cannot be erased/rewritten. 3. The addressed slave device asserts an ACK on the
The EEPROM has three RAM registers associated with it, SDA.
EEPROM Registers 1, 2, and 3 at Addresses 06h, 0Ch, and 4. The master sends a command code.
13h. EEPROM Registers 1 and 2 are for factory use only. 5. The slave asserts ACK on the SDA.
EEPROM Register 3 sets up the EEPROM operating mode. 6. The master asserts a stop condition on the SDA
Setting Bit 0 of EEPROM Register 3 puts the EEPROM into and the transaction ends.
read mode. Setting Bit 1 puts it into programming mode.
In the ADM1026, the send byte protocol is used to write
Setting Bit 2 puts it into erase mode.
a register address to RAM for a subsequent single−byte read
Only one of these bits must be set before the EEPROM
from the same address or block read or write starting at that
may be accessed. Setting no bits or more than one of them
address. This is illustrated in Figure 18.
causes the device to respond with No Acknowledge if an
1 2 3 4 5 6
EEPROM read, program, or erase operation is attempted. RAM
SLAVE
It is important to distinguish between SMBus write S
ADDRESS
W A ADDRESS A P
(00h TO 6Fh)
operations, such as sending an address or command, and
EEPROM programming operations. It is possible to write an Figure 18. Setting a RAM Address for Subsequent Read
EEPROM address over the SMBus, whatever the state of
If it is required to read data from the RAM immediately
EEPROM Register 3. However, EEPROM Register 3 must
after setting up the address, the master can assert a repeat
be correctly set before a subsequent EEPROM operation can
start condition immediately after the final ACK and carry
be performed. For example, when reading from the
out a single byte read, block read, or block write operation
EEPROM, Bit 0 of EEPROM Register 3 can be set, even
without asserting an intermediate stop condition.
though SMBus write operations are required to set up the
EEPROM address for reading. Bit 3 of EEPROM Register 3 Write Byte/Word
is used for EEPROM write protection. Setting this bit In this operation, the master device sends a command byte
prevents accidental programming or erasure of the and one or two data bytes to the slave device as follows:
EEPROM. If an EEPROM write or erase operation is 1. The master device asserts a start condition on the
attempted when this bit is set, the ADM1026 responds with SDA.
No Acknowledge. This bit is write-once and can only be 2. The master sends the 7-bit slave address followed
cleared by a power-on reset. by the write bit (low).
EEPROM Register 3 Bit 7 is used for clock extend. 3. The addressed slave device asserts an ACK on the
Programming an EEPROM byte takes approximately SDA.
250 ms, which would limit the SMBus clock for repeated or 4. The master sends a command code.
block write operations. Because EEPROM block read/write 5. The slave asserts an ACK on the SDA.
access is slow, it is recommended that this clock extend bit 6. The master sends a data byte.
typically be set to 1. This allows the ADM1026 to pull SCL 7. The slave asserts an ACK on the SDA.
low and extend the clock pulse when it cannot accept any 8. The master sends a data byte (or may assert stop
more data. here.)
9. The slave asserts an ACK on the SDA.
ADM1026 SMBus Operations
10. The master asserts a stop condition on the SDA to
The SMBus specifications define several protocols for
end the transaction.
different types of read and write operations. The ones used
in the ADM1026 are discussed below. The following
abbreviations are used in the diagrams:

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ADM1026

In the ADM1026, the write byte/word protocol is used for byte is the actual data. Bit 1 of EEPROM Register 3 must be
four purposes. The ADM1026 knows how to respond by the set. This is illustrated in Figure 22.
value of the command byte and EEPROM Register 3. 1 2 3 4 5 6 7 8 9 10
The first purpose is to write a single byte of data to RAM. EEPROM EEPROM
SLAVE ADDRESS ADDRESS
In this case, the command byte is the RAM address from 00h S
ADDRESS
W A
HIGH BYTE
A
LOW BYTE
A DATA A Y
(80h TO 9Fh) (00h TO FFh)
to 6Fh and the (only) data byte is the actual data. This is
illustrated in Figure 19. Figure 22. Single-Byte Write to EEPROM
1 2 3 4 5 6 7 8

S
SLAVE
W A
RAM
ADDRESS A DATA A P
Block Write
ADDRESS
(00h TO 6Fh) In this operation, the master device writes a block of data
to a slave device. The start address for a block write must
Figure 19. Single Byte Write to RAM
have been set previously. In the case of the ADM1026, this
The protocol is also used to set up a 2-byte EEPROM is done by a Send Byte operation to set a RAM address or by
address for a subsequent read or block read. In this case, the a write byte/word operation to set an EEPROM address.
command byte is the high byte of the EEPROM address 1. The master device asserts a start condition on the
from 80h to 9Fh. The (only) data byte is the low byte of the SDA.
EEPROM address. This is illustrated in Figure 20. 2. The master sends the 7-bit slave address followed
1 2 3 4 5 6 7 8 by the write bit (low).
SLAVE
EEPROM
ADDRESS
EEPROM 3. The addressed slave device asserts an ACK on the
S W A A ADDRESS A P
ADDRESS HIGH BYTE LOW BYTE SDA.
(80h TO 9Fh) (00h TO FFh)
4. The master sends a command code that tells the
Figure 20. Setting an EEPROM Address slave device to expect a block write. The
ADM1026 command code for a block write is A0h
If it is required to read data from the EEPROM
(10100000).
immediately after setting up the address, the master can
5. The slave asserts an ACK on the SDA.
assert a repeat start condition immediately after the final
6. The master sends a data byte (20h) that tells the
ACK and carry out a single-byte read or block read operation
slave device that 32 data bytes are being sent to it.
without asserting an intermediate stop condition. In this
The master should always send 32 data bytes to
case, Bit 0 of EEPROM Register 3 should be set.
the ADM1026.
The third use is to erase a page of EEPROM memory.
7. The slave asserts an ACK on the SDA.
EEPROM memory can be written to only if it is previously
8. The master sends 32 data bytes.
erased. Before writing to one or more EEPROM memory
9. The slave asserts an ACK on the SDA after each
locations that are already programmed, the page or pages
data byte.
containing those locations must first be erased. EEPROM
10. The master sends a packet error checking (PEC)
memory is erased by writing an EEPROM page address plus
byte.
an arbitrary byte of data with Bit 2 of EEPROM Register 3
11. The ADM1026 checks the PEC byte and issues an
set to 1.
ACK if correct. If incorrect (NACK), the master
Because the EEPROM consists of 128 pages of 64 bytes,
resends the data bytes.
the EEPROM page address consists of the EEPROM
12. The master asserts a stop condition on the SDA to
address high byte (from 80h to 9Fh) and the two MSBs of the
end the transaction.
low byte. The lower six bits of the EEPROM address (low
byte only) specify addresses within a page and are ignored
during an erase operation. S SLAVE W A
COMMAND
A0h BLOCK A BYTE A DATA 1 A DATA 2 A
DATA A PEC A P
ADDRESS COUNT 32
WRITE
1 2 3 4 5 6 7 8 9 10
EEPROM EEPROM
S
SLAVE
W A
ADDRESS
A
ADDRESS
A
ARBITRARY A Y Figure 23. Block Write to EEPROM or RAM
ADDRESS HIGH BYTE LOW BYTE DATA
(80h TO 9Fh) (00h TO FFh)
When performing a block write to EEPROM, Bit 1 of
Figure 21. EEPROM Page Erasure EEPROM Register 3 must be set. Unlike some EEPROM
devices that limit block writes to within a page boundary,
Page erasure takes approximately 20 ms. If the EEPROM
there is no limitation on the start address when performing
is accessed before erasure is complete, the ADM1026
a block write to EEPROM, except:
responds with No Acknowledge.
Last, this protocol is used to write a single byte of data to  There must be at least 32 locations from the start
EEPROM. In this case, the command byte is the high byte address to the highest EEPROM address (9FF) to avoid
of the EEPROM address from 80h to 9Fh. The first data byte writing to invalid addresses.
is the low byte of the EEPROM address, and the second data  If the addresses cross a page boundary, both pages must
be erased before programming.

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ADM1026

ADM1026 Read Operations ADM1026 always returns 32 data bytes (20h), the
The ADM1026 uses the SMBus read protocols described maximum allowed by the SMBus 1.1 specification.
here. 10. The master asserts an ACK on the SDA.
11. The master receives 32 data bytes.
Receive Byte
12. The master asserts an ACK on the SDA after each
In this operation, the master device receives a single byte data byte.
from a slave device as follows: 13. The ADM1026 issues a PEC byte to the master.
1. The master device asserts a start condition on the The master should check the PEC byte and issue
SDA. another block read if the PEC byte is incorrect.
2. The master sends the 7-bit slave address followed 14. A NACK is generated after the PEC byte to signal
by the read bit (high). the end of the read.
3. The addressed slave device asserts an ACK on the 15. The master asserts a stop condition on the SDA to
SDA. end the transaction.
4. The master receives a data byte.
5. The master asserts a NO ACK on the SDA.
COMMAND
6. The master asserts a stop condition on the SDA to S SLAVE
ADDRESS
W A A1h BLOCK A S SLAVE
ADDRESS
R
READ
end the transaction.
In the ADM1026, the receive byte protocol is used to read
a single byte of data from a RAM or EEPROM location A
BYTE
A DATA 1 A
DATA
A PEC A P
COUNT 32
whose address has previously been set by a send byte or
write byte/word operation. Figure 24 shows this. When
reading from EEPROM, Bit 0 of EEPROM Register 3 must Figure 25. Block Read from EEPROM or RAM
be set.
1 2 3 4 5 6 When block reading from EEPROM, Bit 0 of EEPROM
SLAVE
Register 3 must be set.
S R A DATA A P
ADDRESS Note that although the ADM1026 supports Packet Error
Checking (PEC), its use is optional. The PEC byte is
Figure 24. Single-Byte Read from EEPROM or RAM calculated using CRC-8. The Frame Check Sequence (FCS)
conforms to CRC-8 by the polynomial:
Block Read
In this operation, the master device reads a block of data C(x) + x 8 ) x 2 ) x ) 1 (eq. 1)
from a slave device. The start address for a block read must Consult the SMBus 1.1 Specification for more information.
have been set previously. In the case of the ADM1026 this
is done by a send byte operation to set a RAM address, or by Measurement Inputs
a write byte/word operation to set an EEPROM address. The The ADM1026 has 17 external analog measurement pins
block read operation consists of a send byte operation that that can be configured to perform various functions. It also
sends a block read command to the slave, immediately measures two supply voltages, 3.3 V MAIN and 3.3 V
followed by a repeated start and a read operation that reads STBY, and the internal chip temperature.
out multiple data bytes as follows: Pins 25 and 26 are dedicated to remote temperature
1. The master device asserts a start condition on the measurement, while Pins 27 and 28 can be configured as
SDA. analog inputs with a range of 0 V to 2.5 V, or as inputs for
2. The master sends the 7-bit slave address followed a second remote temperature sensor.
by the write bit (low). Pins 29 to 33 are dedicated to measuring VBAT, +5.0 V,
3. The addressed slave device asserts an ACK on the −12 V, +12 V supplies, and the processor core voltage VCCP.
SDA. The remaining analog inputs, Pins 34 to 41, are
4. The master sends a command code that tells the general-purpose analog inputs with a range of 0 V to 2.5 V
slave device to expect a block read. The (Pins 34 and 35) or 0 V to 3.0 V (Pins 36 to 41).
ADM1026 command code for a block read is A 1h
(10100001). A-to-D Converter (ADC)
5. The slave asserts an ACK on the SDA. These inputs are multiplexed into the on-chip, successive
6. The master asserts a repeat start condition on the approximation, analog-to-digital converter. The ADC has a
SDA. resolution of 8 bits. The basic input range is 0 V to 2.5 V,
7. The master sends the 7-bit slave address followed which is the input range of AIN6 to AIN9, but five of the
by the read bit (high). inputs have built-in attenuators to allow measurement of
8. The slave asserts an ACK on the SDA. VBAT, +5.0 V, -12 V, +12 V, and the processor core voltage
9. The ADM1026 sends a byte count data byte that VCCP, without any external components. To allow the
tells the master how many data bytes to expect. The tolerance of these supply voltages, the ADC produces an

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ADM1026

output of 3/4 full scale (decimal 192) for the nominal input averaged to reduce noise, so the total conversion time for each
voltage, and so has adequate headroom to cope with over input is 11.38 ms.
voltages. Table 7 shows the input ranges of the analog inputs Measurements on the remote temperature (D1 and D2)
and output codes of the ADC. inputs take 2.13 ms. These are also measured 16 times and
When the ADC is running, it samples and converts an are averaged, so the total conversion time for a remote
analog or local temperature input every 711 ms (typical value). temperature input is 34.13 ms.
Each input is measured 16 times and the measurements are

Table 7. A-TO-D OUTPUT CODES VS. VIN


Input Voltage A-to-D Output
+12 VIN –12 VIN +5.0 VIN 3.3 V MAIN VBAT VCCP AIN (0–5) AIN (6–9) Decimal Binary
< 0.0625 < −15.928 < 0.026 < 0.0172 NA < 0.012 < 0.012 < 0.010 0 00000000
0.062−0.125 −15.928−15.855 0.026−0.052 0.017−0.034 NA 0.012−0.023 0.012−0.023 0.010−0.019 1 00000001
0.125−0.187 −15.855−15.783 0.052−0.078 0.034−0.052 NA 0.023−0.035 0.023−0.035 0.019−0.029 2 00000010
0.188−0.250 −15.783−15.711 0.078−0.104 0.052−0.069 NA 0.035−0.047 0.035−0.047 0.029−0.039 3 00000011
0.250−0.313 −15.711−15.639 0.104−0.130 0.069−0.086 NA 0.047−0.058 0.047−0.058 0.039−0.049 4 00000100
0.313−0.375 −15.639−15.566 0.130−0.156 0.086−0.103 NA 0.058−0.070 0.058−0.070 0.049−0.058 5 00000101
0.375−0.438 −15.566−15.494 0.156−0.182 0.103−0.120 NA 0.070−0.082 0.070−0.082 0.058−0.068 6 00000110
0.438−0.500 −15.494−15.422 0.182−0.208 0.120−0.138 NA 0.082−0.094 0.082−0.094 0.068−0.078 7 00000111
0.500−0.563 −15.422−15.349 0.208−0.234 0.138−0.155 NA 0.094−0.105 0.094−0.105 0.078−0.087 8 00001000



4.000−4.063 −11.375−11.303 1.667−1.693 1.110−1.127 NA 0.750−0.780 0.750−0.780 0.625−0.635 64 01000000
(1⁄4 scale)




8.000−8.063 −6.750−6.678 3.333−3.359 2.000−2.016 2.000−2.016 1.500−1.512 1.500−1.512 1.250−1.260 128 10000000
(1⁄2 scale)




12.000−12.063 −2.125−2.053 5−5.026 3.330−3.347 3.000−3.016 2.250−2.262 2.250−2.262 1.875−1.885 192 11000000
(3⁄4 scale)




15.313−15.375 1.705−1.777 6.38−6.406 4.249−4.267 3.828−3.844 2.871−2.883 2.871−2.883 2.392−2.402 245 11110101
15.375−15.437 1.777−1.850 6.406−6.432 4.267−4.284 3.844−3.860 2.883−2.895 2.883−2.895 2.402−2.412 246 11110110
15.437−15.500 1.850−1.922 6.432−6.458 4.284−4.301 3.860−3.875 2.895−2.906 2.895−2.906 2.412−2.422 247 11110111
15.500−15.563 1.922−1.994 6.458−6.484 4.301−4.319 3.875−3.890 2.906−2.918 2.906−2.918 2.422−2.431 248 11111000
15.562−15.625 1.994−2.066 6.484−6.51 4.319−4.336 3.890−3.906 2.918−2.930 2.918−2.930 2.431−2.441 249 11111001
15.625−15.688 2.066−2.139 6.51−6.536 4.336−4.353 3.906−3.921 2.930−2.941 2.930−2.941 2.441−2.451 250 11111010
15.688−15.750 2.139−2.211 6.536−6.563 4.353−4.371 3.921−3.937 2.941−2.953 2.941−2.953 2.451−2.460 251 11111011
15.750−15.812 2.211−2.283 6.563−6.589 4.371−4.388 3.937−3.953 2.953−2.965 2.953−2.965 2.460−2.470 252 11111100
15.812−15.875 2.283−2.355 6.589−6.615 4.388−4.405 3.953−3.969 2.965−2.977 2.965−2.977 2.470−2.480 253 11111101
15.875−15.938 2.355−2.428 6.615−6.641 4.405−4.423 3.969−3.984 2.977−2.988 2.977−2.988 2.480−2.490 254 11111110
>15.938 >2.428 >6.634 >4.423 >3.984 >2.988 >2.988 >2.490 255 11111111

1. * VBAT is not accurate for voltages under 1.5 V (see Figure 14).

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ADM1026

Voltage Measurement Inputs However, when scaling AIN0 to AIN5, it should be noted
The internal structure for all the analog inputs is shown in that these inputs already have an on-chip attenuator, because
Figure 26. Each input circuit consists of an input protection their primary function is to monitor SCSI termination
diode, an attenuator, plus a capacitor to form a first-order voltages. This attenuator loads any external attenuator. The
low-pass filter that gives each voltage measurement input input resistance of the on-chip attenuator can be between
immunity to high frequency noise. The −12 V input also has 100 kW and 200 kW. For this tolerance not to affect the
a resistor connected to the on-chip reference to offset the accuracy, the output resistance of the external attenuator
negative voltage range so that it is always positive and can should be very much lower than this, that is, 1 kW in order
be handled by the ADC. This allows most popular power to add not more than 1% to the total unadjusted error (TUE).
supply voltages to be monitored directly by the ADM1026 Alternatively, the input can be buffered using an op amp.
without requiring any additional resistor scaling.
ǒVfs * 3.0Ǔ
AIN0 – A IN5
21.9k R1 + ǒfor A IN0 through A IN5Ǔ (eq. 2)
(0V – 3V) R2 3.0
109.4k 4.6pF
ǒVfs * 2.5Ǔ
R1 + ǒfor A IN6 through A IN9Ǔ (eq. 3)
AIN6 – A IN9
52.5k R2 2.5
(0V – 2.5V)
4.6pF Negative and bipolar input ranges can be accommodated
by using a positive reference voltage to offset the input
113.5k voltage range so that it is always positive. To monitor a
+12V
negative input voltage, an attenuator can be used as shown
21k 9.3pF
in Figure 28.

VREF
R2
17.5k MUX AIN(0–9)
R1
114.3k VIN
–12V
9.3pF

83.5k
+5V
50k 4.6pF Figure 28. Scaling and Offsetting AIN0 − AIN9
for Negative Inputs

VBAT
49.5k This offsets the negative voltage so that the ADC always
sees a positive voltage. R1 and R2 are chosen so that the
82.7k
4.5pF
ADC input voltage is zero when the negative input voltage
* SEE TEXT is at its maximum (most negative) value, that is:

+VCCP
21.9k
R1 +
R2
Ť Ť
Vf *
s
V OS (eq. 4)
109.4k 18.5pF
This is a simple and low cost solution, but note the
following:
 Because the input signal is offset but not inverted, the
Figure 26. Voltage Measurement Inputs
input range is transposed. An increase in the magnitude
Setting Other Input Ranges of the negative voltage (going more negative) causes the
AIN0 to AIN9 can easily be scaled to voltages other than input voltage to fall and give a lower output code from
2.5 V or 3.0 V. If the input voltage range is zero to some the ADC. Conversely, a decrease in the magnitude of the
positive voltage, all that is required is an input attenuator, as negative voltage causes the ADC code to increase. The
shown in Figure 27. maximum negative voltage corresponds to zero output
from the ADC. This means that the upper and lower
limits are transposed.
AIN(0–9)
VIN
R1
 For the ADC output to be full scale when the negative
voltage is zero, VOS must be greater than the full−scale
R2
voltage of the ADC, because VOS is attenuated by R1 and
R2. If VOS is equal to or less than the full−scale voltage
of the ADC, the input range is bipolar but not necessarily
Figure 27. Scaling AIN0 − AIN9 symmetrical.

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ADM1026

For example, when VBAT = 3.0 V,


This is a problem only if the ADC output must be full scale
3.0 V 711 ms
when the negative voltage is zero. I+ + 78 nA (eq. 9)
Symmetrical bipolar input ranges can be accommodated 100 kW 273 ms
easily by making VOS equal to the full-scale voltage of the where TPULSE = VBAT measurement time (711 ms typical),
analog input, and by adding a third resistor to set the positive TPERIOD = time to measure all analog inputs (273 ms
full scale. typical), and VBAT input battery protection.
+VOS
VBAT Input Battery Protection
R2 In addition to minimizing battery current drain, the VBAT
R1
AIN(0–9)
measurement circuitry was specifically designed with
VIN
battery protection in mind. Internal circuitry prevents the
R3 battery from being back-biased by the ADM1026 supply or
through any other path under normal operating conditions.
In the unlikely event of a catastrophic ADM1026 failure, the
Figure 29. Scaling and Offsetting AIN0 − AIN9 ADM1026 includes a second level of battery protection
for Bipolar Inputs including a series 3 kW resistor to limit current to the battery,
Ť
V *
R1 + fs
Ť as recommended by UL. Thus, it is not necessary to add a
series resistor between the battery and the VBAT input; the
R2 V OS (eq. 5) battery can be connected directly to the VBAT input to
Note that R3 has no effect as the input voltage at the device improve voltage measurement accuracy.
pin is zero when VIN = negative full scale. VBAT
DIGITAL
ǒVfs * 3.0Ǔ 49.5k 3k
CONTROL

R1 + ǒfor A IN0 through A IN5Ǔ (eq. 6)


R3 3.0 3k
ADC

ǒVfs * 2.5Ǔ
4.5pF
82.7k
R1 + ǒfor A IN6 through A IN9Ǔ (eq. 7)
R3 2.5
Also, note that R2 has no effect as the input voltage at the
device pin is equal to VOS when VIN = positive full scale. Figure 30. Equivalent VBAT Input Protection Circuit

Battery Measurement Input (VBAT) Reference Output (VREF)


The VBAT input allows the condition of a CMOS backup The ADM1026 offers an on-chip reference voltage
battery to be monitored. This is typically a lithium coin cell (Pin 24) that can be used to provide a 1.82 V or 2.5 V
such as a CR2032. The VBAT input is accurate only for reference voltage output. This output is buffered and
voltages greater than 1.5 V (see Figure 14). Typically, the specified to sink or source a load current of 2 mA. The
battery in a system is required to keep some device powered reference voltage outputs 1.82 V if Bit 2 of Configuration
on when the system is in a powered-off state. The VBAT Register 3 (Address 07h) is 0; it outputs 2.5 V when this bit
measurement input is specially designed to minimize battery is set to 1. This voltage reference output can be used to
drain. To reduce current drain from the battery, the lower provide a stable reference voltage to external circuitry such
resistor of the VBAT attenuator is not connected, except as LDOs. The load regulation of the VREF output is typically
whenever a VBAT measurement is being made. The total 0.15% for a sink current of 2 mA and 0.15% for 2 mA source
current drain on the VBAT pin is 80 nA typical (for a current. There may be some ripple present on the VREF
maximum VBAT voltage = 4.0 V), so a CR2032 CMOS output that requires filtering (4 m VMAX). Figure 31 shows
battery functions in a system in excess of the expected 10 the recommended circuitry for the VREF output for loads less
years. Note that when a VBAT measurement is not being than 2 mA. For loads in excess of 2 mA, external circuitry,
made, the current drain is reduced to 6 nA typical. Under such as that shown in Figure 32, can be used to buffer the
normal voltage measurement operating conditions, all VREF output.
measurements are made in a round-robin format, and each
ADM1026
reading is actually the result of 16 digitally averaged
measurements. However, averaging is not carried out on the 24 10k
VREF VREF
VBAT measurement to reduce measurement time and
therefore reduce the current drain from the battery. 0.1F

The VBAT current drain when a measurement is being


made is calculated by:
V BAT T PULSE
I+ (eq. 8) Figure 31. VREF Interface Circuit for VREF Loads < 2 mA
100 kW T PERIOD

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ADM1026

If the VREF output is not being used, it should be left by clearing Bit 3 of Configuration Register 1 (Address 00h)
unconnected. Do not connect VREF to GND using a to 0. If this bit is 1, then Pins 27 and 28 are AIN8 and AIN9.
capacitor. The internal output buffer on the voltage reference The forward voltage of a diode or diode-connected
is capacitively loaded, which can cause the voltage reference transistor, operated at a constant current, exhibits a negative
to oscillate. This affects temperature readings reported back temperature coefficient of about −2 mV/C. Unfortunately,
by the ADM1026. The recommended interface circuit for the absolute value of Vbe varies from device to device, and
the VREF output is shown in Figure 32. individual calibration is required to null this out, so the
technique is unsuitable for mass production.
+12V
The technique used in the ADM1026 is to measure the
change in Vbe when the device is operated at two different
ADM1026 currents, given by:
24
10k
VREF
NDT3055 DV be + K q T log n (N) (eq. 10)

VREF where K is Boltzmann’s constant, q is the charge on the


0.1F
carrier, T is the absolute temperature in Kelvins, and N is the
50 0.1F 10F
ratio of the two currents.
Figure 33 shows the input signal conditioning used to
measure the output of a remote temperature sensor. This
figure shows the external sensor as a substrate transistor
Figure 32. VREF Interface Circuit for VREF Loads > 2 mA provided for temperature monitoring on some
microprocessors, but it could equally well be a discrete
Temperature Measurement System
transistor such as a 2N3904.
Local Temperature Measurement
If a discrete transistor is used, the collector is not grounded
The ADM1026 contains an on-chip band gap temperature and should be linked to the base. If a PNP transistor is used,
sensor whose output is digitized by the on-chip ADC. The the base is connected to the D− input and the emitter to the
temperature data is stored in the local temperature value D+ input. If an NPN transistor is used, the emitter is
register (Address 1Fh). As both positive and negative connected to the D− input and the base to the D+ input.
temperatures can be measured, the temperature data is stored To prevent ground noise from interfering with the
in twos complement format, as shown in Table 8. measurement, the more negative terminal of the sensor is not
Theoretically, the temperature sensor and ADC can measure referenced to ground but is biased above ground by an
temperatures from −128C to +127C with a resolution of internal diode at the D− input.
1C. Temperatures below TMIN and above TMAX are outside
To measure DVbe, the sensor is switched between
the operating temperature range of the device; however, so
operating currents of I and N  I. The resulting waveform is
local temperature measurements outside this range are not
passed through a 65 kHz low−pass filter to remove noise,
possible. Temperature measurement from −128C to
and to a chopper-stabilized amplifier that performs the
+127C is possible using a remote sensor.
functions of amplification and rectification of the waveform
Remote Temperature Measurement to produce a DC voltage proportional to DVbe. This voltage
The ADM1026 can measure the temperature of two is measured by the ADC to give a temperature output in
remote diode sensors, or diode-connected transistors, 8-bit, twos complement format. To further reduce the effects
connected to Pins 25 and 26, or 27 and 28. of noise, digital filtering is performed by averaging the
Pins 25 and 26 are a dedicated temperature input channel. results of 16 measurement cycles. A remote temperature
Pins 27 and 28 can be configured to measure a diode sensor measurement takes nominally 2.14 ms.

VDD
I NxI IBIAS

D+
VOUT+

REMOTE C1* TO ADC


SENSING
BIAS VOUT–
TRANSISTOR D– LOW−PASS FILTER
DIODE
fC = 65kHz

* CAPACITOR C1 IS OPTIONAL. IT IS ONLY NECESSARY IN NOISY ENVIRONMENTS.


C1 = 2.2nF TYPICAL, 3nF MAX.

Figure 33. Signal Conditioning for Remote Diode Temperature Sensors

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ADM1026

The results of external temperature measurements are thermocouple voltages are about 3 mV/C of temperature
stored in 8-bit, twos complement format, as illustrated in difference. Unless there are two thermocouples with a
Table 8. big temperature differential between them, thermocouple
voltages should be much less than 200 mV.
Table 8. TEMPERATURE DATA FORMAT
 Place a 0.1 mF bypass capacitor close to the ADM1026.
Temperature Digital Output Hex
 If the distance to the remote sensor is more than eight
−128C 1000 0000 80 inches, the use of twisted-pair cable is recommended.
−125C 1000 0011 83 This works from about 6 to 12 feet.
−100C 1001 1100 9C  For very long distances (up to 100 feet), use shielded
−75C 1011 0101 B5 twisted pair such as Belden #8451 microphone cable.
−50C 1100 1110 CE Connect the twisted pair to D+ and D− and the shield to
−25C 1110 0111 E7 GND close to the ADM1026. Leave the remote end of
−10C 1111 0110 F6 the shield unconnected to avoid ground loops.
0C 0000 0000 00 Because the measurement technique uses switched
10C 0000 1010 0A current sources, excessive cable and/or filter capacitance
25C 0001 1001 19 can affect the measurement. When using long cables, the
50C 0011 0010 32
filter capacitor may be reduced or removed. Cable resistance
can also introduce errors. A 1 W series resistance introduces
75C 0100 1011 4B
about 0.5C error.
100C 0110 0100 64
125C 0111 1101 7D Limit Values
Limit values for analog measurements are stored in the
127C 0111 1111 7F
appropriate limit registers. In the case of voltage
Layout Considerations measurements, high and low limits can be stored so that an
Digital boards can be electrically noisy environments. interrupt request is generated if the measured value goes
Take these precautions to protect the analog inputs from above or below acceptable values. In the case of
noise, particularly when measuring the very small voltages temperature, a hot temperature or high limit can be
from a remote diode sensor. programmed, and a hot temperature hysteresis or low limit
can be programmed, which is usually some degrees lower.
 Place the ADM1026 as close as possible to the remote
This can be useful because it allows the system to be shut
sensing diode. Provided that the worst noise sources
down when the hot limit is exceeded, and restarted
such as clock generators, data/address buses, and CRTs
automatically when it has cooled down to a safe
are avoided, this distance can be 4 to 8 inches.
temperature.
 Route the D+ and D− tracks close together, in parallel,
with grounded guard tracks on each side. Provide a Analog Monitoring Cycle Time
ground plane under the tracks if possible. The analog monitoring cycle begins when a 1 is written to
the start bit (Bit 0), and a 0 to the INT_Clear bit (Bit 2) of the
 Use wide tracks to minimize inductance and reduce noise
configuration register. INT_Enable (Bit 1) should be set to
pickup. A 10 mil track minimum width and spacing is
1 to enable the INT output. The ADC measures each analog
recommended.
input in turn, starting with Remote Temperature Channel 1
GND 10MIL and ending with local temperature. As each measurement is
10MIL
completed, the result is automatically stored in the
appropriate value register. This round-robin monitoring
D+ 10MIL
cycle continues until it is disabled by writing a 0 to Bit 0 of
10MIL
the configuration register. Because the ADC is typically left
D– 10MIL to free-run in this way, the most recently measured value of
10MIL any input can be read out at any time.
GND 10MIL For applications where the monitoring cycle time is
important, it can easily be calculated.
Figure 34. Arrangement of Signal Tracks The total number of channels measured is:
 Try to minimize the number of copper/solder joints,  Five Dedicated Supply Voltage Inputs
which can cause thermocouple effects. Where copper/  Ten General-purpose Analog Inputs
solder joints are used, make sure that they are in both  3.3 V MAIN
the D+ and D− paths and are at the same temperature.  3.3 V STBY
 Thermocouple effects should not be a major problem  Local Temperature
because 1C corresponds to about 240 mV, and  Two Remote Temperature

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ADM1026

Pins 28 and 27 are measured both as analog inputs  To amplify the 2.5 V range of the analog output up to
AIN8/AIN9 and as remote temperature input D2+/D2−, 12 V, the gain of these circuits needs to be about 4.8.
irrespective of which configuration is selected for these pins.  Take care when choosing the op amp to ensure that its
If Pins 28 and 27 are configured as AIN8/AIN9, the input common-mode range and output voltage swing
measurements for these channels are stored in Registers 27h are suitable.
and 29h, and the invalid temperature measurement is
discarded. On the other hand, if Pins 28 and 27 are configured
 The op amp may be powered from the +12 V rail alone
or from 12 V. If it is powered from +12 V, the input
as D2+/D2−, the temperature measurement is stored in
Register 29h, and there is no valid result in Register 27h. common-mode range should include ground to
As mentioned previously, the ADC performs a conversion accommodate the minimum output voltage of the DAC,
every 711 ms on the analog and local temperature inputs and and the output voltage should swing below 0.6 V to
every 2.13 ms on the remote temperature inputs. Each input ensure that the transistor can be turned fully off.
is measured 16 times and averaged to reduce noise.  If the op amp is powered from −12 V, precautions such
The total monitoring cycle time for voltage and as a clamp diode to ground may be needed to prevent
temperature inputs is therefore nominally: the base-emitter junction of the output transistor being
reverse-biased in the unlikely event that the output of
(18 16 0.711) ) (2 16 2.13) + 273 ms (eq. 11)
the op amp should swing negative for any reason.
The ADC uses the internal 22.5 kHz clock, which has a  In all these circuits, the output transistor must have an
tolerance of 6%, so the worst-case monitoring cycle time ICMAX greater than the maximum fan current, and be
is 290 ms. The fan speed measurement uses a completely capable of dissipating power due to the voltage dropped
separate monitoring loop, as described later. across it when the fan is not operating at full speed.
Input Safety  If the fan motor produces a large back EMF when
Scaling of the analog inputs is performed on-chip, so switched off, it may be necessary to add clamp diodes
external attenuators are typically not required. However, to protect the output transistors in the event that the
because the power supply voltages appear directly at the output goes from full scale to zero very quickly.
pins, it is advisable to add small external resistors (that is, 12 V
500 W) in series with the supply traces to the chip to prevent 1/4
LM324
damaging the traces or power supplies should an accidental
DAC
short such as a probe connect two power supplies together. Q1
2N2219A
Because the resistors form part of the input attenuators,
they affect the accuracy of the analog measurement if their
value is too high. The worst such accident would be
connecting −12 V to +12 V where there is a total of 24 V
difference. With the series resistors, this would draw a
maximum current of approximately 24 mA. R1
10k

Analog Output
The ADM1026 has a single analog output from an
unsigned 8-bit DAC that produces 0 V to 2.5 V Figure 35. Fan Drive Circuit with Op Amp and
(independent of the reference voltage setting). The input Emitter-follower
data for this DAC is contained in the DAC control register 12 V
(Address 04h). The DAC control register defaults to FFh
R4
during a power-on reset, which produces maximum fan 1/4
LM324 1kW
speed. The analog output may be amplified and buffered DAC Q1
with external circuitry such as an op amp and a transistor to BD136
R3 2SA968
provide fan speed control. During automatic fan speed 1kW
control, described later, the four MSBs of this register set the
minimum fan speed. R2
39kW
Suitable fan drive circuits are shown in Figure 35 through
Figure 39. When using any of these circuits, note the
following: R1
10k
 All of these circuits provide an output range from 0 V
to almost +12 V, apart from Figure 35, which loses the
base-emitter voltage drop of Q1 due to the Figure 36. Fan Drive Circuit with Op Amp and PNP
emitter-follower configuration. Transistor

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ADM1026

12 V described below, the four MSBs of this register set the


minimum fan speed.
1/4 R3 The open drain PWM output must be amplified and
100kW
LM324
buffered to drive the fans. The PWM output is intended to
DAC
Q1 be used with an NMOS driver, but may be inverted by setting
IRF9620
Bit 1 of Test Register 1 (Address 14h) if using PMOS
drivers. Figure 40 shows how a fan may be driven under
R2
PWM control using an N-channel MOSFET.
39kW
+V

R1
10k 3.3 V 5.0 V OR 12 V
FAN

10k TYP
Figure 37. Fan Drive Circuit with Op Amp and
P-channel MOSFET PWM
Q1
NDT3055L

12 V
R2 R2
100kW 100kW Figure 40. PWM Fan Drive Circuit Using an
Q3
IRF9620
N-channel MOSFET

Automatic Fan Speed Control


The ADM1026 offers a simple method of controlling fan
speed according to temperature without intervention from
R3
39k the host processor. Monitoring must be enabled by setting
Q1/Q2
MBT3904 Bit 0 of Configuration Register 1 (Address 00h), to enable
DAC DUAL R4
10k
automatic fan speed control. Automatic fan speed control
can be applied to the DAC output, the PWM output, or both,
by setting Bit 5 and/or Bit 6 of Configuration Register 1.
The TMIN registers (Addresses 10h to 12h) contain
Figure 38. Discrete Fan Drive Circuit with P-channel
MOSFET, Single Supply minimum temperature values for the three temperature
channels (on-chip sensor and two remote diodes). This is the
temperature at which a fan starts to operate when the
+12 V temperature sensed by the controlling sensor exceeds TMIN.
R2
100kW TMIN can be the same or different for all three channels.
Q3 TMIN is set by writing a twos complement temperature value
IRF9620
to the TMIN registers. If any sensor channel is not required
for automatic fan speed control, TMIN for that channel
should be set to 127C (01111111).
In automatic fan speed control mode, (as shown Figure 41
R3
39k and Figure 42) the four MSBs of the DAC control register
Q1/Q2
DAC MBT3904 (Address 04h) and PWM control register (Address 05h) set
DUAL R4
10k
the minimum values for the DAC and PWM outputs. Note
that, if both DAC control and PWM control are enabled
R1
4.7k
(Bits 5 and 6 of Configuration Register 1 = 1), the four MSBs
of the DAC control register (Address 04h) define the
–12 V
minimum fan speed values for both the DAC and PWM
Figure 39. Discrete Fan Drive Circuit with P-channel outputs. The value in the PWM control register (Address 05h)
MOSFET, Dual Supply has no effect.
Minimum DAC Code DACMIN = 16  D
PWM Output Code
Fan speed may also be controlled using pulse width DAC Output Voltage + 2.5 (eq. 12)
256
modulation (PWM). The PWM output (Pin 18) produces a Minimum PWM Duty Cycle PWMMIN = 6.67  D
pulsed output with a frequency of approximately 75 Hz and where D is the decimal equivalent of Bits 7 to 4 of the
a duty cycle defined by the contents of the PWM control register.
register (Address 05h). During automatic fan speed control,

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ADM1026

When the temperature measured by any of the sensors SPIN UP FOR 2 SECONDS
exceeds the corresponding TMIN, the fan is spun up for 255

2 seconds with the fan drive set to maximum (full scale from 240
the DAC or 100% PWM duty cycle). The fan speed is then
set to the minimum as previously defined. As the DAC
temperature increases, the fan drive increases until the OUTPUT

temperature reaches TMIN + 20C.


The fan drive at any temperature up to 20C above TMIN
is given by: MIN

T ACTUAL * T MIN
PWM + PWM MIN ) ǒ100 * PWM MINǓ
20
(eq. 13)
TMIN - 45C TMIN TMIN + 205C
or TEMPERATURE

T ACTUAL * T MIN Figure 42. Automatic DAC Fan Control Transfer


DAC + DAC MIN ) ǒ240 * DAC MINǓ Function
20

(eq. 14) Fan Inputs


For simplicity of the automatic fan speed algorithm, the Pins 3 to 6 and 9 to 12 may be configured as fan speed
DAC code increases linearly up to 240, not its full scale of measuring inputs by clearing the corresponding bit(s) of
255. However, when the temperature exceeds TMIN +20C, Configuration Register 2 (Address 01h), or as
the DAC output jumps to full scale. To ensure that the general-purpose logic inputs/outputs by setting bits in this
maximum cooling capacity is always available, the fan drive register. The power-on default value for this register is 00h,
is always set by the sensor channel demanding the highest which means all the inputs are set for fan speed
fan speed. measurement.
If the temperature falls, the fan does not turn off until the Signal conditioning in the ADM1026 accommodates the
temperature measured by all three temperature sensors has slow rise and fall times typical of fan tachometer outputs.
fallen to their corresponding TMIN − 4C. This prevents the The fan tach inputs have internal 10 kW pullup resistors to
fan from cycling on and off continuously when the 3.3 V STBY. In the event that these inputs are supplied from
temperature is close to TMIN. fan outputs that exceed the supply, either resistive
Whenever a fan starts or stops during automatic fan speed attenuation of the fan signal or diode clamping must be
control, a one-off interrupt is generated at the INT output. included to keep inputs within an acceptable range.
This is described in more detail in the section on the Figure 43 through Figure 47 show circuits for common fan
ADM1026 Interrupt Structure. tach outputs.
If the fan tach output is open-drain or has a resistive pullup
SPIN UP FOR 2 SECONDS
100%
to VCC, then it can be connected directly to the fan input, as
shown in Figure 44.
12 V VCC

PWM
OUTPUT PULLUP
4.7k
TYP FAN(0–7) FAN SPEED
COUNTER

MIN

Figure 43. Fan with Tach Pullup to +VCC

If the fan output has a resistive pullup to +12 V (or other


TMIN ć 45C TMIN TMIN + 205C
TEMPERATURE
voltage greater than 3.3 V STBY), the fan output can be
clamped with a Zener diode, as shown in Figure 46. The
Figure 41. Automatic PWM Fan Control Transfer Zener voltage should be chosen so that it is greater than VIH
Function
but less than 3.3 V STBY, allowing for the voltage tolerance
of the Zener.

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ADM1026

12 V VCC 22.5kHz
CLOCK

PULLUP CONFIGURATION
4.7k REG. 1 BIT 0
TYP FAN(0–7) FAN SPEED
COUNTER 1 2 3 4
FAN0
INPUT
1 2 3 4
* CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x VCC

Figure 44. Fan with Tach Pullup to Voltage > VCC


(e.g. 12 V), Clamped with Zener Diode START OF FAN0 FAN1
MONITORING MEASUREMENT MEASUREMENT
CYCLE PERIOD PERIOD
If the fan has a strong pullup (less than 1 kW) to +12 V, or
a totem pole output, a series resistor can be added to limit the Figure 47. Fan Speed Measurement
Zener current, as shown in Figure 45. Alternatively, a
resistive attenuator may be used, as shown in Figure 47. The monitoring cycle begins when a 1 is written to the
R1 and R2 should be chosen such that: monitor bit (Bit 0 of Configuration Register 1). The
INT_Enable (Bit 1) should be set to 1 to enable the INT
2.0 V t V PULLUP R2 t 3.3 V STBY output.
ǒR PULLUP ) R1 ) R2Ǔ The fan speed counter starts counting as soon as the fan
(eq. 15)
channel has been switched to. If the fan tach count reaches
12 V VCC 0xFF, the fan has failed or is not connected. If a fan is
connected and running, the counter is reset on the second
tach rising edge, and oscillator pulses are actually counted
FAN(0–7) FAN SPEED from the second rising tach edge to the fourth rising edge.
PULLUP TYP
COUNTER The measurement then switches to the next fan channel.
<1 k
Here again, the counter begins counting and is reset on the
second tach rising edge, and oscillator pulses are counted
* CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 x VCC from the second rising edge to the fourth rising edge. This
Figure 45. Fan with Strong Tach Pullup to >VCC or is repeated for the other six fan channels.
Totem Pole Output, Attenuated with R1/R2 Note that fan speed measurement does not occur until
1.8 seconds after the monitor bit has been set. This is to
12 V VCC allow the fans adequate time to spin up. Otherwise, the
ADM1026 could generate false fan failure interrupts.
<1 k During the 1.8 second fan spin-up time, all fan tach registers
R1* FAN(0–7) FAN SPEED read 0x00.
COUNTER
TACH To accommodate fans of different speed and/or different
OUTPUT
numbers of output pulses per revolution, a prescaler
* SEE TEXT
(divisor) of 1, 2, 4, or 8 may be added before the counter.
Figure 46. Fan with Strong Tach Pullup to > VCC or
Divisor values for Fans 0 to 3 are contained in the Fan 0–3
Totem Pole Output, Clamped with Zener and Resistor divisor register (Address 02h) and those for Fans 4 to 7 in the
Fan 4–7 divisor register (Address 03h). The default value
is 2, which gives a count of 153 for a fan running at
Fan Speed Measurement
4400 RPM producing two output pulses per revolution. The
The fan counter does not count the fan tach output pulses
count is calculated by the equation:
directly because the fan speed may be less than 1000 RPM
Count + 22.5 10 60
3
and it would take several seconds to accumulate a (eq. 16)
reasonably large and accurate count. Instead, the period of RPM Divisor
the fan revolution is measured by gating an on-chip For constant-speed fans, fan failure is typically
22.5 kHz oscillator into the input of an 8-bit counter for two considered to have occurred when the speed drops below
periods of the fan tach output, as shown in Figure 47, so the 70% of nominal, corresponding to a count of 219. Full scale
accumulated count is actually proportional to the fan tach (255) is reached if the fan speed fell to 60% of its nominal
period and inversely proportional to the fan speed. value. For temperature-controlled, variable-speed fans, the
situation is different.

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ADM1026

Table 9 shows the relationship between fan speed and time initialization or before the fourth tach pulse during
per revolution at 60%, 70%, and 100% of nominal RPM for measurement, the measurement is terminated. This also
fan speeds of 1100, 2200, 4400, and 8800 RPM, and the occurs if an input is configured as GPIO instead of fan. Any
divisor that would be used for each of these fans, based on channels connected in this manner time out after 255 clock
two tach pulses per revolution. pulses.
The worst-case measurement time for a fan−configured
Limit Values
channel occurs when the counter reaches 254 from start to
Fans generally do not over-speed if run from the correct
the second tach pulse and reaches 255 after the second tach
voltage, so the failure condition of interest is under speed
pulse. Taking into account the tolerance of the oscillator
due to electrical or mechanical failure. For this reason, only
frequency, the worst-case measurement time is:
low speed limits are programmed into the limit registers for
the fans. It should be noted that because fan period rather 509 D 0.05 ms (eq. 17)
than speed is being measured, a fan failure interrupt occurs where:
when the measurement exceeds the limit value. 509 is the total number of clock pulses.
D is the divisor: 1, 2, 4, or 8.
Fan Monitoring Cycle Time
0.05 ms is the worst-case oscillator period in ms.
The fan speeds are measured in sequence from 0 to 7. The
monitoring cycle time depends on the fan speed, the number The worst-case fan monitoring cycle time is the sum of the
of tach output pulses per revolution, and the number of fans worst-case measurement time for each fan.
being monitored. Although the fan monitoring cycle and the analog input
If a fan is stopped or running so slowly that the fan speed monitoring cycle are started together, they are not
counter reaches 255 before the second tach pulse after synchronized in any other way.

Table 9. FAN SPEEDS AND DIVISORS


Time Per
Divisor RPM Nominal Rev RPM (ms) 70% RPM Rev 70% (ms) 60% RPM Rev 60% (ms)
1 8800 6.82 6160 9.74 5280 11.36
2 4400 13.64 3080 19.48 2640 22.73
4 2200 27.27 1540 38.96 1320 45.45
8 1100 54.54 770 77.92 660 90.9

Chassis Intrusion Input The chassis intrusion input can also be used for other types
The chassis intrusion input is an active high input intended of alarm input. Figure 48 shows a temperature alarm circuit
for detection and signaling of unauthorized tampering with using an AD22105 temperature switch sensor. This
the system. When this input goes high, the event is latched produces a low-going output when the preset temperature is
in Bit 6 of Status Register 4, and an interrupt is generated. exceeded, so the output is inverted by Q1 to make it
The bit remains set until cleared by writing a 1 to CI clear, compatible with the CI input. Q1 can be almost any
Bit 1 of Configuration Register 3 (05h), as long as battery small-signal NPN transistor, or a TTL or CMOS inverter
voltage is connected to the VBAT input. The CI clear bit itself gate may be used if one is available.
is cleared by writing a 0 to it. VCC
The CI input detects chassis intrusion events even when 6 7
R1
10k CI
the ADM1026 is powered off (provided battery voltage is RSET
AD22105
TEMPERATURE
18

applied to VBAT) but does not immediately generate an SENSOR


1 Q1
interrupt. Once a chassis intrusion event is detected and
latched, an interrupt is generated when the system is
3 2
powered on.
The actual detection of chassis intrusion is performed by
an external circuit that detects, for example, when the cover Figure 48. Using the CI Input with a Temperature Sensor
has been removed. A wide variety of techniques may be used
for the detection, for example: General-Purpose I/O Pins (Open Drain)
 A Microswitch that Opens or Closes when the Cover is The ADM1026 has eight pins that are dedicated to
Removed general-purpose logic input/output (Pins 1, 2, and 43 to 48),
 A Reed Switch Operated by Magnet Fixed to the Cover eight pins that can be configured as general-purpose logic
 A Hall-effect Switch Operated by Magnet Fixed to the pins or fan speed inputs (Pins 3 to 6, and 9 to 12), and one
Cover pin that can be configured as GPIO16 or the bidirectional
THERM pin (Pin 42). The GPIO/FAN pins are configured
 A Phototransistor that Detects Light when the Cover is
as general-purpose logic pins by setting Bits 0 to 7 of
Removed

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ADM1026

Configuration Register 2 (Address 01h). Pin 42 is Analog/Temperature Inputs


configured as GPIO16 by setting Bit 0 of Configuration As each analog measurement value is obtained and stored
Register 3, or as the THERM function by clearing this bit. in the appropriate value register, the value and the limits
Each GPIO pin has four data bits associated with it, two from the corresponding limit registers are fed to the high and
bits in one of the GPIO configuration registers (Addresses low limit comparators. The device performs greater than
08h to 0Bh), one in the GPIO status registers (Addresses 24h comparisons to the high limits. An out-of-limit is also
and 25h), and one in the GPIO mask registers (Addresses generated if a result is less than or equal to a low limit. The
1Ch and 1Dh) result of each comparison (1 = out of limit, 0 = in limit) is
Setting a direction bit = 1 in one of the GPIO configuration routed to the corresponding bit input of Interrupt Status
registers makes the corresponding GPIO pin an output. Register 1, 2, or 4 via a data de-multiplexer, and used to set
Clearing the direction bit to 0 makes it an input. that bit high or low as appropriate. Status bits are
Setting a polarity bit = 1 in one of the GPIO configuration self-clearing. If a bit in a status register is set due to an
registers makes the corresponding GPIO pin active high. out-of-limit measurement, it continues to cause INT to be
Clearing the polarity bit to 0 makes it active low. asserted as long as it remains set, as described later.
When a GPIO pin is configured as an input, the However, if a subsequent measurement is in limit, it is reset
corresponding bit in one of the GPIO status registers is and does not cause INT to be reasserted. Status bits are
read-only, and is set when the input is asserted (“asserted” may unaffected by clearing the interrupt.
be high or low depending on the setting of the polarity bit). Interrupt Mask Registers 1, 2, and 4 have bits
When a GPIO pin is configured as an output, the corresponding to each of the interrupt status register bits.
corresponding bit in one of the GPIO status registers Setting an interrupt mask bit high conceals an asserted status
becomes read/write. Setting this bit then asserts the GPIO bit from display on Interrupt Pin 17. Setting an interrupt
output. (Here again, “asserted” may be high or low mask bit low allows the corresponding status bit to be
depending on the setting of the polarity bit.) asserted and displayed on Pin 17. After mask gating, the
The effect of a GPIO status register bit on the INT output status bits are all OR’ed together to produce the analog and
can be masked out by setting the corresponding bit in one of fan interrupt that is used to set a latch. The output of this latch
the GPIO mask registers. When the pin is configured as an is OR’ed with other interrupt sources to produce the INT
output, this bit is automatically masked to prevent the data output. This pulls low if any unmasked status bit goes high,
written to the status bit from causing an interrupt, with the that is, when any measured value goes out of limit.
exception of GPIO16, which must be masked manually by When an INT output caused by an out-of-limit analog/
setting Bit 7 of Mask Register 4 (Reg 1Bh). temperature measurement is cleared by one of the methods
When configured as inputs, the GPIO pins may be described later, the latch is reset. It is not set again, and INT
connected to external interrupt sources such as temperature is not reasserted until after two local temperature
sensors with digital output. Another application of the GPIO measurements have been taken, even if the status bit remains
pins would be to monitor a processor’s voltage ID code (VID set or a new analog/temperature event occurs, as shown in
code). Figure 49. This delay corresponds to almost two monitoring
cycles, and is about 530 ms. However, interrupts from other
ADM1026 Interrupt Structure sources such as a fan or GPIO can still occur. This is
The Interrupt Structure of the ADM1026 is shown in illustrated in Figure 50.
Figure 52. Interrupts can come from a number of sources,
which are combined to form a common INT output. When
INT is asserted, this output pulls low. The INT pin has an
internal, 100 kW pullup resistor.

START OF ANALOG LOCAL LOCAL START OF ANALOG


MONITORING OUT-OF-LIMIT TEMPERATURE TEMPERATURE MONITORING
CYCLE MEASUREMENT MEASUREMENT START OF ANALOG MEASUREMENT CYCLE
MONITORING
CYCLE OUT-OF-LIMIT
MEASUREMENT
INT CLEARED

INT
INT RE−ASSERTED

FULL MONITORING CYCLE = 273ms

Figure 49. Delay After Clearing INT Before Reassertion

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ADM1026

START OF ANALOG OUT-OF-LIMIT LOCAL TEMPEREATURE START OF ANALOG LOCAL TEMPERATURE START OF ANALOG
MONITORING CYCLE MEASUREMENT MEASUREMENT MONITORING CYCLE MEASUREMENT MONITORING CYCLE

INT INT
CLEARED CLEARED GPIO DE−ASSERTED

INT INT RE−ASSERTED

NEW INT NEW INT


FROM FAN FROM GPIO

Figure 50. Other Interrupt Sources Can Reassert INT Immediately

Status Register 4 also stores inputs from two other Registers 5 and 6, or Bit 7 of Status Register 4 (GPIO16). A
interrupt sources that operate in a different way from the chassis intrusion event sets Bit 6 of Status Register 4.
other status bits. If automatic fan speed control (AFC) is The GPIO and CI status bits, after mask gating, are OR’ed
enabled, Bit 4 of Status Register 4 is set whenever a fan starts together and OR’ed with other interrupt sources to produce
or stops. This bit causes a one-off INT output as shown in the INT output. GPIO and CI interrupts are not latched and
Figure 51. It is cleared during the next monitoring cycle and cannot be cleared by normal interrupt clearing. They can
if INT has been cleared, it does not cause INT to be only be cleared by masking the status bits or by removing the
reasserted. source of the interrupt.
FAN ON
Enabling and Clearing Interrupts
FAN OFF
The INT output is enabled when Bit 1 of Configuration
INT Register 1 (INT_Enable) is high, and Bit 2 (INT_Clear) is
low. INT may be cleared if:
INT CLEARED BY STATUS REGULAR 1 READ, BIT 2  Status Register 1 is read. Ideally, if polling the status
OF CONFIGURATION REGULAR 1 SET, OR ARA
registers trying to identify interrupt sources, Status
Figure 51. Assertion of INT Due to AFC Event Register 1 should be polled last, because a read of Status
In a similar way, a change of state at the THERM output Register 1 clears all the other interrupt status registers.
(described in more detail later), sets Bit 3 of Status  The ADM1026 receives the alert response address
Register 4 and causes a one-off INT output. A change of (ARA) (0001 100) over the SMBus.
state at the THERM output also causes Bit 0 of Status  Bit 2 of Configuration Register 1 is set.
Register 1, Bit 1 of Status Register 1, or Bit 0 of Status
Register 4 to be set, depending on which temperature Bidirectional THERM Pin
channel caused the THERM event. This bit is reset during The ADM1026 has a second interrupt pin (GPIO16/
the next monitoring cycle, provided the temperature channel THERM Pin 42) that responds only to critical thermal
is within the normal high and low limits. events. The THERM pin goes low whenever a THERM limit
is exceeded. This function is useful for CPU throttling or
Fan Inputs system shutdown. In addition, whenever THERM is
Fan inputs generate interrupts in a similar way to activated, the PWM and DAC outputs go full scale to
analog/temperature inputs, but as the analog/temperature provide fail-safe system cooling. This output is enabled by
inputs and fan inputs have different monitoring cycles, they setting Bit 4 of Configuration Register 1 (Register 00h).
have separate interrupt circuits. As the speed of each fan is Whenever a THERM limit is exceeded, Bit 3 of Status
measured, the output of the fan speed counter is stored in a Register 4 (Reg 23h) is set, even if the THERM function is
value register. The result is compared to the fan speed limit disabled (Bit 4 of Configuration Register 1 = 0). In this case,
and is used to set or clear a bit in Status Register 3. In this the THERM status bit is set, but the PWM and DAC outputs
case, the fan is monitored only for underspeed (fan counter are not forced to full scale.
> fan speed limit). Mask Register 3 is used to mask fan Three thermal limit registers are provided for the three
interrupts. After mask gating, the fan status bits are OR’ed temperature sensors at Addresses 0Dh to 0Fh. These registers
together and used to set a latch, whose output is OR’ed with are dedicated to the THERM function and none of the other
other interrupt sources to produce the INT output. limit registers have any effect on the THERM output.
Like the analog/temp interrupt, an INT output caused by an If any of the temperature measurements exceed the
out−of−limit fan speed measurement, once cleared, is not corresponding limit, THERM is asserted (low) and the DAC
reasserted until the end of the next monitoring cycle, although and PWM outputs go to maximum to drive any cooling fans
other interrupt sources may cause INT to be asserted. to full speed.
GPIO and CI Pins. When GPIO pins are configured as To avoid cooling fans cycling on and off continually when
inputs, asserting a GPIO input (high or low, depending on the temperature is close to the limit, a fixed hysteresis of 5C
polarity) sets the corresponding GPIO status bit in Status

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ADM1026

is provided. THERM is only deasserted when the measured if INT is subsequently cleared by one of the methods
temperature of all three sensors is 5C below the limit. previously described, it is not reasserted, even if THERM
Whenever the THERM output changes, INT is asserted, remains asserted. THERM causes INT to be reasserted only
as shown in Figure 53. However, this is edge-triggered, so when it changes state.

EXT1 TEMP
0 MASK GATING
EXT 2 TEMP
1
3.3V STBY
2

REGISTER
3.3V MAIN STATUS

STATUS
3
+5V BIT

1
4
VCCP
5
+12V
6
–12V
7 MASK
BIT
MASK DATA FROM
MASK
SMBus (SAME BIT
REGISTER
FROM ANALOG/TEMP NAMES AND ORDER
1
VALUE AND LIMIT AS STATUS BITS)
REGISTERS
AIN0
0 MASK GATING
HIGH LIMIT AIN1
DEMULTIPLEXER

1
COMPARATORS

AIN2
1 = OUT
LOW LIMIT

2
HIGH AND

AIN3 STATUS

REGISTER
OF LIMIT
DATA

STATUS
3 BIT
VALUE AIN4

2
4
AIN5
5 IN OUT
AIN6
LOW LIMIT 6
AIN7 LATCH
7 MASK
BIT
MASK DATA FROM RESET
SMBus (SAME BIT MASK
NAMES AND ORDER REGISTER
AS STATUS BITS) 2

INT TEMP
VBAT 0 MASK GATING
AIN8 1
2
THERM
REGISTER

STATUS
STATUS

3 BIT
AFC
4

4
RESERVED
5
CI
6
GPIO16
7 MASK
BIT
MASK DATA FROM
MASK CI
SMBus (SAME BIT
REGISTER
NAMES AND ORDER GPIO16
4
AS STATUS BITS)

FAN0
0 MASK GATING
FAN1
VALUE
DEMULTIPLEXER

1
COMPARATOR

1 = OUT FAN2
HIGH LIMIT

2
REGISTER

FROM FAN SPEED OF LIMIT FAN3 STATUS


STATUS
DATA

VALUE AND 3 BIT


FAN4
3

LIMIT REGISTERS 4
FAN5
5 IN OUT INT
FAN6
HIGH LIMIT 6
FAN7 LATCH
7 MASK
BIT
MASK DATA FROM RESET
MASK
SMBus (SAME BIT INT ENABLE
REGISTER
NAMES AND ORDER
AS STATUS BITS) 3

MASK GATING INT CLEAR


GPIO0 TO GPIO7 STATUS REGISTER 5 STATUS
BIT

MASKING DATA MASK


MASK REGISTER 5
FROM SMBus BIT

MASK GATING
GPIO8 TO GPIO15 STATUS REGISTER 6 STATUS
BIT

MASKING DATA MASK


MASK REGISTER 6 BIT
FROM SMBus

Figure 52. Interrupt Structure

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ADM1026

Note that the THERM pin is bidirectional, so THERM NAND Tree Tests
may be pulled low externally as an input. This causes the A NAND tree is provided in the ADM1026 for automated
PWM and DAC outputs to go to full scale until THERM is test equipment (ATE) board-level connectivity testing. This
returned high again. To disable THERM as an input, set Bit 0 allows the functionality of all digital inputs to be tested in a
of Configuration Register 3 (Reg. 07h). This configures simple manner and any pins that are nonfunctional or
Pin 42 as GPIO16 and prevents a low on Pin 42 from driving shorted together to be identified. The structure of the NAND
the fans at full speed. tree is shown in Figure 55. The device is placed into NAND
TEMPERATURE tree test mode by powering up with Pin 25 held high. This
THERM LIMIT pin is sampled automatically after powerup, and if it is
THERM LIMIT - 55C connected high, then the NAND test mode is invoked.
GPIO8

THERM GPIO9
FAN0

GPIO10
INT FAN1

GPIO11
FAN2

INT CLEARED BY STATUS REG 1 READ, GPIO12


INT
BIT 2 OF CONFIG. REG. 1 SET, OR ARA FAN3

Figure 53. Assertion of INT Due to THERM Event CI GPIO13


FAN4
Reset Input and Outputs SDA GPIO14
The ADM1026 has two active low, power-on reset FAN5

outputs, RESETMAIN and RESETSTBY. These operate as SCL GPIO15


FAN6
follows.
RESETSTBY monitors 3.3 V STBY. At powerup, FAN7 GPIO16 NTESTOUT
RESETSTBY is asserted (pulled low) until 180 ms after
3.3 V STBY rises above the reset threshold. Figure 55. NAND Tree
RESETMAIN monitors 3.3 V MAIN. This means that at The NAND tree test may be carried out in one of two
powerup, RESETMAIN is asserted (pulled low) until ways.
180 ms after 3.3 V MAIN rises above the reset threshold. 1. Start with all inputs low and take them high in
If 3.3 V MAIN rises with or before DVCC, RESETMAIN turn, starting with the input nearest to
remains asserted until 180 ms after RESETSTBY is NTEST_OUT (GPIO16/ THERM) and working
negated. RESETMAIN can also function as a RESET input. back up the tree to the input furthest from
Pulling this pin low resets the registers, which are initialized NTESTOUT (INT). This should give the
to their default values by a software reset. (See the Software characteristic output pattern shown in Figure 56,
Reset Function section for register details). with NTESTOUT toggling each time an input is
Note that the 3.3 V STBY pin supplies power to the taken high.
ADM1026. In applications that do not require monitoring of 2. Start with all inputs high and take them low in
a 3.3 V STBY and 3.3 V MAIN supply, these two pins should turn, starting with the input furthest from
be connected together (3.3 V MAIN should not be left NTEST_OUT (INT) and working down the tree to
floating). the input nearest to NTEST_OUT
To ensure that the 3.3 V STBY pin does not become back (GPIO16/THERM). This should give a similar
driven, the 3.3 V STBY supply should power on before all output pattern to Figure 57.
other voltages in the system.
See Table 5 for more information about pin configuration.
3.3VSTBY
~1.0 V

3.3VMAIN ~1.0 V

RESETSTBY

RESETMAIN
180ms 180ms
POWER−ON RESET
Figure 54. Operation of Offset Outputs

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ADM1026

Notes: INT

 For a NAND tree test to work, all outputs (INT, CI

RSTMAIN, RSTSTBY, and PWM) must remain high SDA

during the test. SCL

 When generating test waveforms, allow for a typical FAN7

propagation delay of 500 ns through the NAND tree. FAN6

 If any of the inputs shown in Figure 55 are unused, they FAN5

should not be connected direct to ground, but via a FAN4


resistor such as 10 kW. This allows the automatic test FAN3
equipment (ATE) to drive every input high so that the FAN2
NAND tree test can be properly carried out.
FAN1

GPIO16 FAN0

GPIO15 GPIO8

GPIO14 GPIO9

GPIO13 GPIO10
GPIO12
GPIO11
GPIO11
GPIO12
GPIO10
GPIO13
GPIO9
GPIO14
GPIO8
GPIO15
FAN0
GPIO16
FAN1
NTESTOUT
FAN2

FAN3 Figure 57. NAND Tree Test Taking Inputs Low in Turn
FAN4

FAN5
GPIO16
FAN6
GPIO15
FAN7
GPIO14
SCL
GPIO13
SDA
GPIO12
CI
GPIO11
INT
GPIO10

GPIO9
NTESTOUT
GPIO8

FAN0

Figure 56. NAND Tree Test Taking Inputs High in Turn FAN1

NTESTOUT
In the event of an input being nonfunctional (stuck high or
low) or two inputs shorted together, the output pattern is Figure 58. NAND Tree Test with GPIO11 Stuck Low
different. Some examples are given in Figure 58 through
Figure 60. Figure 59 shows the effect of one input being stuck high.
Figure 58 shows the effect of one input being stuck low. Taking GPIO12 high should take the output high. However,
The output pattern is normal until the stuck input is reached. the next input up the tree, GPIO11, is already high, so the
Because that input is permanently low, neither it nor any output immediately goes low again, causing a missing pulse
inputs further up the tree can have any effect on the output. in the output pattern.

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ADM1026

GPIO16
 Setting the fan divisors using the fan divisor registers
GPIO15
(Addresses 02h and 03h).
GPIO14
 Configuring the GPIO pins for input/output polarity, using
GPIO13
GPIO Configuration Registers 1 to 4 (Addresses 08h to
GPIO12 0Bh) and Bits 6 and 7 of Configuration Register 3.
GPIO11
 Setting mask bits in Mask Registers 1 to 6 (Addresses
GPIO10 18h to 1Dh) for any inputs that are to be masked out.
GPIO9
 Setting up Configuration Registers 1 and 3, as
GPIO8 described in Table 10 and Table 11.
FAN0

FAN1
Table 10. CONFIGURATION REGISTER 1
NTESTOUT Bit Description

Figure 59. NAND Tree Test with One Input Stuck High 0 Controls the monitoring loop of the ADM1026. Setting
Bit 0 low stops the monitoring loop and puts the
ADM1026 into low power mode and reduces power
A similar effect occurs if two adjacent inputs are shorted consumption. Serial bus communication is still
together. The example in Figure 60 assumes that the current possible with any register in the ADM1026 while in
sink capability of the circuit driving the inputs is low power mode. Setting bit 0 high starts the
monitoring loop.
considerably higher than the source capability, so the inputs
are low if either is low, but high only if both are high. 1 Enables or disables the INT interrupt output. Setting
Bit 1 high enables the INT output, setting Bit 1 low
When GPIO12 goes high the output should go high. But disables the output.
because GPIO12 and GPIO11 are shorted, they both go high
2 Used to clear the INT interrupt output when set high.
together, causing a missing pulse in the output pattern. GPIO pins and interrupt status register contents are
not affected.
GPIO16
3 Configures Pins 27 and 28 as the second external
GPIO15
temperature channel when 0, and as AIN8 and AIN9
GPIO14 when set to 1.
GPIO13 4 Enables the THERM output when set to 1.
GPIO12 5 Enables automatic fan speed control on the DAC
GPIO11
output when set to 1.

GPIO10 6 Enables automatic fan speed control on the PWM


output when set to 1.
GPIO9
7 Performs a soft reset when set to 1.
GPIO8

FAN0
Table 11. CONFIGURATION REGISTER 3
FAN1
Bit Description
NTESTOUT
0 Configures Pin 42 as GPIO when set to 1 or as
Figure 60. NAND Tree Test with Two Inputs Shorted THERM when cleared to 0.
1 Clears the CI latch when set to 1. Thereafter, a 0
Using the ADM1026 must be written to allow subsequent CI detection.
When power is first applied, the ADM1026 performs a
2 Selects VREF as 2.5 V when set to 1 or as 1.82 V
power−on reset on all its registers (not EEPROM), which when cleared to 0.
sets them to default conditions as shown in Table 13. In 3–5 Unused.
particular, note that all GPIO pins are configured as inputs
6, 7 Set up GPIO16 for direction and polarity.
to avoid possible conflicts with circuits trying to drive these
pins. Starting Conversion
The ADM1026 can also be initialized at any time by The monitoring function (analog inputs, temperature, and
writing a 1 to Bit 7 of Configuration Register 1, which sets fan speeds) in the ADM1026 is started by writing to
some registers to their default power−on conditions. This bit Configuration Register 1 and setting Start (Bit 0) high. The
should be cleared by writing a 0 to it. INT_Enable (Bit 1) should be set to 1, and INT Clear (Bit 2)
After power−on, the ADM1026 must be configured to the set to 0 to enable interrupts. The THERM enable bit (Bit 4)
user’s specific requirements. This consists of: should be set to 1 to enable temperature interrupts at the
 Writing values to the limit registers. THERM pin. Apart from initially starting together, the
 Configuring Pins 3 to 6, and 9 to 12 as fan inputs or analog measurements and fan speed measurements proceed
GPIO, using Configuration Register 2 (Address 01h). independently, and are not synchronized in any way.

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ADM1026

Reduced Power Mode Note that the limit registers (0Dh to 12h, 40h to 6Dh) are
The ADM1026 can be placed in a low power mode by not reset by the software reset function. This can be useful
setting Bit 0 of the configuration register to 0. This disables if one needs to reset the part but does not want to reprogram
the internal ADC. all parameters again. Note that a power-on reset initializes
all registers on the ADM1026, including the limit registers.
Software Reset Function
As previously mentioned, the ADM1026 can be reset in Application Schematic
software by setting Bit 7 of Configuration Register 1 Figure 61 shows how the ADM1026 could be used in an
(Reg. 00h) to 1. Configuration Register 1, 00h, should then application that requires system management of a PC or
be manually cleared. Note that the software reset differs server. Several GPIOs are used to read the VID codes of the
from a power-on reset in that only some of the ADM1026 CPU. Up to two CPU temperature measurements can be read
registers are reinitialized to their power-on default values. back. All power supply voltages are monitored in the
The registers that are initialized to their default values by the system. Up to eight fan speeds can be measured, irrespective
software reset are of whether they are controlled by the ADM1026 or
 Configuration Registers (Registers 01h to 0Bh) hardwired to a system supply. The VREF output includes the
 Mask Registers 1 to 6, internal temperature offset, and recommended filtering circuitry.
Status Registers 4, 5, and 6 (Registers 18h to 25h)
 All value registers (Registers 1Fh, 20h to 3Fh)
 External 1 and External 2 Offset Registers (6Eh, 6Fh)

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CPU1_VID4 SYS_THERM
CPU1_VID3
CPU1_VID2
CPU1_VID1
CPU1_VID0

+12V +12V
X1 X2
1 1

41 A
40 A
39 A
38 A
37 A

IN0
IN1
IN2
IN3
IN4

42 THERM

48 GPIO10
47 GPIO11
46 GPIO12
45 GPIO13
44 GPIO14
43 GPIO15
1 GPIO9 AIN5 36
2 2
2 GPIO8 AIN6 35
3 FAN0/GPIO0 AIN7 34
3 3 CPU2_VCCP
4 FAN1/GPIO1 +VCCP 33
FAN FAN +12 VIN 32 CPU1_VCCP
5 FAN2/GPIO2 +12 VIN
–12V IN 31
6 FAN3/GPIO3 –12 VIN
+5 VIN 30
7 3.3VMAIN U1 +5 VIN
+VBAT 29
ADM1026_SKT
+12V +12V 8 DGND
X4 D2+/A IN8 28
X3 9 FAN4/GPIO4 CPU2_THERMDA
1 1
D2–/A IN9 27
10 FAN5/GPIO5 CPU2_THERMDC
D1+ 26 +
CPU1_THERMDA

33
2 2 11 FAN6/GPIO6 B1
D1– 25
FAN7/GPIO7 CPU1_THERMDC
12

3 3
ADM1026

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FAN FAN
4

SCL 13
SDA 14
ADD 15
CI 16
INT 17
PWM 18
RESETSTBY 19
RESETMAIN 20
AGND 21
3.3V STBY 22
DAC 23
VREF 24

3.3V STDY
S1

VREF_OUT
R6
1

Figure 61. ADM1026 Schematic


+12V 10k C1
X5 R1 R2 0.1F
1
2k 2k
0–2.5V_OUT
2 R3 VCC
3.3V_STBY

470k
SCLOCK
3 SDATA
FAN R5 R4
10k 10k

POWER_GOOD

Q1 SMB_ALERT
CPURESET
ADM1026

Registers

Table 12. ADDRESS POINTER REGISTER


Bit Name R/W Description
7–0 Address Pointer W Address of ADM1026 registers. See the following tables for details.

Table 13. LIST OF REGISTERS


Hex Power-on
Name Description
Address Value

00 Configuration 1 00h Configures various operating parameters .


01 Configuration 2 00h Configures Pins 3–6 and 9–12 as fan inputs or GPIO.
02 Fan 0–3 Divisor 55h Sets oscillator frequency for Fan 0–3 speed measurement.
03 Fan 4–7 Divisor 55h Sets oscillator frequency for Fan 4–7 speed measurement.
04 DAC Control FFh Contains value for fan speed DAC (analog fan speed control) or minimum value
for automatic fan speed control.
05 PWM Control FFh Contains value for PWM fan speed control or minimum value for automatic fan
speed control.
06 EEPROM Register 100h For factory use only.
07 Configuration Register 300h Configuration register for THERM, VREF and GPIO16.
08 GPIO Config 1 00h Configures GPIO0 to GPIO3 as input or output and as active high or active low.
09 GPIO Config 2 00h Configures GPIO4 to GPIO7 as input or output and as active high or active low.
0A GPIO Config 3 00h Configures GPIO8 to GPIO11 as input or output and as active high or active low.
0B GPIO Config 4 00h Configures GPIO12 to GPIO15 as input or output and as active high or active low.
0C EEPROM Register 2 00h For factory use only.
0D Int Temp THERM Limit 37h (55C) High limit for THERM interrupt output based on internal temperature
measurement.
0E TDM1 THERM Limit 50h (80C) High limit for THERM interrupt output based on Remote Channel 1 (D1)
temperature measurement.
0F TDM2 THERM Limit 50h (80C) High limit for THERM interrupt output based on Remote Channel 2 (D2)
temperature measurement.
10 Int Temp TMIN 28h (40C) TMIN value for automatic fan speed control based on internal temperature
measurement.
11 TDM1 TMIN 40h (64C) TMIN value for automatic fan speed control based on Remote Channel 1 (D1)
temperature measurement.
12 TDM2 TMIN 40h (64C) TMIN value for automatic fan speed control based on Remote Channel 2 (D2)
temperature measurement.
13 EEPROM Register 3 00h Configures EEPROM for read/write/erase, etc.
14 Test Register 1 00h Manufacturer’s test register.
15 Test Register 2 00h For manufacturer’s use only.
16 Manufacturer’s ID 41h Contains manufacturer’s ID code.
17 Revision 4xh Contains code for major and minor revisions.
18 Mask Register 1 00h Interrupt mask register for temperature and supply voltage faults.
19 Mask Register 2 00h Interrupt mask register for analog input faults.
1A Mask Register 3 00h Interrupt mask register for fan faults.
1B Mask Register 4 00h Interrupt mask register for local temp, VBAT, AIN8, THERM, AFC, CI and GPIO16.
1C Mask Register 5 00h Interrupt mask register for GPIO0 to GPIO7.
1D Mask Register 6 00h Interrupt mask register for GPIO8 to GPIO15.
1E Int Temp Offset 00h Offset register for internal temperature measurement.
1F Int Temp Value 00h Measured temperature from on-chip sensor.
20 Status Register 1 00h Interrupt status register for external temp and supply voltage faults.
21 Status Register 2 00h Interrupt status register for analog input faults.
22 Status Register 3 00h Interrupt status register for fan faults.

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ADM1026

Table 13. LIST OF REGISTERS


Hex Power-on
Name Description
Address Value

23 Status Register 4 00h Interrupt status register for local temp, VBAT, AIN8, THERM, AFC, CI, and GPIO16.
24 Status Register 5 00h Interrupt status register for GPIO0 to GPIO7.
25 Status Register 6 00h Interrupt status register for GPIO8 to GPIO15.
26 VBAT Value 00h Measured value of VBAT.
27 AIN8 Value 00h Measured value of AIN8.
28 TDM1 Value 00h Measured value of remote temperature channel 1 (D1).
29 TDM2/AIN9 Value 00h Measured value of remote temperature channel 2 (D2) or AIN9.
2A 3.3 V STBY Value 00h Measured value of 3.3 V STBY.
2B 3.3 V MAIN Value 00h Measured value of 3.3 V MAIN.
2C +5.0 V Value 00h Measured value of +5.0 V supply.
2D VCCP Value 00h Measured value of processor core voltage.
2E +12 V Value 00h Measured value of +12 V supply.
2F −12 V Value 00h Measured value of -12 V supply.
30 AIN0 Value 00h Measured value of AIN0.
31 AIN1 Value 00h Measured value of AIN1
32 AIN2 Value 00h Measured value of AIN2.
33 AIN3 Value 00h Measured value of AIN3.
34 AIN4 Value 00h Measured value of AIN4.
35 AIN5 Value 00h Measured value of AIN5.
36 AIN6 Value 00h Measured value of AIN6.
37 AIN7 Value 00h Measured value of AIN7.
38 FAN0 Value 00h Measured speed of Fan 0.
39 FAN1 Value 00h Measured speed of Fan 1.
3A FAN2 Value 00h Measured speed of Fan 2.
3B FAN3 Value 00h Measured speed of Fan 3.
3C FAN4 Value 00h Measured speed of Fan 4.
3D FAN5 Value 00h Measured speed of Fan 5.
3E FAN6 Value 00h Measured speed of Fan 6.
3F FAN7 Value 00h Measured speed of Fan 7.
40 TDM1 High Limit 64h (100C) High limit for Remote Temperature Channel 1 (D1) measurement.
41 TDM2/AIN9 High Limit 64h (100C) High limit for Remote Temperature Channel 2 (D2) or AIN9 measurement.
42 3.3 V STBY High Limit FFh High limit for 3.3 V STBY measurement.
43 3.3 V MAIN High Limit FFh High limit for 3.3 V MAIN measurement.
44 +5.0 V High Limit FFh High limit for +5.0 V supply measurement.
45 VCCP High Limit FFh High limit for processor core voltage measurement.
46 +12 V High Limit FFh High limit for +12 V supply measurement.
47 −12 V High Limit FFh High limit for -12 V supply measurement.
48 TDM1 Low Limit 80h Low limit for Remote Temperature Channel 1 (D1) measurement.
49 TDM2/AIN9 Low Limit 80h Low limit for Remote Temperature Channel 2 (D2) or AIN9 measurement.
4A 3.3 V STBY Low Limit 00h Low limit for 3.3 V STBY measurement.
4B 3.3 V MAIN Low Limit 00h Low limit for 3.3 V MAIN measurement.
4C +5.0 V Low Limit 00h Low limit for +5.0 V supply.
4D VCCP Low Limit 00h Low limit for processor core voltage measurement.
4E +12 V Low Limit 00h Low limit for +12 V supply measurement.
4F −12 V Low Limit 00h Low limit for -12 V supply measurement.
50 AIN0 High Limit FFh High limit for AIN0 measurement.
51 AIN1 High Limit FFh High limit for AIN1 measurement.

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ADM1026

Table 13. LIST OF REGISTERS


Hex Power-on
Name Description
Address Value

52 AIN2 High Limit FFh High limit for AIN2 measurement.


53 AIN3 High Limit FFh High limit for AIN3 measurement.
54 AIN4 High Limit FFh High limit for AIN4 measurement.
55 AIN5 High Limit FFh High limit for AIN5 measurement.
56 AIN6 High Limit FFh High limit for AIN6 measurement.
57 AIN7 High Limit FFh High limit for AIN7 measurement.
58 AIN0 Low Limit 00h Low limit for AIN0 measurement.
59 AIN1 Low Limit 00h Low limit for AIN1 measurement.
5A AIN2 Low Limit 00h Low limit for AIN2 measurement.
5B AIN3 Low Limit 00h Low limit for AIN3 measurement.
5C AIN4 Low Limit 00h Low limit for AIN4 measurement.
5D AIN5 Low Limit 00h Low limit for AIN5 measurement.
5E AIN6 Low Limit 00h Low limit for AIN6 measurement.
5F AIN7 Low Limit 00h Low limit for AIN7 measurement.
60 FAN0 High Limit FFh High limit for Fan 0 speed measurement (no low limit).
61 FAN1 High Limit FFh High limit for Fan 1 speed measurement (no low limit).
62 FAN2 High Limit FFh High limit for Fan 2 speed measurement (no low limit).
63 FAN3 High Limit FFh High limit for Fan 3 speed measurement (no low limit).
64 FAN4 High Limit FFh High limit for Fan 4 speed measurement (no low limit).
65 FAN5 High Limit FFh High limit for Fan 5 speed measurement (no low limit).
66 FAN6 High Limit FFh High limit for Fan 6 speed measurement (no low limit).
67 FAN7 High Limit FFh High limit for Fan 7 speed measurement (no low limit).
68 Int. Temp. High Limit 50h (80C) High limit for local temperature measurement.
69 Int. Temp. Low Limit 80h Low limit for local temperature measurement.
6A VBAT High Limit FFh High limit for VBAT measurement.
6B VBAT Low Limit 00h Low limit for VBAT measurement.
6C AIN8 High Limit FFh High limit for AIN8 measurement.
6D AIN8 Low Limit 00h Low limit for AIN8 measurement.
6E Ext1 Temp Offset 00h Offset register for Remote Temperature Channel 1.
6F Ext2 Temp Offset 00h Offset register for Remote Temperature Channel 2.

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ADM1026

Detailed Register Descriptions

Table 14. REGISTER 00H, CONFIGURATION REGISTER 1 (POWER-ON DEFAULT 00H)


Bit Name R/W Description
0 Monitor = 0 R/W When this bit is set the ADM1026 monitors all voltage, temperature and fan
channels in a round robin manner.
1 Int Enable = 0 R/W When this bit is set, the INT output pin is enabled.
2 Int Clear = 0 R/W Setting this bit clears an interrupt from the voltage, temperature or fan speed
channels. Because GPIO interrupts are level triggered, this bit has no effect on
interrupts originating from GPIO channels. This bit is cleared by writing a 0 to it. If
in monitoring mode voltages, temperatures and fan speeds continue to be
monitored after writing to this bit to clear an interrupt, so an interrupt may be set
again on the next monitoring cycle.
3 Enable Voltage/Ext2 = 0 R/W When this bit is 1, the ADM1026 monitors voltage (AIN8 and AIN9) on Pins 28
and 27, respectively. When this bit is 0, the ADM1026 monitors a second thermal
diode temperature channel, D2, on these pins. If the second thermal diode channel
is not being used, it is recommended that the bit be set to 1.
4 Enable THERM = 0 R/W When this bit is 1, the THERM pin (Pin 42) is asserted (go low) if any of the
THERM limits are exceeded. If THERM is pulled low as an input, the DAC and
PWM outputs are forced to full scale until THERM is taken high.
5 Enable DAC AFC = 0 R/W When this bit is 1, the DAC output is enabled for automatic fan speed control
(AFC) based on temperature. When this bit is 0, the DAC Output reflects the value
in Reg 04h, the DAC Control Register.
6 Enable PWM AFC = 0 R/W When this bit is 1, the PWM output is enabled for automatic fan speed control
(AFC) based on temperature. When this bit is 0, the PWM Output reflects the value
in Reg 05h, the PWM Control Register.
7 Software Reset = 0 R/W Writing a 1 to this bit restores all registers to the power-on defaults. This bit is
cleared by writing a 0 to it. For more info, see the Software Reset Function section.

Table 15. REGISTER 01H, CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H)


Bit Name R/W Description
0 Enable GPIO0/Fan0 = 0 R/W When this bit is 1, Pin 3 is enabled as a general−purpose I/O pin (GPIO0),
otherwise it is a fan tach measurement input (Fan 0).
1 Enable GPIO1/Fan1 = 0 R/W When this bit is 1, Pin 4 is enabled as a general−purpose I/O pin (GPIO1),
otherwise it is a fan tach measurement input (Fan 1).
2 Enable GPIO2/Fan2 = 0 R/W When this bit is 1, Pin 5 is enabled as a general−purpose I/O pin (GPIO2),
otherwise it is a fan tach measurement input (Fan 2).
3 Enable GPIO3/Fan3 = 0 R/W When this bit is 1, Pin 6 is enabled as a general−purpose I/O pin (GPIO3),
otherwise it is a fan tach measurement input (Fan 3).
4 Enable GPIO4/Fan4 = 0 R/W When this bit is 1, Pin 9 is enabled as a general−purpose I/O pin (GPIO4),
otherwise it is a fan tach measurement input (Fan 4).
5 Enable GPIO5/Fan5 = 0 R/W When this bit is 1, Pin 10 is enabled as a general−purpose I/O pin (GPIO5),
otherwise it is a fan tach measurement input (Fan 5).
6 Enable GPIO6/Fan6 = 0 R/W When this bit is 1, Pin 11 is enabled as a general−purpose I/O pin (GPIO6),
otherwise it is a fan tach measurement input (Fan 6).
7 Enable GPIO7/Fan7 = 0 R/W When this bit is 1, Pin 12 is enabled as a general−purpose I/O pin (GPIO7),
otherwise it is a fan tach measurement input (Fan 7).

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ADM1026

Table 16. REGISTER 02H, FANS 0 TO 3 FAN DIVISOR REGISTER (POWER-ON DEFAULT 55H)
Bit Name R/W Description
1–0 Fan 0 Divisor R/W Sets the oscillator prescaler division ratio for Fan 0 speed measurement. The
division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach
pulses per revolution) are as follows:
Divide Oscillator
Code Fan Speed (RPM)
By: Frequency (kHz)
00 1 22.5 8800, nominal, for count of 153
01 2 11.25 4400, nominal, for count of 153
10 4 5.62 2200, nominal, for count of 153
11 8 2.81 1100, nominal, for count of 153
3–2 Fan 1 Divisor R/W Same as Fan 0
5–4 Fan 2 Divisor R/W Same as Fan 0
7–6 Fan 3 Divisor R/W Same as Fan 0

Table 17. REGISTER 03H, FANS 4 TO 7 FAN DIVISOR REGISTER (POWER-ON DEFAULT 55H)
Bit Name R/W Description
1–0 Fan 4 Divisor R/W Sets the oscillator prescaler division ratio for Fan 4 speed measurement. The
division ratios, oscillator frequencies, and typical fan speeds (based on 2 tach
pulses per revolution) are as follows:
Oscillator
Code Divide By: Fan Speed (RPM)
Frequency (kHz)
00 1 22.5 8800, nominal, for count of 153
01 2 11.25 4400, nominal, for count of 153
10 4 5.62 2200, nominal, for count of 153
11 8 2.81 1100, nominal, for count of 153
3–2 Fan 5 Divisor R/W Same as Fan 4
5–4 Fan 6 Divisor R/W Same as Fan 4
7–6 Fan 7 Divisor R/W Same as Fan 4

Table 18. REGISTER 04H, DAC CONFIGURATION REGISTER (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 DAC Control R/W This register contains the value to which the fan speed DAC is programmed in
normal mode, or the 4 MSBs contain the minimum fan speed in auto fan speed
control mode.

Table 19. REGISTER 05H, PWM CONTROL REGISTER (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–4 PWM Control R/W This register contains the value to which the PWM fan speed is programmed in
normal mode, or the 4 MSBs contain the minimum fan speed in auto fan speed
control mode.
0000 = 0% Duty Cycle
0001 = 7% Duty Cycle
0101 = 33% Duty Cycle
0110 = 40% Duty Cycle
0111 = 47% Duty Cycle
1110 = 93% Duty Cycle
1111 = 100% Duty Cycle
3–0 Unused R Undefined

Table 20. REGISTER 06H, EEPROM REGISTER 1 (POWER-ON DEFAULT 00H)


Bit Name R/W Description
7–0 Factory Use R/W For factory use only. Do not write to this register.

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ADM1026

Table 21. REGISTER 07H, CONFIGURATION REGISTER 3 (POWER-ON DEFAULT 00H)


Bit Name R/W Description
0 Enable GPIO16/ R/W When this bit is 1, Pin 42 is enabled as a general−purpose I/O pin (GPIO16);
THERM = 0 otherwise it is the THERM output.
1 CI Clear = 0 R/W Writing a 1 to this bit clears the CI latch. This bit is cleared by writing a 0 to it.
2 VREF Select = 0 R/W When this bit is 0, VREF (Pin 24) outputs 1.82 V, otherwise, it outputs 2.5 V.
5–3 Unused R Undefined, reads back 0.
6 GPIO16 Direction R/W When this bit is 0, GPIO16 is configured as an input; otherwise, it is an output.
7 GPIO16 Polarity R/W When this bit is 0, GPIO16 is active low; otherwise, it is active high.

Table 22. REGISTER 08H, GPIO CONFIGURATION REGISTER 1 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO0 Direction R/W When this bit is 0, GPIO0 is configured as an input; otherwise, it is an output.
1 GPIO0 Polarity R/W When this bit is 0, GPIO0 is active low; otherwise it is active high.
2 GPIO1 Direction R/W When this bit is 0, GPIO1 is configured as an input; otherwise, it is an output.
3 GPIO1 Polarity R/W When this bit is 0, GPIO1 is active low; otherwise it is active high.
4 GPIO2 Direction R/W When this bit is 0, GPIO2 is configured as an input; otherwise, it is an output.
5 GPIO2 Polarity R/W When this bit is 0, GPIO2 is active low; otherwise, it is active high.
6 GPIO3 Direction R/W When this bit is 0, GPIO3 is configured as an input; otherwise, it is an output.
7 GPIO3 Polarity R/W When this bit is 0, GPIO3 is active low; otherwise, it is active high.

Table 23. REGISTER 09H, GPIO CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO4 Direction R/W When this bit is 0, GPIO4 is configured as an input; otherwise, it is an output.
1 GPIO4 Polarity R/W When this bit is 0, GPIO4 is active low; otherwise, it is active high.
2 GPIO5 Direction R/W When this bit is 0, GPIO5 is configured as an input; otherwise, it is an output.
3 GPIO5 Polarity R/W When this bit is 0, GPIO5 is active low; otherwise, it is active high.
4 GPIO6 Direction R/W When this bit is 0, GPIO6 is configured as an input; otherwise, it is an output.
5 GPIO6 Polarity R/W When this bit is 0, GPIO6 is active low; otherwise, it is active high.
6 GPIO7 Direction R/W When this bit is 0, GPIO7 is configured as an input; otherwise, it is an output.
7 GPIO7 Polarity R/W When this bit is 0, GPIO7 is active low; otherwise, it is active high.

Table 24. REGISTER 0AH, GPIO CONFIGURATION REGISTER 3 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO8 Direction R/W When this bit is 0, GPIO8 is configured as an input; otherwise, it is an output.
1 GPIO8 Polarity R/W When this bit is 0, GPIO8 is active low; otherwise, it is active high.
2 GPIO9 Direction R/W When this bit is 0, GPIO9 is configured as an input; otherwise, it is an output.
3 GPIO9 Polarity R/W When this bit is 0, GPIO9 is active low; otherwise, it is active high.
4 GPIO10 Direction R/W When this bit is 0, GPIO10 is configured as an input; otherwise, it is an output.
5 GPIO10 Polarity R/W When this bit is 0, GPIO10 is active low; otherwise, it is active high.
6 GPIO11 Direction R/W When this bit is 0, GPIO11 is configured as an input; otherwise, it is an output.
7 GPIO11 Polarity R/W When this bit is 0, GPIO11 is active low; otherwise, it is active high.

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ADM1026

Table 25. REGISTER 0BH, GPIO CONFIGURATION REGISTER 4 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
0 GPIO12 Direction R/W When this bit is 0, GPIO12 is configured as an input; otherwise, it is an output.
1 GPIO12 Polarity R/W When this bit is 0, GPIO12 is active low; otherwise, it is active high.
2 GPIO13 Direction R/W When this bit is 0, GPIO13 is configured as an input; otherwise, it is an output.
3 GPIO13 Polarity R/W When this bit is 0, GPIO13 is active low; otherwise, it is active high.
4 GPIO14 Direction R/W When this bit is 0, GPIO14 is configured as an input; otherwise, it is an output.
5 GPIO14 Polarity R/W When this bit is 0, GPIO14 is active low; otherwise, it is active high.
6 GPIO15 Direction R/W When this bit is 0, GPIO15 is configured as an input; otherwise, it is an output.
7 GPIO15 Polarity R/W When this bit is 0, GPIO15 is active low; otherwise, it is active high.

Table 26. REGISTER 0CH, EEPROM CONFIGURATION REGISTER 2 (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 Factory Use R For factory use only. Do not write to this register.

Table 27. REGISTER 0DH, INTERNAL TEMPERATURE THERM LIMIT (POWER-ON DEFAULT, 37H 555C)
Bit Name R/W Description
7–0 Int Temp THERM Limit R/W This register contains the THERM limit for the internal temperature channel.
Exceeding this limit causes the THERM output pin to be asserted.

Table 28. REGISTER 0EH, TDM1 THERM LIMIT (POWER-ON DEFAULT, 50H 805C)
Bit Name R/W Description
7–0 TDM1 THERM Limit R/W This register contains the THERM limit for the TDM1 temperature channel.
Exceeding this limit causes the THERM output pin to be asserted.

Table 29. REGISTER 0FH, TDM2 THERM LIMIT (POWER-ON DEFAULT, 50H 805C)
Bit Name R/W Description
7–0 TDM2 THERM Limit R/W This register contains the THERM limit for the TDM2 temperature channel.
Exceeding this limit causes the THERM output pin to be asserted.

Table 30. REGISTER 10H, INTERNAL TEMPERATURE TMIN (POWER-ON DEFAULT, 28H 405C)
Bit Name R/W Description
7–0 Internal Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the
internal temperature channel.

Table 31. REGISTER 11H, TDM1 TEMPERATURE TMIN (POWER-ON DEFAULT, 40H 645C)
Bit Name R/W Description
7–0 TDM1 Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the
TDM1 temperature channel.

Table 32. REGISTER 12H, TDM2 TEMPERATURE TMIN (POWER-ON DEFAULT, 40H 645C)
Bit Name R/W Description
7–0 TDM2 Temp TMIN R/W This register contains the TMIN value for automatic fan speed control based on the
TDM2 temperature channel.

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ADM1026

Table 33. REGISTER 13H, EEPROM REGISTER 3 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 Read R/W Setting this bit puts the EEPROM into read mode.
1 Write R/W Setting this bit puts the EEPROM in write (program) mode.
2 Erase R/W Setting this bit puts the EEPROM into erase mode.
3 Write Protect R/W Setting this bit protects the EEPROM against accidental writing or erasure. This bit
Once can write once and only be cleared by a power−on reset.
4 Test Mode Bit 0 R/W Test mode bits. For factory use only
5 Test Mode Bit 1 R/W Test mode bits. For factory use only.
6 Test Mode Bit 2 R/W Test mode bits. For factory use only
7 Clock Extend R/W Setting this bit enables SMBus clock extension. The ADM1026 can pull SCL low to
extend the clock pulse if it cannot accept any more data. It is recommended to set
this bit to 1 to extend the clock pulse during repeated EEPROM write or block write
operations.

Table 34. REGISTER 14H, MANUFACTURER’S TEST REGISTER 1 (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Manufacturer’s Test 1 R/W This register is used by the manufacturer for test purposes. It should not be read
from or written to in normal operation.

Table 35. REGISTER 15H, MANUFACTURER’S TEST REGISTER 2 (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Manufacturer’s Test 2 R/W This register is used by the manufacturer for test purposes. It should not be read
from or written to in normal operation.

Table 36. REGISTER 16H, MANUFACTURER’S ID (POWER-ON DEFAULT, 041H)


Bit Name R/W Description
7–0 Manufacturer ID Code R/W This register contains the manufacturer’s ID code.

Table 37. REGISTER 17H, REVISION REGISTER (POWER-ON DEFAULT, 4XH)


Bit Name R/W Description
3–0 Minor Revision Code R This nibble contains the manufacturer’s code for minor revisions to the device.
Rev 1 = 0h, Rev 2 = 1h, and so on.
7–4 Major Revision Code R This nibble denotes the generation of the device. For the ADM1026, this nibble
reads 4h.

Table 38. REGISTER 18H, MASK REGISTER 1 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 Ext1 Temp Mask = 0 R/W When this bit is set, interrupts generated on the Ext1 temperature channel are
masked out.
1 Ext2 Temp R/W When this bit is set, interrupts generated on the Ext2/AIN9 channel are masked out.
2 3.3 V STBY Mask = 0 R/W When this bit is set, interrupts generated on the 3.3 V STBY voltage channel are
masked out.
3 3.3 V MAIN Mask = 0 R/W When this bit is set, interrupts generated on the 3.3 V MAIN voltage channel are
masked out.
4 +5.0 V Mask = 0 R/W When this bit is set, interrupts generated on the +5.0 V voltage channel are masked
out.
5 VCCP Mask = 0 R/W When this bit is set, interrupts generated on the VCCP voltage channel are masked out.
6 +12 V Mask = 0 R/W When this bit is set, interrupts generated on the +12 V voltage channel are masked out.
7 −12 V Mask = 0 R/W When this bit is set, interrupts generated on the −12 V voltage channel are masked out.

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ADM1026

Table 39. REGISTER 19H, MASK REGISTER 2 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 AIN0 Mask = 0 R/W When this bit is set, interrupts generated on the AIN0 voltage channel are masked out.
1 AIN1 Mask = 0 R/W When this bit is set, interrupts generated on the AIN1 voltage channel are masked out.
2 AIN2 Mask = 0 R/W When this bit is set, interrupts generated on the AIN2 voltage channel are masked out.
3 AIN3 Mask = 0 R/W When this bit is set, interrupts generated on the AIN3 voltage channel are masked out.
4 AIN4 Mask = 0 R/W When this bit is set, interrupts generated on the AIN4 voltage channel are masked out.
5 AIN5 Mask = 0 R/W When this bit is set, interrupts generated on the AIN5 voltage channel are masked out.
6 AIN6 Mask = 0 R/W When this bit is set, interrupts generated on the AIN6 voltage channel are masked out.
7 AIN7 Mask = 0 R/W When this bit is set, interrupts generated on the AIN7 voltage channel are masked out.

Table 40. REGISTER 1AH, MASK REGISTER 3 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 FAN0 Mask = 0 R/W When this bit is set, interrupts generated on the FAN0 tach channel are masked out.
1 FAN1 Mask = 0 R/W When this bit is set, interrupts generated on the FAN1 tach channel are masked out.
2 FAN2 Mask = 0 R/W When this bit is set, interrupts generated on the FAN2 tach channel are masked out.
3 FAN3 Mask = 0 R/W When this bit is set, interrupts generated on the FAN3 tach channel are masked out.
4 FAN4 Mask = 0 R/W When this bit is set, interrupts generated on the FAN4 tach channel are masked out.
5 FAN5 Mask = 0 R/W When this bit is set, interrupts generated on the FAN5 tach channel are masked out.
6 FAN6 Mask = 0 R/W When this bit is set, interrupts generated on the FAN6 tach channel are masked out.
7 FAN7 Mask = 0 R/W When this bit is set, interrupts generated on the FAN7 tach channel are masked out.

Table 41. REGISTER 1BH, MASK REGISTER 4 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 Int Temp Mask = 0 R/W When this bit is set, interrupts generated on the internal temperature channel are
masked out.
1 VBAT Mask = 0 R/W When this bit is set, interrupts generated on the VBAT voltage channel are masked out.
2 AIN8 Mask = 0 R/W When this bit is set, interrupts generated on the AIN8 voltage channel are masked out.
3 THERM Mask = 0 R/W When this bit is set, interrupts generated from THERM events are masked out.
4 AFC Mask = 0 R/W When this bit is set, interrupts generated from automatic fan control events are
masked out.
5 Unused R/W Unused. Reads back 0.
6 CI Mask = 0 R/W When this bit is set, interrupts generated by the chassis intrusion input are masked out.
7 GPIO16 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO16 channel are masked out.

Table 42. REGISTER 1CH, MASK REGISTER 5 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 GPIO0 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO0 channel are masked out.
1 GPIO1 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO1 channel are masked out.
2 GPIO2 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO2 channel are masked out.
3 GPIO3 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO3 channel are masked out.
4 GPIO4 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO4 channel are masked out.
5 GPIO5 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO5 channel are masked out.
6 GPIO6 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO6 channel are masked out.
7 GPIO7 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO7 channel are masked out.

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Table 43. REGISTER 1DH, MASK REGISTER 6 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 GPIO8 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO8 channel are masked out.
1 GPIO9 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO9 channel are masked out.
2 GPIO10 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO10 channel are masked out.
3 GPIO11Mask = 0 R/W When this bit is set, interrupts generated on the GPIO11 channel are masked out.
4 GPIO12 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO12 channel are masked out.
5 GPIO13 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO13 channel are masked out.
6 GPIO14 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO14 channel are masked out.
7 GPIO15 Mask = 0 R/W When this bit is set, interrupts generated on the GPIO15 channel are masked out.

Table 44. REGISTER 1EH, INT TEMP OFFSET (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Int Temp Offset R/W This register contains the offset value for the internal temperature channel, a twos
complement result before it is stored or compared to limits. In this way, a sort of
one-point calibration can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel if the thermal
characteristics change for any reason (for instance from one chassis to another), if
the measurement point is moved, if a plug-in card is inserted or removed, and so on.

Table 45. REGISTER 1FH, INT TEMP MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Int Temp Value R This register contains the measured value of the internal temperature channel.

Table 46. REGISTER 20H, STATUS REGISTER 1 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 Ext1 Temp Status = 0 R 1, if Ext1 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise. This bit is set (once only) if a THERM mode is
engaged as a result of Ext1 temp readings exceeding the Ext1 THERM limit. This bit
is also set (once only) if THERM mode is disengaged as a result of Ext1 temperature
readings going 5C below Ext1 THERM limit.
1 Ext2 Temp Status = 0 R 1, if Ext 2 value (or AIN9 if in voltage measurement mode) is above the /AIN9 status =
0 high limit or below the low limit on the previous conversion cycle; 0 otherwise. This
bit is set (once only) if a THERM mode is engaged as a result of Ext2 temperature
readings exceeding the Ext2 THERM limit. This bit is also set (once only) if THERM
mode is disengaged as a result of Ext2 temperature readings going 5C below Ext2
THERM limit.
2 3.3 V STBY Status = 0 R 1, if 3.3 V STBY value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
3 3.3 V MAIN Status = 0 R 1, if 3.3 V MAIN value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
4 +5.0 V Status = 0 R 1, if +5.0 V value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
5 VCCP Status = 0 R 1, if VCCP value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
6 +12 V Status = 0 R 1, if +12 V value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
7 −12 V Status = 0 R 1, if -12 V value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.

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Table 47. REGISTER 21H, STATUS REGISTER 2 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 AIN0 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
1 AIN1 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
2 AIN2 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
3 AIN3 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
4 AIN4 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
5 AIN5 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
6 AIN6 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.
7 AIN7 Status = 0 R 1, if AIN0 to AIN7 value is above the high limit or below the low limit on the previous
conversion cycle; 0 otherwise.

Table 48. REGISTER 22H, STATUS REGISTER 3 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 FAN0 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
1 FAN1 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
2 FAN2 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
3 FAN3 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
4 FAN4 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
5 FAN5 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
6 FAN6 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.
7 FAN7 Status 1 = 0 R 1, if FAN0 to FAN7 value is above the high limit on the previous conversion cycle;
0 otherwise.

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Table 49. REGISTER 23H, STATUS REGISTER 4 (POWER-ON DEFAULT, 00H)


Bit Name R/W Description
0 INT Temp Status = 0 R 1, if INT value is above the high limit or below the low limit on the previous
conversion cycle, 0 otherwise. This bit is set (once only) if a THERM mode is
engaged as a result of INT temperature readings exceeding the INT THERM limit.
This bit is also set (once only) if THERM mode is disengaged as a result of internal
temperature readings going 5C below Int THERM limit.
1 VBAT Status = 0 R 1, if VBAT value is above the high limit or below the low limit on the previous
conversion cycle, 0 otherwise.
2 AIN8 Status = 0 R 1, if AIN8 value is above the high limit or below the low limit on the previous
conversion cycle, 0 otherwise.
3 THERM Status = 0 R This bit is set (once only) if a THERM mode is engaged as a result of temperature
readings exceeding the THERM limits on any channel. This bit is also set (once
only) if THERM mode is disengaged as a result of temperature readings going 5C
below THERM limits on any channel.
4 AFC Status = 0 R This bit is set (once only) if the fan turns on when in automatic fan speed control (AFC)
mode as a result of a temperature reading exceeding TMIN on any channel. This bit is
also set (once only) if the fan turns off when in automatic fan speed control mode.
5 Unused R Unused. Reads back 0.
6 CI Status = 0 R This bit latches a chassis intrusion event.
7 GPIO16 Status = 0 R When GPIO16 is configured as an input, this bit is set when GPIO16 is asserted.
(Asserted may be active high or active low depending on the setting in GPIO
configuration register.)
R/W When GPIO16 is configured as an output, setting this bit asserts GPIO16. (Asserted
may be active high or active low depending on setting in GPIO configuration register.)

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Table 50. REGISTER 24H, STATUS REGISTER 5 (POWER-ON DEFAULT, 00H)


R/W
Bit Name Description
(Note 1)

0 GPIO0 Status = 0 R When GPIO0 is configured as an input, this bit is set when GPIO0 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 1.)
R/W When GPIO0 is configured as an output, setting this bit asserts GPIO0. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 1.)
1 GPIO1 Status = 0 R When GPIO1 is configured as an input, this bit is set when GPIO1 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
R/W Configuration Register 1.)
When GPIO1 is configured as an output, setting this bit asserts GPIO1. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 1.)
2 GPIO2 Status = 0 R When GPIO2 is configured as an input, this bit is set when GPIO2 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 1.)
R/W When GPIO2 is configured as an output, setting this bit asserts GPIO2. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 1.)
3 GPIO3 Status = 0 R When GPIO3 is configured as an input, this bit is set when GPIO3 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 1.)
R/W When GPIO3 is configured as an output, setting this bit asserts GPIO3. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 1.)
4 GPIO4 Status = 0 R When GPIO4 is configured as an input, this bit is set when GPIO4 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 2.)
R/W When GPIO4 is configured as an output, setting this bit asserts GPIO4. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 2.)
5 GPIO5 Status = 0 R When GPIO5 is configured as an input, this bit is set when GPIO5 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 2.)
R/W When GPIO5 is configured as an output, setting this bit asserts GPIO5. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 2.)
6 GPIO6 Status = 0 R When GPIO6 is configured as an input, this bit is set when GPIO6 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 2.)
R/W When GPIO6 is configured as an output, setting this bit asserts GPIO6. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 2.)
7 GPIO7 Status = 0 R When GPIO7 is configured as an input, this bit is set when GPIO7 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 2.)
R/W When GPIO7 is configured as an output, setting this bit asserts GPIO7. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 2.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.

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Table 51. REGISTER 25H, STATUS REGISTER 6 (POWER-ON DEFAULT, 00H)


R/W
Bit Name Description
(Note 1)

0 GPIO8 Status = 0 R When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 3.)
R/W When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 3.)
1 GPIO9 Status = 0 R When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 3.)
R/W When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 3.)
2 GPIO10 Status = 0 R When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 3.)
R/W When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 3.)
3 GPIO11 Status = 0 R When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 3.)
R/W When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 3.)
4 GPIO12 Status = 0 R When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 4.)
R/W When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 4.)
5 GPIO13 Status = 0 R When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 4.)
R/W When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 4.)
6 GPIO14 Status = 0 R When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 4.)
R/W When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 4.)
7 GPIO15 Status = 0 R When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 4.)
R/W When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 4.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.

Table 52. REGISTER 26H, VBAT MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 VBAT Value R This register contains the measured value of the VBAT analog input channel.

Table 53. REGISTER 27H, AIN8 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN8 Value R This register contains the measured value of the AIN8 analog input channel.

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Table 54. REGISTER 28H, EXT1 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Ext1 Value R This register contains the measured value of the Ext1 Temp channel.

Table 55. REGISTER 29H, EXT2/AIN9 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 Ext2 Temp/ R This register contains the measured value of the Ext2 Temp/AIN9 channel depending
AIN9 Low Limit on which bit is configured.

Table 56. REGISTER 2AH, 3.3 V STBY MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 3.3 V STBY Value R This register contains the measured value of the 3.3 V STBY voltage.

Table 57. REGISTER 2BH, 3.3 V MAIN MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 3.3 V MAIN Value R This register contains the measured value of the 3.3 V MAIN voltage.

Table 58. REGISTER 2CH, +5.0 V MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 +5.0 V Value R This register contains the measured value of the +5.0 V analog input channel.

Table 59. REGISTER 2DH, VCCP MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 VCCP Value R This register contains the measured value of the VCCP analog input channel.

Table 60. REGISTER 2EH, +12 V MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 +12 V Value R This register contains the measured value of the +12 V analog input channel.

Table 61. REGISTER 2FH, −12 V MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 –12 V Value R This register contains the measured value of the -12 V analog input channel.

Table 62. REGISTER 30H, AIN0 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN0 Value R This register contains the measured value of the AIN0 analog input channel.

Table 63. REGISTER 31H, AIN1 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN1 Value R This register contains the measured value of the AIN1 analog input channel.

Table 64. REGISTER 32H, AIN2 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN2 Value R This register contains the measured value of the AIN2 analog input channel.

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Table 65. REGISTER 33H, AIN3 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN3 Value R This register contains the measured value of the AIN3 analog input channel.

Table 66. REGISTER 34H, AIN4 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN4 Value R This register contains the measured value of the AIN4 analog input channel.

Table 67. REGISTER 35H, AIN5 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN5 Value R This register contains the measured value of the AIN5 analog input channel.

Table 68. REGISTER 36H, AIN6 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN6 Value R This register contains the measured value of the AIN6 analog input channel.

Table 69. REGISTER 37H, AIN7 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 AIN7 Value R This register contains the measured value of the AIN7 analog input channel.

Table 70. REGISTER 38H, FAN0 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN0 Value R This register contains the measured value of the FAN0 tach input channel.

Table 71. REGISTER 39H, FAN1 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN1 Value R This register contains the measured value of the FAN1 tach input channel.

Table 72. REGISTER 3AH, FAN2 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN2 Value R This register contains the measured value of the FAN2 tach input channel.

Table 73. REGISTER 3BH, FAN3 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN3 Value R This register contains the measured value of the FAN3 tach input channel.

Table 74. REGISTER 3CH, FAN4 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN4 Value R This register contains the measured value of the FAN4 tach input channel.

Table 75. REGISTER 3DH, FAN5 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN5 Value R This register contains the measured value of the FAN5 tach input channel.

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Table 76. REGISTER 3EH, FAN6 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN6 Value R This register contains the measured value of the FAN6 tach input channel.

Table 77. REGISTER 3FH, FAN7 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit Name R/W Description
7–0 FAN7 Value R This register contains the measured value of the FAN7 tach input channel.

Table 78. REGISTER 40H, EXT1 HIGH LIMIT (POWER-ON DEFAULT 64H/1005C)
Bit Name R/W Description
7–0 Ext1 High Limit R/W This register contains the high limit of the Ext1 Temp channel.

Table 79. REGISTER 41H, EXT2/AIN9 HIGH LIMIT (POWER-ON DEFAULT 64H/1005C)
Bit Name R/W Description
7–0 Ext2 Temp/ R/W This register contains the high limit of the Ext2 Temp/AIN9 channel depending on
AIN9 High Limit which one is configured.

Table 80. REGISTER 42H, 3.3 V STBY HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 3.3 V STBY High Limit R/W This register contains the high limit of the 3.3 V STBY analog input channel.

Table 81. REGISTER 43H, 3.3 V MAIN HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 3.3 V MAIN High Limit R/W This register contains the high limit of the 3.3 V MAIN analog input channel.

Table 82. REGISTER 44H, +5.0 V HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 +5.0 V High Limit R/W This register contains the high limit of the +5.0 V analog input channel.

Table 83. REGISTER 45H, VCCP HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 VCCP High Limit R/W This register contains the high limit of the VCCP analog input channel.

Table 84. REGISTER 46H, +12 V HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 +12 V High Limit R/W This register contains the high limit of the +12 V analog input channel.

Table 85. REGISTER 47H, −12 V HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 −12 V High Limit R/W This register contains the high limit of the -12 V analog input channel.

Table 86. REGISTER 48H, EXT1 LOW LIMIT (POWER-ON DEFAULT 80H)
Bit Name R/W Description
7–0 Ext1 Low Limit R/W This register contains the low limit of the Ext1 Temp channel.

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Table 87. REGISTER 49H, EXT/AIN9 LOW LIMIT (POWER-ON DEFAULT 80H)
Bit Name R/W Description
7–0 Ext2 Temp /AIN9 Low R/W This register contains the low limit of the Ext2 Temp/AIN9 channel depending on
Limit which bit is configured.

Table 88. REGISTER 4AH, 3.3 V STBY LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 3.3 V STBY Low Limit R/W This register contains the low limit of the 3.3 V STBY analog input channel.

Table 89. REGISTER 4BH, 3.3 V MAIN LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 3.3 V MAIN Low Limit R/W This register contains the low limit of the 3.3 V MAIN analog input channel.

Table 90. REGISTER 4CH, +5.0 V LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 +5.0 V Low Limit R/W This register contains the low limit of the +5.0 V analog input channel.

Table 91. REGISTER 4DH, VCCP LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 VCCP Low Limit R/W This register contains the low limit of the VCCP analog input channel.

Table 92. REGISTER 4EH, +12 V LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 +12 V Low Limit R/W This register contains the low limit of the +12 V analog input channel.

Table 93. REGISTER 4FH, −12 V LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 −12 V Low Limit R/W This register contains the low limit of the -12 V analog input channel.

Table 94. REGISTER 50H, AIN0 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN0 High Limit R/W This register contains the high limit of the AIN0 analog input channel.

Table 95. REGISTER 51H, AIN1 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN1 High Limit R/W This register contains the high limit of the AIN1 analog input channel.

Table 96. REGISTER 52H, AIN2 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN2 High Limit R/W This register contains the high limit of the AIN2 analog input channel.

Table 97. REGISTER 53H, AIN3 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN3 High Limit R/W This register contains the high limit of the AIN3 analog input channel.

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Table 98. REGISTER 54H, AIN4 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN4 High Limit R/W This register contains the high limit of the AIN4 analog input channel.

Table 99. REGISTER 55H, AIN5 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN5 High Limit R/W This register contains the high limit of the AIN5 analog input channel.

Table 100. REGISTER 56H, AIN6 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN6 High Limit R/W This register contains the high limit of the AIN6 analog input channel.

Table 101. REGISTER 57H, AIN7 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN7 High Limit R/W This register contains the high limit of the AIN7 analog input channel.

Table 102. REGISTER 58H, AIN0 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN0 Low Limit R/W This register contains the low limit of the AIN0 analog input channel.

Table 103. REGISTER 59H, AIN1 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN1 Low Limit R/W This register contains the low limit of the AIN1 analog input channel.

Table 104. REGISTER 5AH, AIN2 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN2 Low Limit R/W This register contains the low limit of the AIN2 analog input channel.

Table 105. REGISTER 5BH, AIN3 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN3 Low Limit R/W This register contains the low limit of the AIN3 analog input channel.

Table 106. REGISTER 5CH, AIN4 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN4 Low Limit R/W This register contains the low limit of the AIN4 analog input channel.

Table 107. REGISTER 5DH, AIN5 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN5 Low Limit R/W This register contains the low limit of the AIN5 analog input channel.

Table 108. REGISTER 5EH, AIN6 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN6 Low Limit R/W This register contains the low limit of the AIN6 analog input channel.

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ADM1026

Table 109. REGISTER 5FH, AIN7 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN7 Low Limit R/W This register contains the low limit of the AIN7 analog input channel.

Table 110. REGISTER 60H, FAN0 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN0 High Limit R/W This register contains the high limit of the FAN0 tach channel.

Table 111. REGISTER 61H, FAN1 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN1 High Limit R/W This register contains the high limit of the FAN1 tach channel.

Table 112. REGISTER 62H, FAN2 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN2 High Limit R/W This register contains the high limit of the FAN2 tach channel.

Table 113. REGISTER 63H, FAN3 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN3 High Limit R/W This register contains the high limit of the FAN3 tach channel.

Table 114. REGISTER 64H, FAN4 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN4 High Limit R/W This register contains the high limit of the FAN4 tach channel.

Table 115. REGISTER 65H, FAN5 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN5 High Limit R/W This register contains the high limit of the FAN5 tach channel.

Table 116. REGISTER 66H, FAN6 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN6 High Limit R/W This register contains the high limit of the FAN6 tach channel.

Table 117. REGISTER 67H, FAN7 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 FAN7 High Limit R/W This register contains the high limit of the FAN7 tach channel.

Table 118. REGISTER 68H, INT TEMP HIGH LIMIT (POWER-ON DEFAULT, 50H 805C)
Bit Name R/W Description
7–0 Int Temp High Limit R/W This register contains the high limit of the internal temperature channel.

Table 119. REGISTER 69H, INT TEMP HIGH LIMIT (POWER-ON DEFAULT 80H)
Bit Name R/W Description
7–0 Int Temp Low Limit R/W This register contains the low limit of the internal temperature channel.

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ADM1026

Table 120. REGISTER 6AH, VBAT HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 VBAT High Limit R/W This register contains the high limit of the VBAT analog input channel.

Table 121. REGISTER 6BH, VBAT LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 VBAT Low Limit R/W This register contains the low limit of the VBAT analog input channel.

Table 122. REGISTER 6CH, AIN8 HIGH LIMIT (POWER-ON DEFAULT FFH)
Bit Name R/W Description
7–0 AIN8 High Limit R/W This register contains the high limit of the AIN8 analog input channel.

Table 123. REGISTER 6DH, AIN8 LOW LIMIT (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 AIN8 Low Limit R/W This register contains the low limit of the AIN8 analog input channel.

Table 124. REGISTER 6EH, EXT1 TEMP OFFSET (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 Ext1 Temp Offset R/W This register contains the offset value for the external 1 temperature channel. A twos
complement number can be written to this register, which is then added to the
measured result before it is stored or compared to limits. In this way, a sort of
one-point calibration can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel if the thermal
characteristics change for any reason (for instance from one chassis to another), if the
measurement point is moved, if a plug-in card is inserted or removed, and so on.

Table 125. REGISTER 6FH, EXT2 TEMP OFFSET (POWER-ON DEFAULT 00H)
Bit Name R/W Description
7–0 Ext2 Temp Offset R/W This register contains the offset value for the external 2 temperature channel. A twos
complement number can be written to this register, which is then added to the
measured result before it is stored or compared to limits. In this way, a sort of
one-point calibration can be done whereby the whole transfer function of the channel
can be moved up or down. From a software point of view, this may be a very simple
method to vary the characteristics of the measurement channel if the thermal
characteristics change for any reason (for instance from one chassis to another), if the
measurement point is moved, if a plug-in card is inserted or removed, and so on.

Table 126. ORDERING INFORMATION


Device Order Number Temperature Range Package Type Package Option Shipping†
ADM1026JSTZ−REEL 0C to +100C 48−Lead LQFP ST−48 2,000 Tape & Reel
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*The “Z’’ suffix indicates Pb−Free part.

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ADM1026

PACKAGE DIMENSIONS

48 LEAD LQFP, 7x7, 0.5P


CASE 932AA−01
ISSUE A
4X
NOTES:
0.2 Y T-U Z 1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
PIN 1
D ASME Y14.5M, 1994.
CORNER 3. DATUM PLANE H IS LOCATED AT BOTTOM OF
D/2 LEAD AND IS COINCIDENT WITH THE LEAD
48 Z 37 DETAIL K e/2 WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS T, U, AND Z TO BE DETERMINED AT
DATUM PLANE H.
1 36 5. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE Y.
T U 6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
G G PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 PER SIDE. DIMENSIONS D1 AND E1 DO
E E1 INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE H.
7. DIMENSION b DOES NOT INCLUDE DAMBAR
E1/2 PROTRUSION. DAMBAR PROTRUSION SHALL
E/2 T, U, Z
NOT CAUSE THE b DIMENSION TO EXCEED 0.350.
12 25 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076.
DETAIL K 9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
NOTE 9
13 24 MILLIMETERS
DIM MIN MAX
D1/2 A 1.4 1.6
A1 0.05 0.15
D1 A2 1.35 1.45
4X BASE METAL b 0.17 0.27

ÇÇÇÇ
ÉÉÉ
PLATING b1 0.17 0.23
0.2 H T-U Z DETAIL F c 0.09 0.20

ÇÇÇÇ
ÉÉÉ
H c1 0.09 0.16
0.08 Y D 9.0 BSC
c1 c

ÇÇÇÇ
ÉÉÉ
D1 7.0 BSC
e 0.5 BSC
E 9.0 BSC
E1 7.0 BSC
e/2 L 0.5 0.7
48 X b b1 L1 1.0 REF
Y 44 X e
b R 0.15 0.25
SEATING S 0.2 REF
PLANE 0.08 M Y T-U Z q 1_ 5_
q1 12 REF
SECTION G−G
q1
TOP & BOTTOM

A A2

(S) 0.250
A1 L q GAUGE PLANE
DETAIL F (L1)

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION


LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Europe, Middle East and Africa Technical Support: Order Literature: http://www.onsemi.com/orderlit
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Phone: 421 33 790 2910
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Japan Customer Focus Center For additional information, please contact your local
Email: orderlit@onsemi.com Phone: 81−3−5817−1050 Sales Representative

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