Data Sheet

ADP150
Ultralow Noise, 150 mA, CMOS Linear Regulator

FEATURES TYPICAL APPLICATION CIRCUITS

► Ultralow noise: 9 µV rms, independent of VOUT
► No additional noise bypass capacitor required
► Stable with 1 µF ceramic input and output capacitors
► Maximum output current: 150 mA
► Input voltage range: 2.2 V to 5.5 V
► Low quiescent current
Figure 1. 5-Lead TSOT with Fixed Output Voltage, 1.8 V
► IGND = 10 µA with zero load
► Low shutdown current: <1 µA
► Low dropout voltage: 105 mV at 150 mA load
► Initial output voltage accuracy: ±1%
► Up to 14 fixed output voltage options: 1.8 V to 3.3 V
► PSRR performance of 70 dB at 10 kHz
► Current limit and thermal overload protection
► Logic-controlled enable Figure 2. 4-Ball WLCSP with Fixed Output Voltage, 1.8 V
► 5-lead TSOT package
► 4-ball, 0.8 mm × 0.8 mm, 0.4 mm pitch WLCSP
► AEC-Q100 qualified for automotive applications
APPLICATIONS
► Mobile phones
► Digital camera and audio devices
► Portable and battery-powered equipment
► Post dc-to-dc regulation
► Portable medical devices
► RF, voltage controlled oscillator (VCO), and phase locked loop
(PLL) power supplies
GENERAL DESCRIPTION
The ADP150 is an ultralow noise (9 µV), low dropout, linear regula- The ADP150 is specifically designed for stable operation with tiny
tor that operates from 2.2 V to 5.5 V and provides up to 150 mA 1 µF ± 30% ceramic input and output capacitors to meet the
of output current. The low 105 mV dropout voltage at 150 mA load requirements of high performance, space-constrained applications.
improves efficiency and allows operation over a wide input voltage
range. The ADP150 is available in 14 fixed output voltage options, ranging
from 1.8 V to 3.3 V.
Using an innovative circuit topology, the ADP150 achieves ultralow
noise performance without the necessity of an additional noise Short-circuit and thermal overload protection circuits prevent dam-
bypass capacitor, making it ideal for noise sensitive analog and age in adverse conditions. The ADP150 is available in tiny 5-lead
RF applications. The ADP150 also achieves ultralow noise per- TSOT and 4-ball, 0.4 mm pitch WLCSP packages for the smallest
formance without compromising PSRR or line and load transient footprint solution to meet a variety of portable power applications.
performance. The ADP150 offers the best combination of ultralow
noise and quiescent current consumption to maximize battery life in
portable applications.

Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog
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 Data Sheet ADP150
TABLE OF CONTENTS

Features................................................................ 1 Applications Information...................................... 12

Applications........................................................... 1 Capacitor Selection.......................................... 12
Typical Application Circuits....................................1 Undervoltage Lockout...................................... 13
General Description...............................................1 Enable Feature.................................................13
Specifications........................................................ 3 Current Limit and Thermal Overload
Recommended Specifications: Input and Protection....................................................... 13
Output Capacitor.............................................. 4 Thermal Considerations................................... 14
Absolute Maximum Ratings...................................5 PCB Layout Considerations............................. 17
Thermal Data......................................................5 Outline Dimensions............................................. 18
Thermal Resistance........................................... 5 Ordering Guide ................................................18
ESD Caution.......................................................5 Output Voltage Options.................................... 19
Pin Configurations and Function Descriptions.......6 Evaluation Boards............................................ 19
Typical Performance Characteristics..................... 7 Automotive Products ....................................... 19
Theory of Operation.............................................11

REVISION HISTORY

11/2022—Rev. D to Rev. E
Changes to Applications Section..................................................................................................................... 1
Changes to Undervoltage Lockout Parameter, Table 1................................................................................... 3
Changes to Figure 12 and Figure 14............................................................................................................... 8
Changes to Figure 49.................................................................................................................................... 18
Changes to Ordering Guide........................................................................................................................... 18
Changes to Evaluation Board ....................................................................................................................... 19

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 Data Sheet ADP150
SPECIFICATIONS

VIN = (VOUT + 0.4 V) or 2.2 V, whichever is greater; EN = VIN, IOUT = 10 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.

Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT VOLTAGE RANGE VIN TJ = −40°C to +125°C 2.2 5.5 V
OPERATING SUPPLY CURRENT IGND IOUT = 0 µA 10 µA
IOUT = 0 µA, TJ = −40°C to +125°C 22 µA
IOUT = 100 µA 20 µA
IOUT = 100 µA, TJ = −40°C to +125°C 40 µA
IOUT = 10 mA 60 µA
IOUT = 10 mA, TJ = −40°C to +125°C 100 µA
IOUT = 150 mA 220 µA
IOUT = 150 mA, TJ = −40°C to +125°C 320 µA
SHUTDOWN CURRENT IGND-SD EN = GND 0.2 µA
EN = GND, TJ = −40°C to +125°C 1.0 µA
OUTPUT VOLTAGE ACCURACY
5-Lead TSOT VOUT IOUT = 10 mA −1 +1 %
100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −2.5 +1.5 %
−40°C to +125°C
4-Ball WLCSP VOUT IOUT = 10 mA −1 +1 %
100 µA < IOUT < 150 mA, VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −2.0 +1.5 %
−40°C to +125°C
REGULATION
Line Regulation ∆VOUT/∆VIN VIN = (VOUT + 0.4 V) to 5.5 V, TJ = −40°C to +125°C −0.05 +0.05 %/V
Load Regulation1
5-Lead TSOT ∆VOUT/∆IOUT IOUT = 100 µA to 150 mA 0.003 %/mA
IOUT = 100 µA to 150 mA, TJ = −40°C to +125°C 0.0075 %/mA
4-Ball WLCSP ∆VOUT/∆IOUT IOUT = 100 µA to 150 mA 0.002 %/mA
IOUT = 100 µA to 150 mA, TJ = −40°C to +125°C 0.006 %/mA
DROPOUT VOLTAGE2 VDROPOUT IOUT = 10 mA 10 mV
IOUT = 10 mA, TJ = −40°C to +125°C 35 mV
IOUT = 150 mA 105 mV
IOUT = 150 mA, TJ = −40°C to +125°C 160 mV
START-UP TIME3 TSTART-UP VOUT = 3.3 V 150 µs
CURRENT-LIMIT THRESHOLD4 ILIMIT 190 260 400 mA
W grade, TJ = −40°C to +125°C 155 260 400 mA
UNDERVOLTAGE LOCKOUT TJ = −40°C to +125°C
Input Voltage Rising UVLORISE 1.96 V
W grade 1.86 V
Input Voltage Falling UVLOFALL 1.28 V
Hysteresis UVLOHYS 115 mV
THERMAL SHUTDOWN
Thermal Shutdown Threshold TSSD TJ rising 150 °C
Thermal Shutdown Hysteresis TSSD-HYS 15 °C
EN INPUT
EN Input Logic High VIH 2.2 V ≤ VIN ≤ 5.5 V 1.2 V
EN Input Logic Low VIL 2.2 V ≤ VIN ≤ 5.5 V 0.4 V

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 Data Sheet ADP150
SPECIFICATIONS

Table 1. (Continued)
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
EN Input Leakage Current VI-LEAKAGE EN = IN or GND 0.001 µA
EN = IN or GND, TJ = −40°C to +125°C 1 µA
OUTPUT NOISE OUTNOISE 10 Hz to 100 kHz, VIN = 5 V, VOUT = 3.3 V 9 µV rms
10 Hz to 100 kHz, VIN = 5 V, VOUT = 2.5 V 9 µV rms
10 Hz to 100 kHz, VIN = 5 V, VOUT = 1.8 V 9 µV rms
POWER SUPPLY REJECTION RATIO PSRR 10 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 70 dB
(VIN = VOUT + 0.5 V)
10 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA 70 dB
100 kHz, VIN = 3.8 V, VOUT = 3.3 V, IOUT = 10 mA 55 dB
100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA 55 dB
POWER SUPPLY REJECTION RATIO 10 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 70 dB
(VIN = VOUT + 1 V)
100 kHz, VIN = 4.3 V, VOUT = 3.3 V, IOUT = 10 mA 55 dB

1 Based on an end-point calculation using 1 mA and 150 mA loads. See Figure 6 for typical load regulation performance for loads less than 1 mA.
2 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output voltages above
2.2 V.
3 Start-up time is defined as the time between the rising edges of EN to VOUT being at 90% of its nominal value.
4 Current limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V output
voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V or 2.7 V.

RECOMMENDED SPECIFICATIONS: INPUT AND OUTPUT CAPACITOR

Table 2.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
INPUT AND OUTPUT CAPACITOR
Minimum Input and Output Capacitance1 CMIN TA = −40°C to +125°C 0.7 µF
Capacitor ESR RESR TA = −40°C to +125°C 0.001 0.2 Ω

1 The minimum input and output capacitance should be greater than 0.7 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R-type and X5R-type capacitors are recommended,
and Y5V and Z5U capacitors are not recommended for use with any LDO.

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 Data Sheet ADP150
ABSOLUTE MAXIMUM RATINGS

Table 3. power dissipation exists, close attention to thermal board design is

Parameter Rating required. The value of θJA can vary, depending on PCB material,
VIN to GND −0.3 V to +6.5 V
layout, and environmental conditions. The specified values of θJA
are based on a 4-layer, 4 inch × 3 inch circuit board. Refer to
VOUT to GND −0.3 V to VIN
JESD 51-7 and JESD 51-9 for detailed information on the board
EN to GND −0.3 V to +6.5 V construction. For additional information, see the AN-617 Application
Temperature Range Note, Wafer Level Chip Scale Package.
Storage −65°C to +150°C
ΨJB is the junction-to-board thermal characterization parameter with
Operating Junction −40°C to +125°C units of °C/W. ΨJB of the package is based on modeling and
Operating Ambient −40°C to +85°C a calculation using a 4-layer board. The JESD51-12, Guidelines
Soldering Conditions JEDEC J-STD-020 for Reporting and Using Package Thermal Information, states that
thermal characterization parameters are not the same as thermal
Stresses at or above those listed under Absolute Maximum Ratings resistances. ΨJB measures the component power flowing through
may cause permanent damage to the product. This is a stress multiple thermal paths rather than a single path as in thermal
rating only; functional operation of the product at these or any other resistance, θJB. Therefore, ΨJB thermal paths include convection
conditions above those indicated in the operational section of this from the top of the package as well as radiation from the pack-
specification is not implied. Operation beyond the maximum operat- age, factors that make ΨJB more useful in real-world applications.
ing conditions for extended periods may affect product reliability. Maximum junction temperature (TJ) is calculated from the board
THERMAL DATA temperature (TB) and power dissipation (PD) by

Absolute maximum ratings apply individually only, not in combina- TJ = TB + (PD × ΨJB)
tion. The ADP150 can be damaged when the junction temperature Refer to JESD51-8 and JESD51-12 for more detailed information
limits are exceeded. Monitoring ambient temperature does not about ΨJB.
guarantee that TJ is within the specified temperature limits. In appli-
cations with high power dissipation and poor thermal resistance, the THERMAL RESISTANCE
maximum ambient temperature may have to be derated. θJA and ΨJB are specified for the worst-case conditions, that is, a
In applications with moderate power dissipation and low printed device soldered in a circuit board for surface-mount packages.
circuit board (PCB) thermal resistance, the maximum ambient tem- Table 4. Thermal Resistance
perature can exceed the maximum limit as long as the junction Package Type θJA ΨJB Unit
temperature is within specification limits. The junction temperature
(TJ) of the device is dependent on the ambient temperature (TA), 5-Lead TSOT 170 43 °C/W
the power dissipation of the device (PD), and the junction-to-ambi- 4-Ball, 0.4 mm Pitch WLCSP 260 58 °C/W
ent thermal resistance of the package (θJA).
ESD CAUTION
Maximum junction temperature (TJ) is calculated from the ambient
ESD (electrostatic discharge) sensitive device. Charged devi-
temperature (TA) and power dissipation (PD) by
ces and circuit boards can discharge without detection. Although
TJ = TA + (PD × θJA) this product features patented or proprietary protection circuitry,
damage may occur on devices subjected to high energy ESD.
The junction to ambient thermal resistance (θJA) of the package is Therefore, proper ESD precautions should be taken to avoid
based on modeling and a calculation using a 4-layer board. The performance degradation or loss of functionality.
junction to ambient thermal resistance is highly dependent on the
application and board layout. In applications where high maximum

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 Data Sheet ADP150
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. 5-Lead TSOT Pin Configuration

Table 5. 5-Lead TSOT Pin Function Descriptions

Pin No. Mnemonic Description
1 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
2 GND Ground.
3 EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
4 NC No Connect. Not connected internally.
5 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.

Figure 4. 4-Ball WLCSP Pin Configuration

Table 6. 4-Ball WLCSP Pin Function Descriptions

Pin No. Mnemonic Description
A1 VIN Regulator Input Supply. Bypass VIN to GND with a 1 µF or greater capacitor.
A2 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 1 µF or greater capacitor.
B1 EN Enable Input. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
B2 GND Ground.

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 Data Sheet ADP150
TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 3.7 V, VOUT = 3.3 V, IOUT = 1 mA, CIN = COUT = 1 µF, TA = 25°C, unless otherwise noted.

Figure 5. Output Voltage (VOUT) vs. Junction Temperature Figure 8. Ground Current vs. Junction Temperature

Figure 6. Output Voltage (VOUT) vs. Load Current (IOUT) Figure 9. Ground Current vs. Load Current (IOUT)

Figure 7. Output Voltage (VOUT) vs. Input Voltage (VIN) Figure 10. Ground Current vs. Input Voltage (VIN)

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 Data Sheet ADP150
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages Figure 14. Ground Current vs. Input Voltage (VIN) in Dropout

Figure 12. Dropout Voltage vs. Load Current (ILOAD) Figure 15. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 1.8 V,
VIN = 2.3 V

Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout
Figure 16. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 2.8 V,
VIN = 3.3 V

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 Data Sheet ADP150
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 17. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 3.3 V, Figure 20. Output RMS Noise vs. Load Current (IOUT) and Output Voltage
VIN = 3.8 V (VOUT), VIN = 5 V, COUT = 1 µF

Figure 18. Power Supply Rejection Ratio (PSRR) vs. Frequency Various Figure 21. Output Noise Spectrum, VIN = 5 V, ILOAD = 10 mA, COUT = 1 μF
Output Voltages and Load Currents

Figure 22. Load Transient Response, COUT = 1 µF

Figure 19. Power Supply Rejection Ratio (PSRR) vs. Frequency with Various
Headroom Voltages (VIN − VOUT), VOUT = 3.3 V

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 Data Sheet ADP150
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 23. Load Transient Response, COUT = 4.7 μF Figure 25. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 150 mA

Figure 24. Line Transient Response, CIN, COUT = 1 μF, ILOAD = 1 mA

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 Data Sheet ADP150
THEORY OF OPERATION

The ADP150 is an ultralow noise, low quiescent current, low Internally, the ADP150 consists of a reference, an error amplifier,
dropout linear regulator that operates from 2.2 V to 5.5 V and a feedback voltage divider, and a PMOS pass transistor. Output
can provide up to 150 mA of output current. Drawing a low 220 current is delivered via the PMOS pass device that is controlled
µA of quiescent current (typical) at full load makes the ADP150 by the error amplifier. The error amplifier compares the reference
ideal for battery-operated portable equipment. Shutdown current voltage with the feedback voltage from the output and amplifies
consumption is typically 200 nA. the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
Using a proprietary architecture, the ADP150 provides superior more current to pass and increasing the output voltage. If the
noise performance for noise sensitive analog and RF applications feedback voltage is higher than the reference voltage, the gate of
without the need for a noise bypass capacitor. The ADP150 is also the PMOS device is pulled higher, allowing less current to pass and
optimized for use with small 1 µF ceramic capacitors. decreasing the output voltage.
The ADP150 is available in 14 output voltage options, ranging from
1.8 V to 3.3 V. The ADP150 uses the EN pin to enable and disable
the VOUT pin under normal operating conditions. When EN is high,
VOUT turns on, and when EN is low, VOUT turns off. For automatic
startup, EN can be tied to VIN.

Figure 26. Internal Block Diagram

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 Data Sheet ADP150
APPLICATIONS INFORMATION

CAPACITOR SELECTION of output capacitance is required, increase the input capacitor to

match the output capacitor.
Output Capacitor
Input and Output Capacitor Properties
The ADP150 is designed for operation with small, space-saving
ceramic capacitors but functions with most commonly used capaci- Any good quality ceramic capacitors can be used with the ADP150,
tors as long as care is taken with regard to the effective series as long as they meet the minimum capacitance and maximum
resistance (ESR) value. The ESR of the output capacitor affects the ESR requirements. Ceramic capacitors are manufactured with a
stability of the LDO control loop. A minimum of 1 µF capacitance variety of dielectrics, each with different behavior over temperature
with an ESR of 1 Ω or less is recommended to ensure the stability and applied voltage. Capacitors must have a dielectric adequate to
of the ADP150. The transient response to changes in load current ensure the minimum capacitance over the necessary temperature
is also affected by output capacitance. Using a larger value of range and dc bias conditions. X5R or X7R dielectrics with a voltage
output capacitance improves the transient response of the ADP150 rating of 6.3 V or 10 V are recommended. Y5V and Z5U dielectrics
to large changes in the load current. Figure 27 and Figure 28 show are not recommended, due to their poor temperature and dc bias
the transient responses for output capacitance values of 1 µF and characteristics.
4.7 µF, respectively. Figure 29 depicts the capacitance vs. the voltage bias characteristic
of a 0402, 1 µF, 10 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the X5R
dielectric is about ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.

Figure 27. Output Transient Response, COUT = 1 µF

Figure 29. Capacitance vs. Voltage Bias Characteristic

Use Equation 1 to determine the worst-case capacitance, account-

ing for capacitor variation over temperature, component tolerance,
and voltage.
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL) (1)
where:
CBIAS is the effective capacitance at the operating voltage.
TEMPCO is the worst-case capacitor temperature coefficient.
Figure 28. Output Transient Response, COUT = 4.7 µF TOL is the worst-case component tolerance.
In this example, the worst-case temperature coefficient (TEMPCO)
Input Bypass Capacitor
over −40°C to +85°C is assumed to be 15% for an X5R dielectric.
Connecting a 1 µF capacitor from VIN to GND reduces the circuit The tolerance of the capacitor (TOL) is assumed to be 10%, and
sensitivity to the PCB layout, especially when long input traces the CBIAS is 0.94 µF at 1.8 V, as shown in Figure 29.
or high source impedance is encountered. If greater than 1 µF Substituting these values in Equation 1 yields

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 Data Sheet ADP150
APPLICATIONS INFORMATION

CEFF = 0.94 µF × (1 − 0.15) × (1 − 0.1) = 0.719 µF

Therefore, the capacitor chosen in this example meets the mini-
mum capacitance requirement of the LDO over temperature and
tolerance at the chosen output voltage.
To guarantee the performance of the ADP150, it is imperative that
the effects of the dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each.
UNDERVOLTAGE LOCKOUT
The ADP150 has an internal undervoltage lockout circuit that disa-
bles all inputs and the output when the input voltage is less than
approximately 2.0 V. This ensures that the ADP150 inputs and
output behave in a predictable manner during power-up.
Figure 31. Typical EN Pin Thresholds vs. Input Voltage (VIN)
ENABLE FEATURE
The ADP150 uses the EN pin to enable and disable the VOUT pin The ADP150 uses an internal soft start to limit the inrush current
under normal operating conditions. As shown in Figure 30, when a when the output is enabled. The start-up time for the 3.3 V option
rising voltage on EN crosses the active threshold, VOUT turns on. is approximately 150 µs from the time the EN active threshold is
When a falling voltage on EN crosses the inactive threshold, VOUT crossed to when the output reaches 90% of its final value. As
turns off. shown in Figure 32, the start-up time is dependent on the output
voltage setting.

Figure 30. Typical EN Pin Operation

Figure 32. Typical Start-Up Time
As shown in Figure 30, the EN pin has hysteresis built in. This
prevents on/off oscillations that can occur due to noise on the EN CURRENT LIMIT AND THERMAL OVERLOAD
pin as it passes through the threshold points. PROTECTION
The EN pin active/inactive thresholds are derived from the VIN volt- The ADP150 is protected against damage due to excessive power
age; therefore, these thresholds vary with changing input voltage. dissipation by current and thermal overload protection circuits. The
Figure 31 shows the typical EN active/inactive thresholds when the ADP150 is designed to limit current when the output load reaches
input voltage varies from 2.2 V to 5.5 V. 260 mA (typical). When the output load exceeds 260 mA, the output
voltage is reduced to maintain a constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power dissipation)
when the junction temperature starts to rise above 150°C, the
output is turned off, reducing the output current to zero. When the
junction temperature drops below 135°C, the output is turned on
again and the output current is restored to its nominal value.
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 Data Sheet ADP150
APPLICATIONS INFORMATION

Consider the case where a hard short from VOUT to GND occurs. Table 7. Typical θJA Values (Continued)
At first, the ADP150 limits current so that only 260 mA is conducted θJA (°C/W)
into the short. If self-heating of the junction is great enough to Copper Size (mm2) TSOT WLCSP
cause its temperature to rise above 150°C, thermal shutdown
activates, turning off the output and reducing the output current to 500 131 151
zero. As the junction temperature cools and drops below 135°C, 1 Device soldered to minimum size pin traces.
the output turns on and conducts 260 mA into the short, again
causing the junction temperature to rise above 150°C. This thermal Table 8. Typical ΨJB Values
oscillation between 135°C and 150°C causes a current oscillation ΨJB (°C/W)
between 260 mA and 0 mA that continues as long as the short TSOT WLCSP
remains at the output. 42.8 58.4
Current and thermal limit protections are intended to protect the de-
vice against accidental overload conditions. For reliable operation, Use Equation 2 to calculate the junction temperature.
device power dissipation must be externally limited so that the TJ = TA + (PD × θJA) (2)
junction temperatures do not exceed 125°C.
where:
THERMAL CONSIDERATIONS TA is the ambient temperature.
PD is the power dissipation in the die, given by
In most applications, the ADP150 does not dissipate much heat
due to its high efficiency. However, in applications with high ambient PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND)
temperature and high supply voltage to output voltage differential,
the heat dissipated in the package is large enough that it can cause where:
the junction temperature of the die to exceed the maximum junction ILOAD is the load current.
temperature of 125°C. IGND is the ground current.
VIN and VOUT are input and output voltages, respectively.
When the junction temperature exceeds 150°C, the converter en-
ters thermal shutdown. It recovers only after the junction tempera- Power dissipation due to ground current is quite small and can be
ture decreases below 135°C to prevent any permanent damage. ignored. Therefore, the junction temperature equation simplifies to
Therefore, thermal analysis for the chosen application is very TJ = TA + (((VIN − VOUT) × ILOAD) × θJA) (3)
important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient As shown in the previous equation, for a given ambient temper-
temperature of the environment and the temperature rise of the ature, input-to-output voltage differential, and continuous load cur-
package due to the power dissipation, as shown in Equation 2. rent, there exists a minimum copper size requirement for the PCB
to ensure that the junction temperature does not rise above 125°C.
To guarantee reliable operation, the junction temperature of the Figure 33 to Figure 46 show the junction temperature calculations
ADP150 must not exceed 125°C. To ensure that the junction for the different ambient temperatures, load currents, VIN-to-VOUT
temperature stays below 125°C, be aware of the parameters that differentials, and areas of PCB copper.
contribute to the junction temperature changes. These parameters
include ambient temperature, power dissipation in the power de-
vice, and thermal resistances between the junction and ambient
air (θJA). The θJA number is dependent on the package assembly
compounds that are used and the amount of copper used to solder
the package GND pins to the PCB. Table 7 shows typical θJA
values of the 5-lead TSOT and 4-ball WLCSP packages for various
PCB copper sizes. Table 8 shows the typical ΨJB value of the
5-lead TSOT and 4-ball WLCSP.
Table 7. Typical θJA Values
θJA (°C/W)
Copper Size (mm2) TSOT WLCSP
01 170 260
50 152 159
Figure 33. TSOT, 500 mm2 of PCB Copper, TA = 25°C
100 146 157
300 134 153

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 Data Sheet ADP150
APPLICATIONS INFORMATION

Figure 34. TSOT, 100 mm2 of PCB Copper, TA = 25°C Figure 37. TSOT, 100 mm2 of PCB Copper, TA = 50°C

Figure 35. TSOT, 0 mm2 of PCB Copper, TA = 25°C Figure 38. TSOT, 0 mm2 of PCB Copper, TA = 50°C

Figure 36. TSOT, 500 mm2 of PCB Copper, TA = 50°C Figure 39. TSOT, 100 mm2 of PCB Copper, Board Temperature = 85°C

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 Data Sheet ADP150
APPLICATIONS INFORMATION

Figure 40. WLCSP, 500 mm2 of PCB Copper, TA = 25°C Figure 43. WLCSP, 500 mm2 of PCB Copper, TA = 50°C

Figure 41. WLCSP, 100 mm2 of PCB Copper, TA = 25°C Figure 44. WLCSP, 100 mm2 of PCB Copper, TA = 50°C

Figure 42. WLCSP, 0 mm2 of PCB Copper, TA = 25°C Figure 45. WLCSP, 0 mm2 of PCB Copper, TA = 50°C

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 Data Sheet ADP150
APPLICATIONS INFORMATION

Figure 46. WLCSP, 100 mm2 of PCB Copper, Board Temperature = 85°C Figure 48. Example WLCSP PCB Layout

PCB LAYOUT CONSIDERATIONS

Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP150. However,
as listed in Table 7, a point of diminishing returns is reached
eventually, beyond which an increase in the copper size does not
yield significant heat dissipation benefits.
Place the input capacitor as close as possible to the VIN and
GND pins. Place the output capacitor as close as possible to the
VOUT and GND pins. Use of 0402 size or 0603 size capacitors and
resistors achieves the smallest possible footprint solution on boards
where area is limited.

Figure 47. Example TSOT PCB Layout

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 Data Sheet ADP150
OUTLINE DIMENSIONS

Figure 49. 5-Lead Thin Small Outline Transistor Package [TSOT]

(UJ-5)
Dimensions shown in millimeters

Figure 50. 4-Ball Wafer Level Chip Scale Package [WLCSP]

(CB-4-3)
Dimensions shown in millimeters

Updated: November 11, 2022

ORDERING GUIDE
Table 9. Ordering Guide
Package
Model1, 2 Temperature Range Package Description Packing Quantity Option Marking Code
ADP150ACBZ-1.8-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 36
ADP150ACBZ-2.5-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 3V
ADP150ACBZ-2.6-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 63
ADP150ACBZ-2.75R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 3X
ADP150ACBZ-2.85R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 3Y
ADP150ACBZ-2.8-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 46
ADP150ACBZ-3.0-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 47
ADP150ACBZ-3.3-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 48
ADP150AUJZ-1.8-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LDS
ADP150AUJZ-2.0-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LT4
ADP150AUJZ-2.5-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LDZ
ADP150AUJZ-2.65-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LPE
ADP150AUJZ-2.8-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LE3
ADP150AUJZ-3.0-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LE2

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 Data Sheet ADP150
OUTLINE DIMENSIONS

Table 9. Ordering Guide (Continued)

Package
Model1, 2 Temperature Range Package Description Packing Quantity Option Marking Code
ADP150AUJZ-3.3-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LEJ
ADP150WACBZ-1.8-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 EY
ADP150WACBZ-2.5-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 EZ
ADP150WACBZ-2.6-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 F0
ADP150WACBZ-2.75-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 F1
ADP150WACBZ-2.85-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 F3
ADP150WACBZ-2.8-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 F2
ADP150WACBZ-3.0-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 FV
ADP150WACBZ-3.3-R7 −40°C to +125°C 4-Ball WLCSP (0.8mm x 0.8mm) Reel, 3000 CB-4-3 FW
ADP150WAUJZ-1.8-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LXA
ADP150WAUJZ-2.0-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LX8
ADP150WAUJZ-3.0-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LXB
ADP150WAUJZ-3.3-R7 −40°C to +125°C 5-Lead TSOT Reel, 3000 UJ-5 LXD
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.

OUTPUT VOLTAGE OPTIONS

Table 10. Output Voltage Options
Model1, 2, 3 Output Voltage (V)
ADP150ACBZ-1.8-R7, ADP150WACBZ-1.8-R7, ADP150AUJZ-1.8-R7, ADP150WAUJZ-1.8-R7 1.8
ADP150AUJZ-2.0-R7, ADP150WAUJZ-2.0-R7 2.0
ADP150ACBZ-2.5-R7, ADP150WACBZ-2.5-R7. ADP150AUJZ-2.5-R7 2.5
ADP150ACBZ-2.6-R7, ADP150WACBZ-2.6-R7 2.6
ADP150AUJZ-2.65-R7 2.65
ADP150ACBZ-2.75R7, ADP150WACBZ-2.75-R7 2.75
ADP150ACBZ-2.8-R7, ADP150WACBZ-2.8-R7, ADP150AUJZ-2.8-R7 2.8
ADP150ACBZ-2.85R7, ADP150WACBZ-2.85-R7 2.85
ADP150ACBZ-3.0-R7, ADP150WACBZ-3.0-R7, ADP150AUJZ-3.0-R7, ADP150WAUJZ-3.0-R7 3.0
ADP150ACBZ-3.3-R7, ADP150WACBZ-3.3-R7, ADP150AUJZ-3.3-R7, ADP150WAUJZ-3.3-R7 3.3
1 Z = RoHS Compliant Part.
2 W = Qualified for Automotive Applications.
3 Up to 14 fixed output voltage options from 1.8 V to 3.3 V are available. For additional voltage options, contact your local Analog Devices, Inc., sales or distribution
representative.

EVALUATION BOARDS
Table 11. Evaluation Boards
Model1 Description
ADP150CB-3.3-EVALZ Evaluation Board with WLCSP Package
ADP150UJZ-REDYKIT Evaluation Board
SCP-ADP150-EVALZ Signal Chain Power (SCP) Evaluation Board
1 Z = RoHS Compliant Part.

AUTOMOTIVE PRODUCTS
The ADP150W models are available with controlled manufacturing to support the quality and reliability requirements of automotive applications.
Note that these automotive models may have specifications that differ from the commercial models; therefore, designers should review the

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 Data Sheet ADP150
OUTLINE DIMENSIONS

Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in automotive applications.
Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive
Reliability reports for these models.

©2009-2022 Analog Devices, Inc. All rights reserved. Trademarks and Rev. E | 20 of 20
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.

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