Current Sources

Methods to Improve CMRR

CMRR can be Increased by increasing RE, but its affecting IC and VCE, hence which affects the
operating point and biasing of the circuits, which is undesirable.

Hence for this another options are

1. To use constant current source
2. To use current mirror circuit:-
either in place of RE
or in place of RC (active load)
 Current Mirror Circuit

Constant-current sources figure prominently in circuit-analysis exercises and network theorems, then they seem to more
or less disappear . . . unless you’re an IC designer. Though rarely encountered in typical PCB design, current sources are
ubiquitous in the world of analog ICs. This is because they are used 1) for biasing and 2) as active loads.

1.Biasing: Transistors functioning as linear amplifiers need to be biased such that they are operating in a desirable
portion of their transfer characteristic. The best way to do this in the context of IC design is to cause a predetermined
current to flow through the transistor’s drain (for MOSFETs) or collector (for BJTs). This predetermined current needs
to be stable and independent of the voltage across the current-source component. Of course, no real circuit will ever
be perfectly stable or perfectly immune to changes in voltage, but as is usually the case in engineering, perfection is
not quite necessary.

2.Active loads: In amplifier circuits, current sources can be used instead of collector/drain resistors. These “active
loads” provide higher voltage gain and allow the circuit to function properly with lower supply voltage. Also, IC
manufacturing technology favors transistors over resistors.

https://www.allaboutcircuits.com/technical-articles/the-basic-mosfet-constant-current-source/
 For maintaining stable biasing conditions, constant current source circuits like current
mirrors are required as they provide high voltage gain and also improves biasing stabilty

https://www.youtube.com/watch?v=Jmu02dErhdg
 In saturation ID can be given by above
equation, hence by controlling VGS ID
can be controlled

Need to generate VGS proportional to the Iref , so that ID of MOSFET will

be equal to the IRef hence diode connected transistor structure is used
as shown
 1 2

This MOSFET always operates

in the saturation region

Thus this MOSFET is operating in saturation region and Iref is producing VGS
like ID
Same VGS is applied between Mref and M1.

If both the MOSFETs are perfectly matched then

same VGS applied to the Mref and M1 should
produce same ID1 as that of Iref, provided M1
should always operate in the saturation.
Now let us find out the relationship between ID1
and Iref
Thus if this W/L ratio of the two
MOSFETS are same then ID1 = Iref
Widlar Current Source:-
In basic Current mirror circuit when value of Iref = ID = low , then value of drain resistance
connected need to be increased, which is difficult to fabricate. Hence modifications are
done in the basic current mirror circuit as shown in figure called as WIDLAR Current
Source
Used for generating low value currents, i.e. Io < IIN

IN > 0, then M1 operates in saturation

Let M2 is operating in saturation then, applying

KVL to gate source loop

VGS1 = VGS2 + IoR2

FET Current Sources :- Widlar Current Source
To avoid drawback of current mirror circuit Widlar
Current source is used

Series resistance R2 is placed at source terminal of

M2

It is suitable for low value currents

If IN > 0, then M1 operates in saturation region

Applying KVL around gate and source loop

VGS1 = VGs2 + I0R2
VGS1 - VGs2 - I0R2 = 0

If we ignore the body effect, the threshold

components of gate-source voltage cancel out in
above equation
Thus this MOSFET is operating in saturation region and Iref is producing VGS
like ID
FET Current Sources

If both MOSFETs are in strong inversion region

FET Current Sources

Since VGS1/VGS2 = ((W/L)2/(W/L)1)0.5 + [ 1 – (((W/L)2/(W/L)1)0.5 ] Vth

 M3 is driven by constant current IR

The gate and drain of M2 are

connected

IR = I0

Works on negative feedback

https://www.bing.com//videos/riverview/relatedvideo?q=wilson+current+mirror+circuit&mid=4A
9BE18C506F9328F8914A9BE18C506F9328F891&FORM=VIRE
• If Vo increases by some reason , then Io will increase and V2 also increases
• IO > IR
• V2 also increases
• This V2 is connected to gate of M2 and M3, hence VG3 also increases
• M3 is driven by constant current IR, now as per the equation given for IR , VDs3 is going to get reduced
• Now this VDs3 is connected to the gate of M1, hence VGs3 decreases, ultimately Io decreases.
• Thus owing to the negative feedback, IR = I0
DC Analysis

The important Dc parameters consider for analysis

are
1. Calculate IQ = I1
2. Calculate ID1 and ID2
3. Gate to source voltages of M1 and M2
4. Calculate common mode voltage :- Vcmax when M1 and M2 are at
transition
1.
5. Vcmmin when M4 is in transistion
Level Shifting Stage:-
Output Stage:-
Output Stage:-
Output Stage:-
The stability of the load current as a function of the drain-to-source voltage is an important consideration in many
applications. The drain current versus drain-to-source voltage is similar to the bipolar characteristic shown in Figure 10.4.
Taking into account the finite output resistance of the transistors, we can write the load and reference currents as follows:
Since transistors in the current mirror are processed on the same integrated circuit, all physical parameters,
such as VTN, μn , Cox, and λ, are essentially identical for both devices. Therefore, taking the ratio of IO to IREF, we have

Equation (10.47) again shows that the ratio IO/IREF is a function of the aspect ratios, which is controlled
by the designer, and it is also a function of λ and VDS2.
As before, the stability of the load current can be described in terms of the output resistance. Note from
the circuit in Figure 10.16 that VDS1 = VG S1 = constant for a given reference current. Normally,
λVDS1 = λVG S1 , and if (W/L )2 = (W/L )1 , then the change in bias current with respect to a change in VDS2 is
where ro is the output resistance of the transistor.
As we found with bipolar current-source circuits, MOSFET current sources
require a large output resistance for excellent stability.
Reference Current

The reference current in bipolar current-source circuits is generally established by the bias voltages and a resistor.
Since MOSFETs can be configured to act like a resistor, the reference current in MOSFET current mirrors is usually established
by using additional transistors.
Consider the current mirror shown in Figure 10.17. Transistors M1 and M3 are in series; assuming λ = 0,
we can write,

If we again assume that VT N , μn, and Cox are identical in all transistors, then Equation (10.49) can be rewritten

where VT N is the threshold voltage of both transistors.

From the circuit, we see that
Objective: Design a MOSFET current source circuit to meet a set of specifications.

Specifications: The circuit to be designed has the configuration shown in Figure 10.17. The bias voltages are
V + = +5 V and V − = 0. Transistors are available with parameters k n = 40 μA/V2, VT N = 1 V, and λ = 0. Design the circuit such
that IREF = 0.25 mA, IO = 0.10 mA, and VDS2(sat) = 0.85 V.

We have that VDS2(sat) = 0.85 = VG S2 − 1, so that VG S2 = 1.85 V. Then

Ex 10.8: For the circuit shown in Figure 10.17, V + = 10 V and V − = 0, and the transistor parameters are: VT N = 2 V, 1
2μnCox = 20 μA/V2 , and λ = 0. Design the circuit such that IREF = 0.5 mA and IO = 0.2 mA, and M2 remains biased in the saturation
region for VDS2 ≥ 1 V. (Ans. (W/L )2 = 10, (W/L )1 = 25, (W/L )3 = 1)
Multi-MOSFET Current-Source Circuits:- Wilson Current Source
 Multi-MOSFET Current-Source Circuits:- Wilson Current Source

• Two additional multi-MOSFET current sources are shown in Figures 10.20(a) and 10.20b).
• The circuit in Figure 10.20(a) is the Wilson current source. Note that the VDS values of M1 and M2 are not equal. Since λ
is not zero, the ratio IO/IREF is slightly different from the aspect ratios.
• This problem is solved in the modified Wilson current source, shown in Figure 10.20(b), which includes transistor M4.
For a constant reference current, the drain-to-source voltages of M1, M2, and M4 are held constant. The primary
advantage of these circuits is the increase in output resistance, which further stabilizes the load current.
Widlar Current Source:-
In basic Current mirror circuit when value of Iref = ID = low , then value of drain resistance
connected need to be increased, which is difficult to fabricate. Hence modifications are
done in the basic current mirror circuit as shown in figure called as WIDLAR Current
Source
Used for generating low value currents, i.e. Io < IIN

IN > 0, then M1 operates in saturation

Let M2 is operating in saturation then, applying

KVL to gate source loop

VGS1 = VGS2 + IoR2

Widlar Current Source:-
FET Current Sources :- Widlar Current Source
To avoid drawback of current mirror circuit Widlar
Current source is used

Series resistance R2 is placed at source terminal of

M2

It is suitable for low value currents

If IN > 0, then M1 operates in saturation region

Applying KVL around gate and source loop

VGS1 = VGs2 + I0R2
VGS1 - VGs2 - I0R2 = 0

If we ignore the body effect, the threshold

components of gate-source voltage cancel out in
above equation
Thus this MOSFET is operating in saturation region and Iref is producing VGS
like ID
FET Current Sources

If both MOSFETs are in strong inversion region

FET Current Sources

Since VGS1/VGS2 = ((W/L)2/(W/L)1)0.5 + [ 1 – (((W/L)2/(W/L)1)0.5 ] Vth