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Cmos B

The document discusses CMOS technology which uses both PMOS and NMOS transistors. CMOS circuits have very low static power dissipation unlike NMOS or bipolar circuits. This allows for higher integration densities on chips resulting in better performance. CMOS logic gates use a pull-up network of PMOS transistors and a pull-down network of NMOS transistors such that one is always on and the other off.

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19 views2 pages

Cmos B

The document discusses CMOS technology which uses both PMOS and NMOS transistors. CMOS circuits have very low static power dissipation unlike NMOS or bipolar circuits. This allows for higher integration densities on chips resulting in better performance. CMOS logic gates use a pull-up network of PMOS transistors and a pull-down network of NMOS transistors such that one is always on and the other off.

Uploaded by

mukulgrd1
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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CMOS (Complementary Metal Oxide Semiconductor)

The main advantage of CMOS over NMOS and BIPOLAR technology is the much smaller power
dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary MOS circuit has almost no static
power dissipation. Power is only dissipated in case the circuit actually switches. This allows integrating
more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.
Complementary Metal Oxide Semiconductor transistor consists of P-channel MOS (PMOS) and
Nchannel
MOS (NMOS). Please refer the link to know more about the fabrication process of CMOS
transistor.

NMOS
NMOS is built on a p-type substrate with n-type source and drain diffused on it. In NMOS, the
majority carriers are electrons. When a high voltage is applied to the gate, the NMOS will conduct.
Similarly, when a low voltage is applied to the gate, NMOS will not conduct. NMOS are considered to be
faster than PMOS, since the carriers in NMOS, which are electrons, travel twice as fast as the holes.

PMOS
P- channel MOSFET consists P-type Source and Drain diffused on an N-type substrate. Majority
carriers are holes. When a high voltage is applied to the gate, the PMOS will not conduct. When a low
voltage is applied to the gate, the PMOS will conduct. The PMOS devices are more immune to noise than
NMOS devices.
CMOS Working Principle
In CMOS technology, both N-type and P-type transistors are used to design logic functions. The
same signal which turns ON a transistor of one type is used to turn OFF a transistor of the other type. This
characteristic allows the design of logic devices using only simple switches, without the need for a pullup
resistor.
In CMOS logic gates a collection of n-type MOSFETs is arranged in a pull-down network
between the output and the low voltage power supply rail (Vss or quite often ground). Instead of the load
resistor of NMOS logic gates, CMOS logic gates have a collection of p-type MOSFETs in a pull-up
network between the output and the higher-voltage rail (often named Vdd).
Thus, if both a p-type and n-type transistor have their gates connected to the same input, the ptype
MOSFET will be ON when the n-type MOSFET is OFF, and vice-versa. The networks are arranged
such that one is ON and the other OFF for any input pattern as shown in the figure below.

CMOS Logic Gate using Pull-Up and Pull-Down Networks

CMOS ADVANTAGES
 Very low static power consumption
 Reduce the complexity of the circuit
 The high density of logic functions on a chip
 Low static power consumption
 High noise immunity

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