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Physical Only Cells

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257 views5 pages

Physical Only Cells

Uploaded by

durgaprasadkatakam66
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Physical Only Cells

Physical only cells are cells with no logical functions and are not present in netlist. Those
have VDD and VSS connections only.

Preplace cells:

1. End cap:
- It is used to mitigate Well Proximity Effect
- There are high chances to get damaged the gate of standard cells placed at
the boundary during the manufacturing of chip. To prevent such damages at
the boundary we have a special kind of cell in the standard cell library is called
end cap cell or boundary cell.
- The end cap cells place at boundaries of core area .
2.Well tap:
- Well tap ceels are used for “ removing the LATCHUP “ issue.
-it Tap the nwell to POWER and psub to GND rails.

- these cells are placed by following the “ check board fasssion”.

2. Spare cells:
Spare cells will be used to implement ECO after BaseTape Out & Before Metal-Tape
Out. If any bugs are reported/found after the tape-out, we can use these spare cells
to fix the bugs. The key to having spare cells in your design is that you only need to
change the metal layers to rewire the logic and fix any bugs. This means you only
need to pay for new metal masks, thus saving money. The Spare Cell Input pins must
be tied to VSS and output pins left floating. Spare cells are nothing but standard cells
and are placed randomly across the chip for later use.
4. IO buffers: Signal strengthening/slew rate improvement

Post place cells:

1. Tie cells:
- Tie cells are used to protect the std cells from power and ground bounces .
- Tie high cell connect gate to VDD , Tie low cell connect the gate to VSS .
- Smetimes pins need to be connected to logic0 / logic-1. In Lower technology nodes,
if the gate is connected directly to power/ground the transistor might be turned
on/off or damaged due to power/ground bounce. Hence Tie High and Tie Low cells
are used to connect Power/Ground to input pins of the standard cells. They act as
low pass RC filters and will filter out any high charge that could have potentially
damaged the thin gate oxide
After routing:

1. Filler cells:
- They reduce the DRC Violations created by the base(NWell, PPlus & NPlus) layers.
They help maintain the Power Rail connection continuity. Filler cells are used to
establish the continuity of the N- well and the implant layers on the standard cell
rows

2. Decap cells:

Decap cell is basically a capacitor cell which is used temporarily in the design
between power and ground rails to counter the functional failure.

-VENU KUMAR KARE

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