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Basics of Floorplan in IC Design

The document discusses floorplanning which is an initial stage of integrated circuit design where space is allocated for different functional blocks and components on the chip layout. It aims to optimize circuit performance, power, and area through determining location, shape and size of modules to avoid congestion. The document also defines full chip and block level floorplanning and their key considerations.

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durgaprasadkatakam66
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106 views5 pages

Basics of Floorplan in IC Design

The document discusses floorplanning which is an initial stage of integrated circuit design where space is allocated for different functional blocks and components on the chip layout. It aims to optimize circuit performance, power, and area through determining location, shape and size of modules to avoid congestion. The document also defines full chip and block level floorplanning and their key considerations.

Uploaded by

durgaprasadkatakam66
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Title: Understanding Basics of

Floorplan in Integrated Circuit


Design

Introduction: It's the initial stage where you allocate


space for different functional blocks and components on
the chip layout.

❖Floor Planning involves determining the location, shape,


and size of modules in a way that one can avoid
congestion.

✓ A good floorplan optimizes the circuit in terms of chip


area, total wire length, delay of critical paths, routability,
etc.

Definition of floorplanning in the context of IC design:


Floorplanning is the stage where we plan the positions and
shapes of the modules to optimize the performance of the circuit.

Purpose of floorplanning:
• Optimizing performance, power, and area

- Sonika M
Goals of Floorplan:
• Partition the design into functional
blocks
• Arrange the blocks on a chip
• Place the macros
• Decide the location of the I/O
pads and place them

Importance of early-stage
floorplanning in the design process:

Early-stage floorplanning
✓ Optimizes area usage
✓ Defines chip layout
✓ Facilitates hierarchical design
✓ Manages power distribution
✓ Supports design exploration
✓ Addresses signal integrity and timing closure
✓ Reduces the need for later design iterations.
✓ Allocating space efficiently and considering
critical factors upfront, designers can
➢ Minimize risks
➢ Enhance performance
➢ Lowers manufacturing cost

- Sonika M
Full Chip Floorplan
Definition of full chip floorplan: A full chip floorplan refers to
the comprehensive layout blueprint of an entire integrated circuit (IC)
design, encompassing the allocation of space for all functional blocks,
including logic, memory, and I/O interfaces, within the chip's core area.

Scope of full chip floorplanning: Arranging all functional


blocks and components on the chip's surface

Types of Floorplan:
1. Channeled / Non-Abutted Floorplan: Planning the floor
in such a way that we leave sufficient channel spacing between
macros/blocks while placing them.
• This spacing is for the tool to place the standard cells in a later
stage of placement and allocate a sufficient amount of routing
channels in further stages.
Spacing between Macros =
(No. of pins x Pitch)/Total no.of available routing layers

2. Abutted Floorplan: Here all blocks sit side by side without


any spacing in between them. It doesn’t allocate spacing for the
macro cell placement between the blocks.

- Sonika M
Key considerations in full chip floorplanning:

Conclusion:
• Full chip floorplanning is a crucial aspect of integrated circuit
design, enabling us to translate conceptual designs into physical
layouts optimized for performance and efficiency.

• The principles and techniques of full chip floorplanning can


contribute to the development of cutting-edge electronic devices
that shape the future of technology.

- Sonika M
Block Level Floorplan Explained

• Block-level floorplanning involves planning individual


functional blocks within an integrated circuit.
• This precedes full chip floorplanning, focusing on optimizing
block layout and placement to meet design requirements.
Key Considerations:

Tools and Techniques:


- Placement algorithms: Position blocks within the layout.
- Routing algorithms: Determine optimal interconnect paths.
- Floorplanning tools: Software for graphical interface and automation.

Conclusion: Block-level floorplanning is essential for optimizing


individual blocks within an integrated circuit.
• Understanding its principles helps streamline the overall design
process and achieve performance, power, and area efficiency
goals.

- Sonika M

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