CMOS Peripherals

CDP6853 Product Preview

fttil
C.O
2.
27
YDO
08 CMOS Asynchronous Communications
CIT 21 ilia
lIfl Interface Adapter (ACIA) with MOTEL Bus
.
2. 07
ft.c
XTLI
xno
2.

22
o.
.1

DO
F••tur••:
• Compatible with q-bit microprocessors
m
nJ" •
21
20
••
02 • Multiplexed Address/Data Bus (MOTEL Bus)
T •• 10 I. AOI • Full duplex operation with buffered receiver
1m! I. ADO
ft., ,."12 17 mr and transmitter
CE Ie 1m! • Data set/modem control functions
Yso
"
TOP Vl!W"
A' • Internal baud rate generator with 15
tics-non programmable baud rates (50 to 19,200)
TERMINAL ASSIGNMENT
• Operates at baud ra-tes up to 250,000 via
proper crystal or clock selection

The RCA-CDP6853 Asynchronous Communications Inter- • Program-selectable internally or externally

face Adapter (ACIA) provides an easily implemented, controlled receiver rate
program controlled interface between 8-bit microprocessor- • Programmable word lengths, number of stop bits,
based systems and serial communication data sets and and parity bit generation and detection
modems. • Programmable interrupt control
The CDP6853 has an Internal baud rate generator. This • Program reset
feature eliminates the need for multiple component support • Program-selectable serial echo mode
circuits, a crystal being the only other part required. The • Two chip selects
Transmitter baud rate can be selected under program • One chip enable
control to be either 1 of 15 different rates from 50 to 19,200 • Single 3V to 6V power supply
baud, or at 1/16 times an external clock rate. The Receiver • Full TTL compatibility
baud rate may be selected under program control to be • 4-MHz, 2-MHz, or 1-MHz operation
either the Transmitter rate, or at 1/16 times an external (CDP6853-4, CDP6853-2, CDP6853-1, respectively)
clock rate. The CDP6853 has programmable word lengths
of 5,6,7, or 8 bits; even, odd, or no parity; 1, 1'h, or 2 stop The Transmitter and Receiver Data Registers are used for
bits. temporary data storage by the CDP6853 Transmit and
The CDP6853Is designed for maximum programmed control Receiver circuits.
from the CPU, to simplify hardware implementation. Three The MOTEL Bus allows interfacing to 6805 and 8085 type
separate registers permit the CPU to easily select the multiplexed address data bus.
CDP6853 operating modes and data checking parameters
and determine operational status. The CDP6853-1, CDP6853-2, and CDP6853-4 are capable
of interfaCing with microprocessors with cycle times of 1-
The Command Register controls parity, receiver echo MHz, 2-MHz, and 4-MHz, respectively.
mode, transmitter interrupt control, the state of the RTS
line, receiver Interru pt control, and the state of the J5TR Ii ne. The CDP6853 Is supplied In 28-lead, hermetic, dual-in-line
side-brazed ceramic (0 suffix) and in 28-lead, dual-in-line
The Control Register controls the number of stop bits, word plastic (E suffix) packages.
length, receiver clock source, and baud rate.
The Status Register indicates the states of the IRO, DSR,
and i5Ci5' lines, Transmitter and Receiver Data Registers,
and Overrun, Framing and Parity Error conditions.

File Number 1487

612 _________________________________________________________________
 CMOS Peripherals

CDP6853
MAXIMUM RATINGS, Absolute-Maximum Value.:
DC SUPPLY-VOLTAGE RANGE. (Voo)
(Voltage referenced to VI. tarmlnal) ....................................................................................-0.5 to +7 V
INPUT VOLTAGE RANGE. ALL INPUTS .......................................................................... -0.5 to Voo +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ................................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po):
For T.=-40 to +80" C (PACKAGE TYPE E) ................................................................................ 500 mW
For T.=+80 to +85·C (PACKAGE TYPE E) ................................................... Derate Linearly at 8 mW/·C to 300 mW
ForT.=-55 to +1000C (PACKAGE TYPE D) ............................................................................... 500 mW
ForT.=+100to 126·C (PACKAGE TYPE D) .................................................. Derate Linearly at 8 mW/·C to 300 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For T.=FULL PACKAGE-TEMPERATURE RANGE (All Package Type.) .................................................... 100 mW
OPERATING-TEMPERATURE RANGE (T.):
PACKAGE TYPE 0 ............................................................................................... -55 to +125·C
PACKAGE TYPE E ................................................................................................ -40 to +85· C
STORAGE-TEMPERATURE RANGE (TOIl) ........................................................................... -85 to +1500 C
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/18 ± 1132 In. (1.59 ± 0.79 mm) from case for 10. max. .. ................................................... +285·C

RECOMMENDED OPERATING CONDITIONS at T. = -40· to +85°C

For maximum r.llabillty, nominal operating condlDonl Ihould b. Hlected 10 that operation II IlwaYI
within the following rangn:

DC ODlratlna Voltaae Ranae

CHARACTERISTIC
Min.
3
LIMITS
I
I
Max.
6
UNITS lEI
V
Input Voltaae Ranae V.. I V....

STATIC ELECTRICAL CHARACTERISTICS aIT.=-40· 10+8So C, Voo = S V ± 50ft

LIMITS
CHARACTERISTIC UNITS
Min. Typ. Max.
Quiescent Device Current 100 - 50 200 IIA
Output Low Current (Sinking): VOL = 0.4 V 10L
(00-07. TxO. RxC. RTS. DTR. IRQ)
1.6 - - mA

Output High Current (Sourcing): VOH = 4.6 V 10H

(00-07. TxO. RxC. FiTs. OTR)
-1.6 - - mA

Output Low Voltage: iLOAO = 1.6 mA VOL

(00-07. TxD. RxC. RTS. DTR. IRQ)
- - 0.4 V
Output High Voltage: iLOAO = -1.6 mA VOH
4.6 - - V
(00-07. TxO.RxC.RTS.OTR)
Input Low Voltage V,L V•• - 0.8 V
Input High Voltage V,H
(Except XTLI and XTLO) 2 - Voo
V
(XTLland XTLO) 3 - Voo
Input Leakage Current: V,N = 0 to 5 V ioN
(RiW. RES. CSO. CS1. CEo OS. AS. CTS. RxD. DCD. DSR)
- - ±1 pA

Input Leakage Current for Hiah Impedance State (00-07) iT., - - ± 1.2 pA
Output Leakage Current (off state): VOUT = 5 V (mo) 10FF - - 2 IIA
Input Capacitance (except XTLI and XTLO) C'N - - 10 pF
Output Capacitance COUT - - 10 pF

_______________________________________________________________________________ 813
CMOS Peripherals

CDP6853
CDP8853 INTERFACE REQUIREMENTS D2-D7 (Da" BUI) (20-25)
This section describes the interface requirements for the The 02-07 pins are the eight data lines used to transfer data
CDP6853 ACIA. Fig. 1 Is the Interface Diagram and the between th4;l processor and the CDP6853. These lines are
Terminal Diagram shows the pin-out configuration for the bi-directional and are normally high-impedance except
CDP6853. during Read cycles when the CDP6853 is selected.
CE, cso,Cii (Chip Seleetl) (2,3,13)
The two chip select and the one chip enable inputs are
02-07 CTs normally connected to the processor address lines either
AOO.A01 directly or through decoders. The CDP6853 is selected
when CSO is high, CSi is low, and CE is high.
TxD
ADO, AD1 (Multiplexed Bidirectional Addres./Da" Bltl)
(18,19)
Multiplexed bus processors save pins by presenting the
6CO address during the first portion of the bus cycle and using
IiSR the same pins during the second portion for data. Address-
then-data multiplexing does not slow the access time of the
RxC CDP6853 since the bus reversal from address to data is
XTLI occurring during the Internal RAM access time.
XTLO
The address must be valid just prior to the fall of AS/ALE at
which time the CDP6853 latches the address from ADO to
AD1. Valid write data must be presented and held stable
during the latter portion of the OS or'WR pulses. In a read
OTR cycle, the CDP6853 outputs 8 bits of data during the latter
FiTs portion of the OS or RD pulses, then ceases driving the bus
(returns the output drivers to three-state) when OS falls in
this case of MOTEL or RD rises in the other case. The
RxD following table shows internal register select coding:
TABLE I

AD1 ADO Write Read

0 0 Transmit Data Receiver Data
92CM-37024 Register Register
0 1 Programmed Reset Status Register
Fig. 1 - CDP6853 Interface diagram. (Data Is "Don't
Care")
MICROPROCESSOR INTERFACE 1 0 Command Register
SIGNAL DESCRIPTION 1 1 Control Register
RES (R.let) (4)
Only the Command and Control registers are read/write.
During system initialization a Iowan the RES input will The programmed Reset operation does not cause any data
cause a hardware reset to occur. The Command Register transfer, but is used to clear bits 4 through 0 in the
and the Control Register will be cleared. The Status Command register and bit 2 in the Status register. The
Registerwill be cleared with the exception of the indications Control Register is unchanged by a Programmed Reset. It
of Data Set Ready and Data Carrier Detect, which are should be noted that the Programmed Reset is slightly
externally controlled by the i5SR and BCD lines, and the different from the Hardware Reset (RES); these differences
transmitter Empty bit, which will be set. A hardware reset is are shown in Figs. 4, 5, and 6.
required after power-up.
ACIA/MODEM INTERFACE
R/ii (R.ad/Wrlte) (1) SIGNAL DESCRIPTION
The MOTEL circuit treats the R/W pin in one of two ways. XTLI, XTLO (Crystal Plnl) (8,7)
When a 6805 type processor is connected, R/W is a level These pins are normally directly connected to the external
which indicates whether the current cycle is a,!!ad or write. crystal (1.8432 MHz) used to derive the various baud rates
A read cycle is indicated with a high level ollfl/W while OS is (see "Generation of Non-Standard Baud Rates"). Alter-
high, whereas a write cycle is a Iowan R/W during OS. natively, an externally generated clock may be used to drive
The secondJEt~retati~R/W is as a negative write theXTLI pin, in which case the XTLO pin must float. XTLI is
pulse, 'WR, , and I/OW from competitor .!}pe pro- the input pin for the transmit clock.
cessors. The MOTEL circuit in this mode gives RlW pin the TxD (Tranlmlt Data) (10)
same meaning as the write (W) pulse on many generic
RAMs. The TxD output line is used to transfer serial NRZ
(nonreturn-to-zero) data to the modem. The LSB (least
iRQ (Interrupt Requelt) (28) significant bit) of the Transmit Data Register is the first data
The IRQ pi n Is an interrupt output from the interrupt control bit transmitted and the rate of data transmission is
logic. It is an open drain output, permitting several devices determined by the baud rate selected or under control of an
to be connected to the common-mtr microprocessor Input. external clock. This selection is made by programming the
Normally a high level, TRO goes low when an interrupt Control Register.
occurs.
614 _________________________________________________________________
 CMOS Peripherals

CDP6853
CDP8863 INTERFACE REQUIREMENTS (Confd)
RxD (Receive Date) (12) The second MOTEL Interpretation of OS is that of RD,
The RxD input line is used to transfer serial NRZ data into MEMR, or i70ifemanatlng from an 8085 type processor. In
this case, OS Identifies the time period when the real-time
the ACIA from the modem, LSB first. The receiver data rate
Is either the programmed baud rate or under the control of clock plus RAM drives the bus with read data. This
an externally generated receiver clock. The selection is interpretation of OS Is also the same as an output-enable
made by programming the Control Register. signal on a typical memory.
RxC (Receive Clock) (5) The MOTEL circuit, within the CDP6853 latches the state of
the OS pin on the falling edge of AS/ALE. When the 8800
The RxC Is a bi-dlrectional pin which serves as either the mode of MOTEL is desired OS must be low during AS! ALE,
receiver l6x clock Input or the receiver l6x clock output. which is the case with the CDP6805 family of multiplexed
The latter mode results If the internal baud rete generator is bus processors. To insure the 8065 mode of MOTEL, the OS
selected for receiver data clocking. pin must remain high during the time AS/ALE Is high.
RTs (Reque.t to Send) (8) AS (Multiplexed Addreu Strobe) (15)
The RTS output pin is used to control the modem from the A positive-going multiplexed address strobe pulse serves to
processor. The state of the lfm' pin is determined by the demultiplex ADO and AD1. The falling edge of AS or ALE
contents of the Command Register. causes the address to be latched within the CDP6853. The
CTS (Clear to Send) (t) automatic MOTEL circuitry in the CDP6853 also latches the
state of the OS pin with the failing edge of AS or ALE.
The CTS input pin is used to control the transmitter
operation. The enable state is with CTS low. The transmitter
is automatically disabled if CTS is high.
DTR (Da" Terminal Ready) (11)
MOTEL
This output pin is used to indicate the status of the CDP6853
to the modem. A low on "fii'R Indicates the CDP6853 is The MOTEL circuit is a new concept that permits the
enabled, a high Indicates it is disabled. The processor CDP6853 to be directly Interfaced with many types of
controls this pin via bit 0 of the Command Register. microprocessors. No external logiC is needed to adapt to
the differences in bus control signals from common
DSR (Da" Set Ready) (17) multiplexed bus microprocessors.
The DSR input pin is used to Indicate to the CDP6853 the
Practically all microprocessors interface with one of two
status of the modem. A low Indicates the "ready" state and a
synchronous bus structures.
high, "not-ready".
The MOTEL circuit is built Into peripheral and memory ICs
DCD (Da" carrier Detect) (18)
to permit direct connection to either type of bus. An
The DCD Input pin is used to indicate to the CDP6853 the Industry-standard bus structure is now available. The
status of the carrier-detect output of the modem. A low MOTEL concept is shown logically In Fig. 2.
indicates that the modem carrier signal is present and a
MOTEL selects one of two interpretations oftwo pins. In the
high, that It is not.
6805 case, OS and R/W are gated together to produce the
DS (Data Strobe or Rnd) (27) internal read enable. The internal write enable is a similar
The OS pin has two interpretations via the MOTEL circuit. gating of the inverse of RlW. With 8085 Family buses, the
When emanating from a 6800 type processor, OS Is a inversion of RD and WR create functionally identical internal
positive pulse during the latter portion ofthe bus cycle, and read and write enable Signals.
is variously called OS (data strobe), E (enable), and ~2 (~2 The CDP6853 automatically selects the p!Qcessor type by
clock). During read cycles, OS signifies the time that the usi ng AS/ALE to ~h the state of the DS/R 0 pin. Since OS
ACIA is to drive the bidirectional bus. In write cycles, the Is always low and RD is always high during AS and ALE, the
trailing edge of OS causes the ACIA to latch the written latch automatically Indicates which processor type Is
data. connected.

~
• '00
FAMILY TYPE
808•
FAMILY TYPE
MPU SIGNALS
CDP..53
.!!!!.!!!!!!!:! D
........
FAMILY 8US
al------.
INTERNAL
SIGNALS

FAMILY
AS ALE AS \---+.., C Q BUS

OS, E,or02 DS READ ENABLE

RIW R'W WRITE ENABLE

12C1I471111

Fig. 2 - Functional diagram of MOTEL circuit.

_______________________________________________________________ 615
CMOS Peripherals

CDP6853
CDP8853 INTERNAL ORGANIZATION
This section provides a functional description of the
CDP6853. A block diagram of the CDP6853 is presented In
Fig. 3.
eTS

D2·D7 TxD
ADO,AD1

oeD
DSR

Rxe
XTLI
XTLO

DTR

iiTs

RxD

92CM-37026Rl

Fig. 3 - Internal organization.

DATA BUS BUFFERS Bus Buffer, and the microprocessor data bus, and the
The Data Bus Buffer interfaces the system data lines to the hardware reset features.
internal data bus. The Data Bus Buffer is bi-directional. Timing is controlled by the system 1/12 clock input. The chip
When the R/Wline is high and the chip is selected, the Data will perform data transfers to or from the microcomputer
Bus Buffer passes the data to the system data lines from the data bus during the 1/12 high period when selected.
CDP6853 internal data bus. When the R/W line is low and All registers will be initialized by the Timing and Control
the chip is selected, the Data Bus Buffer writes the data from Logic when the Reset (RES) line goes low. See the individual
the system data bus to the internal data bus. register description for the state of the registers following a
INTERRUPT LOGIC hardware reset.
The Interrupt Logic will cause the IRQ line to the micro- TRANSMITTER AND RECEIVER
processor to go low when conditions are met that require DATA REGISTERS
the attention of the microprocessor. The conditions which These registers are used as temporary data storage for the
can cause an interrupt will set bit 7 and the appropriate bit of CDP6853 Transmit and Receive Circuits. Both the Trans-
bits 3 through 6 in the Status Register if enabled. Bits 5 and 6 mitter and Receiver are selected by a Register Select 0
correspond to the Data Carrier Detect (DCDi logic and the (RSO) and Register Select 1 (RS1) low condition. The
Data Set Ready (DSR) logic. Bits 3 and 4 correspond to the Read/Write line determines which actually uses the internal
Receiver Data Registerfull and the Transmitter Data Register data bus; the Transmitter Data Register is write only and the
empty conditions. These conditions can cause an interrupt Receiver Data Register is read only.
request if enabled by the Command Register.
Bit 0 is the first bit to be transmitted from the Transmitter
I/O CONTROL Data Register (least significant bit first). The higher order
The I/O Control Logic controls the selection of internal bits follow in order. Unused bits in this register are "don't
registers in preparation for a data transfer on the internal care".
data bus and the direction of the transfer to or from the The Receiver Data Register holds the first received data bit
register. in bit 0 (least significant bit first). Unused high-order bits
The registers are selected by the Register Select and Chip are "0". Parity bits are not contained in the Receiver Data
Select and Read/Write lines as described in Table I, Register. They are stripped off after being used for parity
previously. checking.
TIMING AND CONTROL STATUS REGISTER
The Timing and Control logic controls the timing of data Fig. 4 indicates the format of the CDP6853 Status Register.
transfers on the internal data bus and the registers, the Data A description of each status bit follows.

616 _________________________________________________________________
 CMOS Peripherals

COP68S3
COP8853 INTERNAL ORGANIZATION (Cont'd)
78543210
I I I I I II I I CONTROL REGISTER
The Control Register selects the desired transmitter baud

L
PARITY ERRO...
0- NO PARITY ERROR rate, receiver clock source, word length, and the number of
1 - PARITY ERROR DETECTED stop bits.
FRAMING ERROR"
0- NO FRAMING ERROR Selected Baud Rate (Bltl 0,1,2,3)
1 - FRAMING ERROR DETECTED
These bits, set by the processor, select the Transmitter
' - - - OVERRUN"
0- NO OVERRUN
baud rate, which can beat 1/16 an external clock rate orone
1 - OVERRUN HAS OCCURRED of 15 other rates controlled by the internal baud rate
RECEIVER DATA REGISTER FULL generator as shown in Fig. 5.
0- NOT FULL
1 - FULL

TRANSMITTER DATA REGISTER EMPTY

0- NOT EMPTY
1- EMPTY 7 8 5 4 3

ISBN~RCS SSR
sa"
DATA CARRIER DETECT (DCD) SBR2 S8Rl BBRO
0- iX5 LOW (DETECll
1- 6eD HIGH (NOT DETECTED) L..J
DATA seT READV

~: 8B ~~:H(r:~~EADV)
(liP)
L___ SELECTED BAUD RATE ISBA)
3210
0000 1/,8X EXTERNAL CLOCK
INTERRUPT (IAQ) 0001 50 BAUD

~ ::'~~~~~Ap~U~~':c'~:;~:~1.m PIN LOW)

0010 75 BAUD
0011 10892 BAUD
0100 134.58 BAUD
"NO INTERRUPTS OCCUR FOR 0101 150 BAUD
THESE CONDITION8 0110 300 BAUD
78543210 0111 800 BAUD

I~ 1:1: I:I~ I~ I~I~I::::::~:::~T (RES)

HCU-1I713R1
1000
1001
1010
1200
1800
2400
BAUD
BAUD
BAUD
1011 3800 BAUD
1100 4800 BAUD
Fig. 4 - Status ragistar format. 1101 7200 BAUD
1110 9800 BAUD
1111 19200 BAUD

' - - - - - - - - RECEIVER CLOCK SOURCE (RCS)

Receiver Data Regllter Full (Bit 3) 0- EXTERNAL RECEIVER CLOCK
1 - BAUD RATE
This bit goes to a "1" when the CDP6853 transfers data from
' - - - - - - - - - - - WORD LENGTH (WL)
the Receiver Shift Register to the Receiver Data Register, U
and goes to a "0" when the processor reads the Receiver 00 8 BITS
01 7 BITS
Data Register. 10 BBITS
11 5 BITS
TranlmlHer Date Regllter Empty (Bit 4)
' - - - - - - - - - - - - - - STOP BIT NUMBER ISBN)
This bit goes to a "1" when the CDP6853 transfers data from 78543210
0-1 STOP BIT
1 - 2 STOP BITS
the Transmitter Data Register to the Transmitter Shift 10 10 10 10 \0 10- 10- - 10-
IHARDWARE RESET(iiEi) - ' .... /2 STOP BITS
FOR WL=5 AND NO PARITY
Register, and goes to a "0" when the processor writes new - - - - PROGRAM RESET
-1 STOP BIT
data onto the Transmitter Data Register. FOA WL 8 AND PARITY

Date Carrier Detect (Bit 5) and 92CM- 36781

Date Set Ready (Bit 8)
These bits reflect the levels of the DCD and DSR inputs to
the CDP6853. A "0" indicates a low level (true condition) Fig. 5 - CDP6853 control raglster.
and a "1" indicates a high (false). Whenever either of these
inputs change state, an immediate processor interrupt
occurs, unless the CDP6853 Is disabled (bit 0 of the
Command Regil!ter is a "0"). When the Interrupt occurs, the
status bits will Indicate the levels of the inputs immediately Receiver Clock Source (Bit 4)
after the change of state occurred. Subsequent level This bit controls the clock source to the Receiver. A "0"
changes will not affect the status bits until the Status causes the Receiver to operate at a baud rate of 1/16 an
Register is interrogated by the processor. At that time, external clock. A "1" causes the Receiver to operate at the
another Interrupt will immediately occur and the status bits same baud rate as Is selected for the transmitter as shown in
will reflect the new input levels. Fig.5.
Framing Error (Bit 1), Overrun (2), and Word Length (Bltl 5,8)
Parity Error (Bit 0) These bits determine the word length to be used (5,6,7 or 8
None of these bits causes a processor interrupt to occur, bits). Fig. 5 shows the configuration for each number of bits
but they are normally checked at the time the Receiver Data desired.
Register is read so that the validity of the data can be Stop Bit Number (Bit 7)
verified.
This bit determines the number of stop bits used. A "0"
Interrupt (Bit 7) always indicates one stop bit. A "1" indicates 1'h stop bits If
This bit goes to a "0" when the Status Register has been the word length is 5 with no parity selected, 1 stop bit if the
read by the processor, and goes to a "1" whenever any kind word length is 8 with parity selected, and 2 stop bits in all
of interrupt occurs. other configurations.

_________________________________________________________________ 617
CMOS Peripherals

CDP6853
CDP6853 INTERNAL ORGANIZATION (Cont'd)

COMMAND REGISTER Parity Mode Control (Bits 6,7)

The Command Register controls specific modes and These bits determine the type of parity generated by the
functions (Fig. 6). Transmitter, (even, odd, mark or space) and the type of
Data Terminal Ready (Bit 0) parity check done by the Receiver (even, odd, or no check).
Fig. 6 shows the possible bit configurations for the Parity
This bit enables all selected interrupts and controls the Mode Control bits.
state of the Data Terminal Ready (DTR) line. A "0" indicates
the microcomputer system is not ready by setting the DTR TRANSMITTER AND RECEIVER
line high. A "1" indicates the microcomputer system is Bits 0-3 of the Control Register select divisor used to
ready by setting the DTR line low. When the DTR bit issetto generate the baud rate for the Transmitter. If the Receiver
a "0", the receiver and transmitter are both disabled. clock is to use the same baud rate as the transmitter, then
Receiver Interrupt Control (Bit 1) RxC becomes an output and can be used to slave other
circuits to the CDP6853. Fig. 7 shows the transmitter and
This bit disables the Receiver from generating an interrupt Receiver layout.
when set to a "1". The Receiver interrupt is enabled when
this bit is set to a "0" and Bit 0 is set to a "1".
Transmitter Interrupt Control (Bits 2,3)
These bits control the state of the Ready to Send (RTS) line
and the Transmitter interrupt. Fig. 6 shows the various
configurations of the RTS line and Transmit Interrupt bit
settings.
Receiver Echo Mode (Bit 4) ~----------------------R'C

This bit enables the Receiver Echo Mode. Bits 2 and 3 must
also be zero. In the Receiver Echo Mode, the Transmitter XTLr
returns each transmission received by the Receiver delayed XTLO
by'h bit time. A "1" enables the Receiver Echo Mode. A "0"
bit disables the mode.
Parity Mode Enable (Bit 5)
This bit enables parity bit generation and checking. A "0"
disables parity bit generation by the Transmitter and parity 92CS-36791
bit checking by the Receiver. A "1" bit enables generation Fig. 7 - Transmitter receiver clock circuits.
and checking of parity bits.

DATA TERMINAL READY (OTR)

0- DATA TERMINAL NOT READY (OTR PIN HIGH)
1 - DATA TERMINAL READY (OTR PIN LOW)
RECEIVER INTERRUPT CONTROL (IRD)
0" RECEIVER INTERRUPT ENABLED
1 - RECEIVER INTERRUPT DISABLED

' - - - - - - TRANSMITTER INTERRUPT CONTROL (TIC)

3 2
00 rn-
HIGH. TRANSMIT INTERRUPT DISABLED*
o1 m-LOW, TRANSMIT INTERRUPT ENABLE
1 0 m-LOW, TRANSMIT INTERRUPT DISABLED
1 1 R'i'§ - LOW, TRANSMIT INTERRUPT DISABLED
TRANSMIT BREAK ON T x 0

' - - - - - - - - - - RECEIVER ECHO MODE (REM)

0- RECEIVER NORMAL MODE
1 - RECEIVER ECHO MODE*

' - - - - - - - - - - - - PARITY MODE ENABLE (PME)

0- PARITY MODe DISABLED
NO PARITY BIT GENERATED
PARITY CHECK DISABLED
1 - PARITY MODE ENABLED

' - - - - - - - - - - - - - - PARITY MODE CONTROL (PMC)

7 •
6 i5 ODD PARITY TRANSMITTED/RECEIVED
76543210
1°\° 10 \ ° \0 I
0 10 \0 \ 0 HARDWARE RESET (RES) 1
°°
1 EVEN PARITY TRANSMITTED/RECEIVED
MARK PARITY BIT TRANSMITTED
- - - 0 0 0 0 PROGRAM RESET PARITY CHECK DISABLED
1 1 SPACE PARITY BIT TRANSMITTED
PARITY CHECK DISABLED

* BITS 2 AND 3 MUST BE ZERO FOR RECEIVER ECHO MODE fiTS WILL BE LOW.

92CM-36790A1

Fig. 6 - CDP6853 command register.

618
 CMOS Peripherals

CDP6853
CDPSSS3 OPERATION (Cont'd)

TRANSMITTER AND RECEIVER OPERATION

Continuous Data Transmit (Fig. 8) the Status Register of the CDP6853, the interrupt is cleared.
The processor must then identify that the Transmit Data
l!!..J!Ie normal operating mode, the processor interrupt
Register is ready to be loaded and must then load it with the
(I Ra) is used to signal when the CDP6853 is ready to accept
next data word. This must occur before the end of the Stop
the next data word to be transmitted. This interrupt occurs
Bit, otherwise a continuous "MARK" will be transmitted.
at the beginning of the Start Bit. When the processor reads

CHAR#n CHAR#n+l CHAR#n+2 CHAR#n+3

/ I '-/ I '-/ I ,~' ~

T"'...,._..,.~T:.::O::;P STOP STOP STOP

Tx ol [BOIBtJ1~diJ I GGCGE] I GG1]:£1 I [%G[:GI:] L

Lm'-c
START STAR'r START START

I Lm
I I I I
I I I I

iRO -un PROCESSOR

INTERRUPT /
J PROCESSOR MUST
Lw L
(TRANSMIT OATA LOAD NEW DATA
REGISTER EMP"rY) IN THIS TIME
INTERVAL; OTHERWISE,
CONTINUOUS "MARK"
IS TRANSMITTEO
PROCESSOR READS STATUS 92CM·36792R1

III
REGISTER, CAUSES IRQ
TO CLEAR

Fig. 8 - Continuous data transmit.

Continuoul Data Receive (Fig. 9) data word. This occurs at about the 8/16 point through the
Stop Bit. The processor must read the Status Register and
Similar to the above case, the normal mode is to generate a read the data word before the next interrupt, otherwise the
processor interrupt when the CDP6853 has received a full Overrun condition occurs.

CHAR#n CHAR#n-t-1 CHAR#I"+2 CHAR#n+3

/~ __----~I--------~,/ ~/ ~/r--------~I--_----~,
'T""-r_,SrT"o""p STOP STOP STOP

Rx D l [%IB1I:8O:J I I [BO"Gf~~ I [BO'Er ~ I [BOIBtJ hE] I L

)I
START START I START I START
I : i I

U' 1 /LJJJ JLJlj.,,------1L

=:girv~SRO~A~~~~ ~~~f
TIME INTERVAL; OTHERWISE,
PROCESSOR OVERRUN OCCURS
INTERRUPT OCCURS
ABOUT 8/18 INTO 92CM-38793R1
LAST STOP BIT.
PARITY, OVERRUN,
AND FRAMING ERROR
UPDATED, ALSO

PROCESSOR READS STATUS

REGISTER, CAUSES IRQ
TO CLEAR

Fig. 9 - Continuous data receive.

------------------------_______________________________________ 619
CMOS Peripherals

CDP6853
CDP6853 OPERATION (Cont'd)
Transmit Data Register Not Loaded continue to occur at the same rate as previously, except no
By Processor (Fig. 10) data is transmitted. When the processor finally loads new
If the processor is unable to load the Transmit Data Register data, a Start Bit immediately occurs, the data word
in the allocated time, then the TxD line will go to the transmission is started, and another interrupt is initiated,
"MARK" condition until the data is loaded. IRQ interrupts signaling for the next data word.

CHAR #n CONTINUOUS "MARK" CHAR#n+1 CHAR #n+2

/~ ________LI________~,
/~--------~------~,/~------~I----------

TxO n STOP

[qii1T-0EE]
STOP

I rq;;;J~:EEI
START
STOP

IJ"TARTreELEr
I START LCHARACTER1
1- TIME
I'TT"---

PROCESSO'I
INTERRUPT
FOR DATA WHEN PROCESSOR FINALLY LOADS
REGISTER INTERRUPTS NEW DATA, TRANSMISSION STARTS
EMPTY CONTINUE AT IMMEDIATELY AND INTERRUPT
CHARACTER RATE OCCURS, INDICATING TRANSMIT
PROCESSOR EVEN THOUGH DATA REGISTER EMPTY
READS NO DATA IS 92CM-36794RI
STATUS TRANSMITTED
REGISTER

Fig. 10 - Transmit data register not loaded by processor.

Effect of CTS on Transmitter (Fig. 11) continue at the same rate, but the Status Register does not
indicate that the Transmit Data Register is empty. Since
CTS is the Clear-to-Send Signal generated by the modem. there is no status bit for CTS, the processor must deduce
It is normally low (True State) but may go high in the event that CTS has-ille to the FALSE (high) state. This is
of some modem problems. When this occurs, the TxD line covered later. CTS isa transmit control line only, and has no
immediately goes to the "MARK" condition. Interrupts effect on the CDP6853 Receiver Operation.

CHAR#n CHAR#n+1 CONTINUOUS "MARK"

______~I----------__,/r--~::~::~I:;::~:::;:::" I

Tx DE~_.I_B_N
. ......_p--,lsTOPlsTARTI Be S_T_O_pl~S_TA_R_T.LI_B°-.LI_Bl-.L1_B2-1:/
I:J _...I_B_N.....I_p...I...

I I I'TT"'---I-"'"
~ CHARACTER--I
I TIME I

NOT CLEAR-T()'SEND

ClEAR-T(),SEND

ffi_",~
INDICATING MODEM

~E~~~V~~A:"~~~x D
PROCESSOR

~~T:~=~~
PROCESSOR READS
STATUS REGISTER.
SINCE DATA REGISTER
IS r:!QI EMPTY, PROCESSOR
IMMEDIATELY GOES START BIT MUST DEDUCE THAT
TO "MARK" CONDITION TIME eft IS SOURCE OF
INTERRUPT (THIS IS
COVERED ELSEWHERE
IN THIS NOTE).

92CM-36795

Fig. 11 - Effect of CTS on transmitter.

620
 CMOS Peripherals

CDP6853
CDP8853 OPERATION (Cont'd)

Effect of Overrun on Receiver (Fig. 12)

If the processor does not read the Receiver Data Register in Data Register, but the Overrun status bit is set. Thus, the
the allocated time, then, when the following interrupt Data Register will contain the last valid data word received
occurs, the new data word is nottransferred to the Receiver and all following data Is lost.

CHAR#n CHAR#n+1 CHAR#n+2 CHAR#n+3

--'v ' 'J ' ,/ ' ,/,------"---
STOP STOP STOP STOP

Rx D n Grs~[8O:] I GG[(gi] I [801~]~EJ I GFT]~I

I~ I~ I~ I~
rn-----
RECEIVER DATA REQISTER
NOT UPDATED BECAUSE
PROCESSOR DID NOT READ
PREVIOUS DATA. OVERRUN
BIT SET IN STATUS
REGISTER.

~OVERRUN BIT SET IN

lEI
'-----.-----'
STATUS REGISTER

92CM-36796R I

Fig. 12 - Effect of overrun on receiver.

Echo Mode Timing (Fig. 13)

In Echo Mode, the TxD line re-transmits the data on the RxD
line, delayed by 'h of the bit time.

RxD nSTARTI I ., I ~
Be

TxD
\\\\
92CM- 36797

Fig. 13 - Echo mode timing.

_________________________________________________________________ 621
CMOS Peripherals

CDP6853
CDP8853 OPERATION (Cont'd)

Effect of CTS on Echo Mode Operation (Fig. 14) way as "Effect of C'F§ on Transmitter". In this case,
See "Effect of CTS on Transmitter" for the effect of CTS on however, the processor interrupts signify that the Receiver
the Transmitter. Receiver operation is unaffected by CTS, Data Register is full, so the processor has no way of
so, in Echo Mode, the Transmitter is affected in the same knowing that the Transmitter has ceased to echo.

CHAR#n CHAR#n+1 CHAR#n+2 CHAR#n+3

--_\/ I 'j I 'j I 'J I
STOP STOP STOP STOP

R,O Jl G"GIHJ I [SJBtJ~:GEJ I [%GIOGOEJ I SEtH

1- 1- I~ 1-
nIQLJI] LllJ Llll UU......----
Nor·CLEAR-rO·SEND
!
I
I

)
STOP STOP

hO
~L.I~EI ISNI p I Isols,I··11
L~
[ CTS GOES TO
"FALSE" CONDITION

NORMAL
RECEIVER DATA
REGISTER FULL
INTERRUPTS
--~

92CM-36798

Fig. 14 - Effect of CTS on echo mode,

Overrun In Echo Mode (Fig. 15) For the re-transmitted data, when overrun occurs, the TxD
If Overrun occurs in Echo Mode, the Receiver is affected the line goes to the "MARK" condition until the first Start Bit
same way as described in "Effect of Overrun on Receiver", after the Receiver Data Register is read by the processor,

CHAR#n CHAR #x CHAR #x +1

/~ _ _ _-LI_ _ _ _ ~~ _ _LI_ _ _
~/r--------JI--_~

A'O1-
n r;E[EL:] -I GELID
STOP STOP STOP

I
~
[%G[~
STOP

I
~
[%EII~;E

-- LJl]\~--.--_/LJ] !l!---'LllJ LJ]mr-----

IAQ ISTOP 1 1"-'r--r_-~!----''-- - _- _- _~~---- _- _- _~-/+-i
TxO nI 83 ~
START
'--L_......8_,...
1;-
~H
PROCESSOR FINALLY
PROCESSOR
~~~E:~g~VER I READS RECEIVER
E:~~ ::~~STER, Tx D DATA
DATA REGISTER CHARACTER (#n) RESUMES
FULL I OVERRUN OCCURS PROCESSOR
T x D GOES TO INTERRUPT
PROCESSOR "MARK" FOR CHAR#x
READS CONDITION IN RECEIVER
STATUS DATA REGISTER
REGISTER
92CM-36788

Fig, 15 - Overrun in echo mode,

622 _______________________________________________________________
 CMOS Peripherals

CDP6853
CDPelS3 OPERATION (Cont'd)

Fremlng Error (Fig. 18) interrupt occurs. Subsequent data words are tested for
Framing Error is caused by the absence of Stop Blt(s) on Framing Error separately, so the status bit will always
received data. The status bit is set when the processor reflect the last data word received.

O.D
(EXPECTED)

O.D
(ACTUAL)

NOTES
PRoctSSOR
1 FRAMING ERROR DOES NOT INTERRUPT,
INHIBIT RECEIVER OPERATION FRAMING
2 IF NEXT DATA WORD 18 OK. ERROR
FRAMING ERROR IS CLEARED 81T8ET

Fig. 16 - Framing error.

92CM- 36789

III
Effect of DCD on Receiver (Fig. 17) condition via the Status Register.
DcD is a modem output used to indicate the status of the Once such a change of state occurs, subsequent transitions
carrier-frequency-detectlon circuit of the modem. This line will not cause interrupts or changes in the Status Register
goes high for a loss of carrier. Normally, when this occurs, until the fi rst interrupt is serviced. When the Status Register
the modem will stop transmitting data (RxD on the CDP6853 is read by the process.2!:.....the CDP6853 automatically
some time later. The CDP6853 will cause a processor checks the level of the DCD line, and if it has changed,
interrupt wheneveroco changes state and will indicate this another interrupt occurs.

~-r~rST~D;P ~-r-'r-'-r-____C~O~N~T~IN~U~OU~S~"~M~A~OK~"____-'rrS~TO~P STOP

O.D ·EB~:bEJ I 1·0 I·, 1··11 8 I [BOGI _GEJ L

START I MODEM I I- MODEM -t STAOT
r DELAY 1 I DELAV I
I I
DCD
I ~I- - - - - + - - - + -
loa ~rc'==:::;:::t==::7j/LW iii
IL __1U
III

t
:~~~E"sLSOR
INTERRUPT
I
PROCESSOR
f AS LONG AS
~F~R~~E~
INTERRUPTS
PROCESSOR
t
NO INTERRUPT
WILL OCCUR
/L
PROCESSOR
HERE, SINCE INTERRUPT
INTERRUPT FOR RECEIVER INTERRUPT RECEIVER IS NOT FOR
FOR 6C6 WILL OCCUR FOR m!IS ENABLED UNTIL RECEIVER
GOING HIGH GOING LOW DATA
FIRST START BIT
DETECTED

92CM-36786

Fig. 17 - Effect of OeD on receiver.

____________________________________________________________ 623
CMOS Peripherals

CDP6853
CDP6853 OPERATION (Cont'd)

Timing with 1'12 Stop Bit. (Fig. 18) 5-bit data words with no parity bit. In this case, the
processor interrupt for Receiver Data Register Full occurs
It is possible to select 11,1, Stop Bits, but this occurs only for halfway through the trailing half-Stop Bit.
CHAR#n CHAR#n+1
/,~____________-LI____________~ I

AxC

LllJ L
t
PROCESSOR INTERRUPT
OCCURS HALFWAY 92CM- 36787
THROUGH THE 1!2
STOP BIT

Fig. 18 - Timing with 1-1/2 stop bits.

Tran.mlt ContinuoU8 "BREAK" (Fig. 19)

This mode is selected via the CDP6853 Command Register When the Command Register is programmed back to
and causes the Transmitter to send continuous "BREAK" normal transmit mode, a Stop Bit is generated and normal
characters after both the transmitter and transmitter-holding transmission continues.
registers have been emptied.

/~----------~,~-----

TKO n STOP

ISTART
~~I3iJ
STOP

I I BO

START
81! _ aN p STOP
STOP

~GEJ
STOP

II R"81J
START

ITT"-----...;

1-------------1- PERIOD DURING

WHICH PROCESSOR
SELECTS
CONTINUOUS
POINT AT
PROCESSOR
WHI~ PROCESSOR
/

NORMAL SELECTS INTERRUPT

INTERRUPT "BREAK" MODE
NORMAL TO LOAD
TRANSMIT TRANSMIT
MODE DATA

92CM-36785

Fig. 19 - Transmit continuous "BREAK".

Receive Contlnuou8 "BREAK" (Fig. 20) characters, the CDP6853 will terminate receiving. Reception
will resume only after a Stop Bit is encountered by the
In the event the modem transmits continuous "BREAK" CDP6853.

CONTINUOUS "BREAK" /r--------------~, .r--------

,,---,_-rST:.::O~P STOP STOP

Rx 0 E~~ I I Bo I B1 BN P STOP ,=:+'_L.-I-~EEJ I I I BO 81 I

I START I I START

--------~r_n~--------~~~~~-~-~+ST~---TlJr---------~ ~-----
PROCESSOR
INTERRUPT
I ,I;,
PROCESSOR
NO INTERRUPT
SINCE RECEIVER
NORMAL
RECIEVER
FOR INTERRUPT DISABLED UNTIL INTERRUPT
RECEIVER WITH FRAMING FIRST STOP BIT
DATA REGISTER ERROR (PARITY
FULL AND OVERRUN
CHECKS NORMAL)
92CM-36784

Fig. 20 - Receive continuous "BREAK".

624
 CMOS Peripherals

CDP6853
CDP8853 OPERATION (Cont'd)

STATUS REGISTER OPERATION 5. Transmitter and Receiver may be in full operation

Because of the special functions of the various status bits, simultaneously. This is "full-duplex" mode.
there is a suggested sequence for checking them. When an 6. If the RxD line inadvertently goes low and then high
interrupt occurs, the CDP6853 should be interrogated, as during the first 9 receiver clocks after a Stop Bit; will
follows: result in a false Start Bit.
1. Read Status Register For false Start Bit detection, the CDP6853 does not
This operation automatically clears Bit 7 (IRQ). Sub- begin to receive data, instead, only a true Start Bit
sequent transitions on 5SR and DCD will cause another initiates receiver operation.
interrupt. 7. Precautions to consider with the crystal oscillator
2. Check IRQ Bit circuit:
The XTLI input may be used as an external clock
If not set, interrupt source is not the CDP6853. input. The XTLO pin must be floating and may not
3. Check DCD and DSR be used for any other function.
These must be compared to their previous levels, which 8. DCD and~ transitions, although causing immediate
must have been saved by the processor. If they are both processor interrupts, have no effect on transmitter
"0" (modem "on-line") and they are unchanged then operation. Data will continue to be sent, unless the
the remaining bits must be checked. processor forces transmitter to turn off. Since these are
high-impedance inputs, they must not be permitted to
4. Check RDRF (Bit 3) float (un-connected). If unused, they must beterminated
Check for Receiver Data Register Full. either to GND or Voo.
5. Check Parity, Overrun, and Framing Error (Bits 0-2)
Only if Receiver Data Register is Full.
6. Check TORE (Bit 4)
Check for Transmitter Data Register Empty.
7. If none of the above, then CTS must have gone to the
GENERATION OF NON-STANDARD BAUD RATES
Divisors
The internal counter/divider circuit selects the appropriate
divisor for the crystal frequency by means of bits 0-3 of the
III
FALSE (high) state. CDP6853 Control Register.
The divisors, then, are determined by bits 0-3 in the Control
PROGRAMMED RESET OPERATION
Register and their values are shown in Table II.
A program reset occurs when the processor performs a
write operation to the CDP6853 with ADO high and AD1 Generating Other Baud Rates
low. The program reset operates somewhat different from By using a different crystal, other baud rates may be
the hardware reset (RES pin) and is described as follows: generated. These can be determined by:
1. Internal registers are not completely cleared. The data Crystal Frequency
sheet indicates the effect of a program reset on internal Baud Rate = - - - - - - -
Divisor
registers.
Furthermore, it is possible to drive the CDP6853 with an
2. The DTR line goes high immediately.
off-chip oscillator to achieve the same thing. In this case,
3. Receiver and transmitter interrupts are disabled immed- XTLI (pin 6) must be the clock input and XTLO (pin 7) must
iately. If IRQ is low when the reset occurs, it st!l'!low be a no-connect.
until serviced, unless interrupt was caused by oeD or
15m'! transition.
4. DCD and DSR interrupts disabled immediately. If IRQ DIAGNOSTIC LOOP-BACK OPERATING MODES
is low and was caused by DCD or DSR, then it goes A simplified block diagram for a system incorporating a
high, also ~ andl5SR status bits subsequently will CDP6853 ACIA is shown in Fig. 21.
follow the input lines, although no interrupt will occur.
Occasionally it may be desirable to include in the system a
5. Overrun cleared, if set. facility for "loop-back" diagnostic testing, of which there
MISCELLANEOUS NOTES ON OPERATION are two kinds:
1. If Echo Mode is selected, RTS goes low. 1. Local Loop-Back
2. If Bit 0 of Command Register is "0" (disabled), then: Loop-back from the point of view of the processor. In
a) All interr~disabled, including those caused by this case, the Modem and Data Link must be effectively
DCD andDffi'l transitions. disconnected and the ACIA transmitter connected
b) Receiver disabled, but a character currently being back to its own receiver, so that the processor can
received will be completed first. perform diagnostic checks on the system, excluding
c) Transmitter is disabled after both the Transmit the actual data channel.
Data and Transmit Shift Registers have been 2. Remote Loop-Back
emptied
Loop-back from the point of view of the Data Link and
3. Odd parity occurs when the sum of all the "1" bits in the Modem. In this case, the processor, itself, is discon-
data word (including the parity bit) is odd. nected and all received data is immediately retrans-
4. In the receive mode, the received parity bit does not go mitted, so the system on the other end of the Data Link
into the Receiver Data Register, but is used to generate may operate independent of the local system.
parity error for the Status Register.

____________________________________________________________ 625
CMOS Peripherals

CDP6853
CDP6853 OPERATION (Conl'd)

Tabla II - Divisor Selecllon for Ihe CDP6853

CONTROL DIVISOR SELECTED BAUD RATE GENERATED BAUD RATE GENERATED

REGISTER FOR THE WITH 1.8432 MHz WITH A CRYSTAL
BITS INTERNAL COUNTER CRYSTAL OF FREQUENCY (F)
3 2 1 0
0 0 0 0 No Divisor Selected 1/16of External Clock at Pin XTLI 1/16 of External Clock al Pin XTLI
1.8432 x 10" F
0 0 0 1 36,864 36.864 - 50 36864
1.8432 x 10' F
0 0 1 0 24.576 24576 = 75 24576
1.8432 x 10" F
16_768 = 109.92
0 0 1 1 16.768 -
16768
1.8432 x 10' F
0 1 0 0 13.696 13696 = 134.58 13696
1.8432 x 10' F
0 1 0 1 12.288 12288 = 150 12288
1.8432 x 10· F
0 1 1 0 6.144 6, 144 - 300 6144
1.8432 x 10' F
0 1 1 1 3.072 3. 72 = 600 3072
1.8432 x 10' F
1 0 0 0 1.536 1_536 = 1200 1536
1.8432 x 10' F
1 0 0 1 1.024 1024 = 1800 1024
1.8432 x 10' F
1 0 1 0 768 768 = 2400 768
1.8432 x 10' F
1 0 1 1 512 512 = 3600 512
1.8432 x 10' F
1 1 0 0 384 384 = 4800 384
1.8432 x 10· F
1 1 0 1 256 256 = 7200 256
1.8432 x 10" F
1 1 1 0 192 192 = 9600 192
1.8432 x 10· F
1 1 1 1 96 96 = 19200 96

TO DATA LINK

Fig. 21 - Simplified system diagram.

626 __________________________________ ~---------------------------

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ CMOS Peripherals

CDP6853
CDP6653 OPERATION (Conl'd)
CDP8853

I iiTs DTii T.D R.D Dcii CTs DSR J

LL8

~
SEL

ST8
::dJ
3'
4'
CD74HC157 R.D
>--- 18 1A
DCD
28 2A
3A CTS
38
DSR
48 4A
~
MODEM
T.D
L....-.. SEL 1V
DTR
2Y
RTS
ST8 3.
~
CD74HC1S7
19
4'
1A
-
E 2B 2A
92CM- 3703

..
39 3A f---
- 48 4A f--

NOTES: 1. HIGH ON LLB SELECTS LOCAL LOOp·BACK MODE.

2. HIGH ON CD74HC157 SELECT INPUT GATES "B"INPUTS
TO "V" OUTPUTS; LOW GATES "A" TO "V".

Fig. 22 - Loop-back circuit schematic.

The CDP6853 does not contain automatic loop-back LLB may be tied to a peripheral control pin to provide
operating modes, but they may be implemented with the processor control of local loop-back operation. In this way,
addition of a small amount of external circuitry. the processor can easily perform local loop-back diagnostic
Fig. 22 indicates the necessary logic to be used with the testing.
CDP6853. Remote loop-back does not require this circuitry, so LLB
The LLB line is the positive-true signal toenable local loop- must be set low. However, the processor must select the
back operation. Essentially, LLB=high does the following: following:
1. Disables outputs TxD, DTR, and RTS (to Modem). 1. Control Register bit 4 must be "1 ", so that the transmitter
clock=receiver clock.
2. Disables inputs RxD, 5Ci5, CTS, 5SR (from Modem).
2. Command Register bit 4 must be "1" to select Echo
3. Connects transmitter outputs to respective receiver Mode.
inputs:
3. Command Register bits 3 and 2 must be "1" and "0",
a) TxD to RxD respectively, to disable transmitter interrupts.
b) DTR to DCD
c) RTS to Ci'S 4. Command Register bit 1 must be "0" to disable receiver
interrupts.
In this way, the system re-transmits received data without
any effect on the local system.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 627
CMOS Peripherals

CDP6853
DYNAMIC ELECTRICAL CHARACTERISTICS-BUS TIMING, VDD = 5 V de ± 5"10, Vss = 0 V de,
= =
TA -40 to +85°C, CL 75 pF, See Figi. 23, 24, 25.

LIMITS
IDENT.
CHARACTERISTIC CDP8853-1 CDP885W CDP8853-4 UNITS
NUMBER
Min. Ma •• Min. Ma•• Min. Ma••
1 Cycle Time tevc 953 DC 500 DC 250 DC
2 Pulse Width, DS/E Low or /mIWR High PWEL 300 - 125 - 90 -
3 Pulse Width, DS/E High or RD/WR Low PWEH 325 - 145 - 70 -
4 Clock Rise and Fall Time t"t, - 30 - 30 - 30
8 R/Vil Hold Time tRWH 10 - 10 - 5 -
13 R/W Set-up Time Before DS/E tRwS 15 - 10 - 5 -
14 Chip Enable Set-up Time Before AS/ALE Fall Ics 55 - 20 - 10 -
15 Chip Enable Hold Time leH 0 - 0 - 0 -
18 Read Data Hold Time tDHR 10 100 10 40 10 20
ns
21 Write Data Hold Time tDHW 0 - 0 - 0 -
24 Muxed Address Valid Time to AS/ALE Fall IAsL 50 - 20 - 10 -
25 Muxed Address Hold Time IAHL 50 - 15 - 5 -
26 Delay Time, DS/E to AS/ALE Rise IAsD 50 - 0 - 0 -
27 Pulse Width, AS/ALE High PWASH 100 - 45 - 20 -
28 Delay Time, AS/ALE to DS/E Rise lAsED 90 - 20 - 10 -
30 Peripheral Output Data Delay Time
From DS/E or RD tDDR 20 240 10 70 5 35
31 Peripheral Data Set-up Time tDSW 220 - 110 - 55 -
NOTE: Designations E, ALE, RD and WR refer to signals from non-6805 type microprocessors.

AS--....Ji

os

R/ii

CE

ADOIADI -------(1
WR'TE

AIO, AOI

MAO

NOTE:YH'GH "Yoo-20Y,VLOW "O.8Y, YDD 5.0V!'O'llo

92CM-37029
Fig. 23 - Bus timing waveforms of CDP6853.

628 ____________________________________________________________
 CMOS Peripherals

CDP6853

ALE (ADDRESS LATCH ENABLEI

(AS PINI

Ro (READ OUTPUT ENABLEI

(DS PIN I

WR (WRITE ENABLEI
(RiW PINI

CE CHIP (ENAB

ADO- AD?
(ADDRESS/DATA .:.B.:..US:..;I_ _ _ _ _ _ _ _ _ -< READ DATA
VALID

Fig. 24 - Bus-read timing waveforms of 8085 multiplexed bus. 92CM-37031

ALE (ADDRESS LATCH ENABLEI

(AS PIN I
III
Ro (READ OUTPUT ENABLE I
(OS PINI

WR (WRITE ENABLE)
(R/W PIN I

CE (CHIP ENABLEI
_ _~~~~WW~~~

1-----{i31}---..,
ADO-Ao7
(ADDRESS /..::;oA:;:.T:.:;A:..:8:.:U..::;S:..1_ _ _ _ _ _ _- - { WRITE DATA
VALID

NOTE'VHIGH • Voo -2 V, V LOW ' O.SV, FOR VoD ' 5Vt 10 %

Fig. 25 - Bus-write timing waveforms of 8085 multiplexed bus.

DYNAMIC ELECTRICAL CHARACTERISTICS· TRANSMIT/RECEIVE, See FlgB. 28, 27 and 28.

Voo = 5 V ± 5%, TA = _40° to +85°C
LIMITS
CHARACTERISTIC CDP8853·1 CDP8853·2 CDP8853-4 UNITS
Min. Max. Min. Max. Min. Max.
Transmit/Receive Clock Rate teCY 400' - 325 - 250 -
Transmit/Receive Clock High Time tCH 175 - 145 - 110 -
Transmit/Receive Clock Low Time tCl 175 - 145 - 110 -
XTU to TxD Propagation Delay too - 500 - 410 - 315 ns
RTS Propagation Delay tOlY - 500 - 410 - 315
IRQ Propagation Delay (Clear) tiRa - 500 - 410 - 315
RES Pulse Width tREs 400 - 300 - 200 -
(t"t, = 10 to 30 ns)
'The baud rate with external clocking IS: Baud Rate=:-::--=_ _
16 x Tccy
_______________________________________________________________ 629
CMOS Peripherals

CDP6853
os _ _ _ _J
XTLI
t TRANSMIT)
CLOCK INPUT)

TKO
fRo
(CLEAR)
NOTE: TxO RATE IS 1/16 TxC RATE
92CS-S8776 Sl2CS -annRI

1]
Fig. 28 - Transmit-timing waveforms with external clock. Fig. 27 - Interrupt- and output-timing waveforms.

EXTERNAL
TRANSMITTER XTLI
CLOCK
1.B432 MHr
CRYSTAL
Rxe
OPEN
(INPUT) CIRCUIT XTL.O

NOTE. RxO RATE IS 1/16 RxC RATE C· 10-50 pF

92CS-36778 INTERNAL CLOCK EXTERNAL CL.OCK
92CS-42341

Fig. 28 - Receive external clock timing waveforms. Fig. 29 - Transmitter clock generation.

8H ____________________________________________________________