CHAPTER 12

Registers and Counters

CMPE 261 Digital Logic Design

Prepared by: Dr. Mohamed Al-Meer

Modified and presented by: Dr. Khalid Abualsaud

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Learning Objectives
 Explain the operation of registers. Show how to transfer data
between registers using a tri-state bus.
 Explain the operation of shift registers, show how to build them
using flip-flops, and analyze their operation. Construct a timing
diagram for a shift register.
 Explain the operation of binary counters, show how to build them
using flip-flops and gates, and analyze their operation.

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Learning Objectives
 Given the present state and desired next state of a flip-flop,
determine the required flip-flop inputs.
 Given the desired counting sequence for a counter, derive the
flip-flop input equations.
 Explain the procedures used for deriving flip-flop input equations.

 Construct a timing diagram for a counter by tracing signals

through the circuit.

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Registers and Counters

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Registers and Counters
 Several D flip-flops may be grouped together with a common clock to
form a register.
 Next slide shows a register that can store four bits of information.
 Load signal is ANDed with a clock signal.
 When Load = 0, register is not clocked and it holds its present value.
 To load data into the register, Load is set to 1 for one clock period, and
data is applied to D inputs so it can be loaded on the falling edge of
the clock.
 Register has asynchronous clear inputs (ClrN)
 Alternatively, the flip-flops may have a clock enable (CE) input. We
can apply the load signal to (CE).
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Registers and Register Transfers
4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock Inputs.

When Load = 1, the Clk is transmitted to the flip-flop clock inputs and the data
applied to the D inputs will be loaded into the flip-flops on the falling edge of the
clock. 6
 Registers and Register Transfers
4-Bit D Flip-Flop Registers with Data, Load, Clear, and Clock Inputs.

When Load = 0, the clock is disabled, and the register holds its data. When Load
is 1, the clock is enabled, and the data applied to the D inputs will be loaded into
the FF, following the falling edge of the clock. 7
Data Transfer Between Registers
If En=1 and Load=1, the
output of register A is
enabled onto the tri-state
bus and the data in
register A will be stored in
Q after the rising edge of
the clock.

If En=0 and Load=1, the

output of register B will be
enabled onto the tri-state
bus and stored in Q after
the rising edge of the
clock.
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Logic Diagram for 8-Bit Register with Tri-State Output

• Integrated circuit register.

• A symbol for this 8-bit register

These buffers are enabled when En = 0.

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 Data Transfer Between Registers
This figure shows how
data can be transferred
from one of four 8-bit
registers into one of
two other registers

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Parallel Adder With Accumulator

 It is frequently desirable to store one number in a register of flip-flops

(called an accumulator) and add a second number to it, leaving the
result stored in the accumulator.
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Full adder cell with an associated accumulator
flip-flop and Load capability of an operand
Accumulator Flip-flop

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Full adder cell with an associated accumulator flip-
flop and Load capability of an operand
 Cell i has inputs ci , xi and yi and outputs si and ci+1.
 Accumulator flip-flop can either be loaded from yi or from the
sum si of the adder output.
 When Ld = 1 and Ad = 0, the multiplexer selects yi to be loaded
in the accumulator flip-flop Q on the rising edge.
 When Ad = 1 and Ld = 0, the adder output (si) is loaded into Q.
 The Ad and Ld are ORed to enable clock.
 When Ad = Ld = 0, the clock is disabled.
 Ad and Ld cannot be 1 at the same time.
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Shift Registers
 A shift register is a register in which binary data can be stored, and this
data can be shifted to the left or right when a shift signal is applied.
 Bits shifted out at one end of the register may be lost, or if the shift
register is of cyclic type, bits shifted out at one end are shifted back in
at the other end.
 When Shift = 1, clock is enabled and shifting occurs on rising edge.
 When Shift = 0, no shifting occurs and data in the register is
unchanged.
 Serial input (SI) is loaded into flip-flop Q3 at the rising edge of clock.
 If the register initially contains 0101 and serial input sequence is
1,1,0,1. Sequence of states will be 0101, 1010, 1101, 0110, 1011.
 If we connect serial output to serial input, and initially the register
holds 0111, Sequence of states will be 1011, 1101, 1110, 0111. 14
Right – Shift Registers

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8-Bit Serial-In, Serial-Out Shift Register

Serial in means that data is shifted into the first FF one bit at a time, and the FFs cannot
be loaded in parallel.
Serial out means that data can only be read out of the last FF and the outputs from the
other FFs are not connected to terminals of the integrated circuit. 16
Typical Timing Diagram for Shift Register

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4-bit Parallel-in, Parallel-out Right Shift Register
 Parallel-in means that all 4-bits can be loaded at the same time.
 Parallel-out means that all 4-bits can be read out at the same
time.
 Shift register has two control inputs: shift enable (Sh) and load
enable (L).
 If Sh = 1 (and L=0 or L=1), clocking the register causes Serial input
(SI) to be shifted into the first flip-flop.
 If Sh = 0 and L = 1, load 4 data inputs in parallel.
 If Sh = L = 0, clocking register causes no change in Q.

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4-bit Parallel-in, Parallel-out Right Shift Register

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4-bit Parallel-in, Parallel-out Right Shift Register

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4-bit Parallel-in, Parallel-out Right Shift Register
 The next-state equations for the flip-flops are as follows:

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 4-bit Parallel-in, Parallel-out Right Shift Register
Timing Diagram for Shift Register

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Shift Register with Inverted Feedback
twisted ring counter or Johnson counter

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Design of Binary Counters

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Binary Counters Using 3 T Flip-Flops
 We will first construct a binary counter using three T flip-flops to
count clock pulses.

TA = 1, TB = A, TC = AB 25
Binary Counters Using 3 T Flip-Flops

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Binary Counters Using 3 T Flip-Flops

TA = 1

TB = A

TC = AB

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 Binary Counters Using 3 D Flip-Flops

 We can also derive the D flip-flop

inputs for the binary counter starting
with its transition table (Table 12-2).
 For a D flip-flop, Q+ = D.
 By inspection of the table, QA+ = A′, so
DA = A′.
 The maps for QB+ and QC+ can be
plotted.

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 Binary Counters Using 3 D Flip-Flops
 The D input equations derived from the maps are
 DA = A+ = A′
 DB = B+ = BA′ + B′A = B ⊕ A
 DC = C+ = C′BA + CB′ + CA′ = C′BA + C(BA)′ = C ⊕ BA

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Binary Counters Using 3 D Flip-Flops

DA = A′

DB = B ⊕ A

DC = C ⊕ BA

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Design of 3-bit Up/Down Binary Counter

 Using One Control line X.

 If X=0, the Counter Will

Count Up.
 If X=1, the Counter Will
Count Down.

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 Design of 3-bit Up/Down Binary Counter

 We need three flip-flops.

 Let us use D type flip-flop.

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Design of 3-bit Up/Down Binary Counter

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Design of 3-bit Up/Down Binary Counter

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Design of 3-bit Up/Down Binary Counter

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Design of 3-bit Up/Down Binary Counter
 When X = 0, the equations are reduced to the equations of a
binary up counter:

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Design of 3-bit Up/Down Binary Counter
 When X = 1, the equations are reduced to the equations of a
binary down counter:

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 Design of 3-bit Up/Down Binary Counter

DA = A+ = A’

DB = B+ = X ⊕ A ⊕ B

DC = C+ = C’(X’BA + XB’A’)
+ C((X ⊕ A)’ + (X ⊕ B)’)

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Loadable Counter with Count Enable

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Loadable Counter with Count Enable

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 Counters for Other Sequences

 We will design a counter for the transition table shown in Table 12-3
using T Flip-Flops

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Counters for Other Sequences

Input for T Flip-Flop:

T=1 whenever a state of change

is required.

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 Counters for Other Sequences

Counter using T Flip-Flops

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 Procedure for Counter Design Using S-R Flip-Flops
 Instead of deriving an input equation for each D or T flip-flop,
the S and R input equations must be derived.

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Procedure for Counter Design Using S-R Flip-Flops

not in the graph= dont care sit

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Procedure for Counter Design Using S-R Flip-Flops

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Procedure for Counter Design Using S-R Flip-Flops

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Procedure for Counter Design Using S-R Flip-Flops

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Counter Design Using J-K Flip-Flops

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Counter Design Using J-K Flip-Flops
J-K Flip-Flop Table

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Counter Design Using J-K Flip-Flops

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Counter Design Using J-K Flip-Flops

Logic Circuit
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Design of 2-bit Binary Counters Using JK Flip-Flops
state diagram

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Design of 2-bit Binary Counters Using JK Flip-Flops

 We need two flip-flops.

 Let us use JK type flip-flop. state table

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Design of 2-bit Binary Counters Using JK Flip-Flops

Present Flip-Flops' Inputs

State J A KA J B KB J A KA J B KB
QA QB
X=0 X=1

0 0 0 X 0 X 0 X 1 X

0 1 0 X X 0 1 X X 1

1 0 X 0 0 X X 0 1 X

1 1 X 0 X 0 X 1 X 1

Excitation Table
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Design of 2-bit Binary Counters Using JK Flip-Flops

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Circuit of 2-bit Binary Counters Using JK Flip-Flops

x and b is common in all equations

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