CT 221: DIGITAL ELECTRONICS

Unit 4: Registers and Counters

Introduction
 Counters and registers belong to the category of MSI
sequential logic circuits.
 They have similar architecture, as both counters and
registers comprise a cascaded arrangement of more than
one flip-flop with or without combinational logic devices.
 Counters are mainly used in counting applications. They can
either measure the time interval between two unknown
time instants or measure the frequency of a given signal.
 Registers are primarily used for the temporary storage of
data.
Register
 A register is a memory device that can be used to store more
than one bit of information.
 A register is usually realized as several flip-flops with
common control signals that control the movement of data
to and from the register.
 An n-bit register is a group of n flip-flops and is capable of
storing binary information containing n bits.
 In addition to flip-flops, it may contain combinational logic
which performs certain data-processing tasks.
 The flip-flops hold the information and the logic controls
when and how new information is transferred into the
register.
Shift Registers
 A register which is capable of shifting its binary information
either to the right or to the left is called a shift register.
 It consists of a number of flip-flops cascaded together with
the output of one flip-flop connected to the input of the
next.
 All flip-flops in the register receive a common clock pulse
that causes the shift from one state to the next.
 A given binary number is multiplied by 2 if its bits are shifted
one bit position to the left and a 0 is inserted as the new
least-significant bit.
 And a number is divided by 2, if the bits are shifted one
position to the right.
Shift Registers
 Some basic shift register operations are
 Shift Registers
Serial In-Serial Out
 This shift register accepts data serially (one bit at a time)
and produce the stored information in serial form.
 Each clock pulse will move an input bit to the next flip-
flop.
Shift Registers
Serial In-Serial Out
 Assume the register is initially clear. If four bits 1010 inter into
the register, beginning with the right most bit.
 The 0 is put onto the data line, making D=0 for FF0. When the
first clock pulse is applied FF0 is reset, thus storing a 0.
 Next the second bit which is 1 is applied to the data input,
making D=1 for FF0 and D=0 for FF1.
 When the second clock pulse occurs, the 1 on the data input
is shifted into FF0 and 0 that was in FF0 is shifted into FF1.
 On the next clock pulse third bit 0, is shifted into FF0, a 1
shifted into FF1 and a 0 stored in FF1 is shifted into FF2
Shift Registers
Serial In-Serial Out
 For last bit a 1 is applied to the data input and a clock pulse
is applied. The 1 is entered into FF0, the 0 from FF0 is shifted
into FF1, the 1 from FF1 is shifted into FF2 and the 0 from
FF2 is shifted into FF3.
 When we want to get the data out of the register, the bits
must be shifted out serially and taken off at the Q3 output.
 After a CLK4 in the data entry is applied, the right most bit 0
appear at Q3 output.
 When CLK5 is applied, the second bit appear at Q3 output.
CLK6 shifts the third bit to output and CLK7 shifts the last
bit to output.
Shift Registers
Serial In-Serial Out
Shift Registers
Serial In-Serial Out
Shift Registers
Serial in - Parallel Out
 Data bits are entered serially into this type of the register,
and taken out of the register in parallel way.
 Once the data is stored each bit appears on its respective
output line and all bit are available simultaneously.
Shift Registers
Serial in - Parallel Out
 Example: show the status of the 4 bit SIPO register for
the data input and clock waveform shown in figure
below. The register initially contain all 1s.
Shift Registers
Parallel In- Serial Out
 For this register the bits are entered simultaneously into
their respective stages on parallel lines and the output is
taken serially.
Shift Registers
Parallel In- Serial Out
 It consists of four bit data lines and a shift/load’ input, which
allows for bits of data to loads in parallel into the register.
 When shift/load’ is low gates G1 through G4 are enabled
allowing each data bit to be applied to the D input of its
respective flip-flop.
 When shift/load’ is high, gates G5 through G7 are enabled
allowing the data bits to shift right from one stage to the
next.
 An OR gate allow either the normal shifting operation or the
parallel data entry operation.
Shift Registers
Parallel In- Parallel Out
 This register follow simultaneous entry of data bits and
all bits appear on the output simultaneously
Counters
 A counting circuit composed of memory elements, such
as flip-flops and electronic gates, is the simplest form of
sequential circuit available.
 Counting circuits can be in either synchronous (clock
driven) and asynchronous (event driven).
 All counter circuits count clock pulses and store the
number received in an array of memory elements.
 Counters are fundamental and important components of
a digital system and can be used for timing, control or
sequencing operations.
Counters
Counting in Binary
 A counter can form the same pattern of 0’s and 1’s with logic
levels.
 The first stage in the counter represents the least significant
bit – notice that these waveforms follow the same pattern as
counting in binary.
Asynchronous (Ripple) Counters
 A ripple counter is a cascaded arrangement of flip-flops
where the output of one flip-flop drives the clock input of
the following flip-flop.
 The number of flip-flops in the cascaded arrangement
depends upon the number of different logic states that it
goes through before it repeats the sequence, a parameter
known as the modulus of the counter.
 The clock input is applied only to the first flip-flop in the
cascaded arrangement. The clock input to any subsequent
flip-flop comes from the output of its immediately preceding
flip-flop.
Asynchronous Counters
Two bit Asynchronous Counter
 The two-bit asynchronous counter as shown in figure.
 It uses two J-K flip-flops in the toggle mode i.e. J=K=1.
Asynchronous Counters
Two bit Asynchronous Counter
 Notice that the Q0 output is triggered on the leading edge of
the clock signal. The following stage is triggered from Q’0 .
 The leading edge of Q’0 is equivalent to the trailing edge of
Q0 . The resulting sequence is that of an 2-bit binary up
counter.
Asynchronous Counters
Two bit Asynchronous Counter
 The two bit counter exhibit four different states.
 If Q0 represents the LSB and Q1 represents the MSB,
then the sequence of the counter states represents a
sequence of binary numbers.
Asynchronous Counters
Three bit Asynchronous Counter
 The three-bit asynchronous counter uses three J-K flip-
flops in the toggle mode.
Asynchronous Counters
Three bit Asynchronous Counter
 Asynchronous Counters
Propagation Delay
 Asynchronous counters are sometimes called ripple
counters, because the stages do not all change together.
 For certain applications requiring high clock rates, this is a
major disadvantage.
 The low to high transition of Q0 occurs one delay time after
the positive going transition of the clock pulse.
 The low to high transition of Q1 occurs one delay time after
the positive going transition of Q’0.
 The low to high transition of Q2 occurs one delay time after
the positive going transition of Q’1.
Asynchronous Counters
Propagation Delay
 Figure below illustrate the propagation delay in 3-bit
asynchronous counter.
Asynchronous Counters
Propagation Delay
 The cumulative delay of an asynchronous counter is a
major disadvantages because it limits the rate at which
the counter can be clocked and creates decoding
problems.
 The maximum cumulative delay in a counter must be less
than the period of the clock waveform.
Asynchronous Counters
Asynchronous Decade Counter
 This counter uses partial decoding to recycle the count
sequence to zero after the 1001 state.
 It is also known as BCD decade counter because its ten
sequence produces the BCD code.
 It requires four flip-flops and a NAND gate.
 Other truncated sequences can be obtained using a
similar technique.
Asynchronous Counters
Asynchronous Decade Counter
 This counter counts upwards on each negative edge of
the input clock signal starting from “0000” until it
reaches an output “1001”.
 Both outputs QA and QD are now equal to logic "1" and
the output from the NAND gate changes state from logic
"1" to a logic "0" level when the clock goes to level one
and whose output is also connected to the CLEAR (CLR)
inputs of all the J-K Flip-flops.
Asynchronous Counters
Asynchronous Decade Counter
Asynchronous Counters
Asynchronous Decade Counter
 BCD is called decade counter (0-9). To count from 0-99 2-decade
counters are needed, and to count up to 999 3-decade counters
are need. Below is the timing diagram for decade counter.
Synchronous Counters
 In a synchronous counter all flip-flops are clocked
together with a common clock pulse.
 Thus, all the flip-flops change state simultaneously.
 The effect of propagation delay is not cumulative since
all flip-flops in the counter change state at the same
time. Delay if any is due to the delay of a single flip-flop.
Synchronous Counters
Two bit Synchronous Counter
 A two bit synchronous counter consists of two J-K flip-
flops as shown in figure.
Synchronous Counters
Two bit Synchronous Counter
 Assume that the counter is initially in the binary 0 state.
 During positive edge of CLK1 pulse FF0 will toggle and Q0 will go
high. Due to the propagation delay J1 =K1=0 therefore FF1 does not
change state.
 When positive edge of CLK2 occurs, FF0 will toggle and Q0 will go
low and since J1 =K1=1 then FF1 will toggles and Q1 goes high.
 When the leading edge of CLK3 occurs FF0 toggles Q0 will go high
and Q1 remains high.
 Finally at the leading edge of CLK4 both Q0 and Q1 go low because
they both have a toggle condition.
Synchronous Counters
Two bit Synchronous Counter
 The complete timing diagram for this counter is shown in
figure
 Synchronous Counters
Three bit Synchronous Counter
 A three bit synchronous counter and its binary state
sequence are shown below
Synchronous Counters
Three bit Synchronous Counter
 FF0 must be held in toggle mode Q0 changes on each clock
pulse.
 Q0 is connected to the J1 and K1 inputs of FF1 hence Q1
changes each time Q0 is high and remains on its previous
state when Q0 is low.
 Q2 changes state when it is preceded by the condition in
which both Q0 and Q1 are high. This condition is detected by
AND gate and applied to the J2 and K2 inputs of FF2. at all
times the J2 and K2 inputs of FF2 are held low by the AND
gate output and FF2 does not change state.
Synchronous Counters
Three bit Synchronous Counter
 The timing diagram of 3 bit counter is shown below
Design of Synchronous Counters
 Besides the binary sequence, synchronous counters can
be design to output any random sequence.
 We can design a counter which sequence only even
numbers or odd numbers or gray code sequence etc..
 In this part the general design procedure for
synchronous counter is applied in series of steps.
Design of Synchronous Counters
Step 1: State Diagram
 Specify counter sequence and draw a state diagram
 A state diagram shows the progression of states through
which the counter advances when it is clocked.
Design of Synchronous Counters
Step 2: Next-State Table
 Derive a next-state table from the state diagram.
 The next state is the state that the counter goes to from
its present state upon application of a clock pulse.
Design of Synchronous Counters
Step 3: Flip-Flop Transition Table
 Develop a transition table showing the flip-flop inputs
required for each transition. The transition table is
always the same for a given type of flip-flop.
Design of Synchronous Counters
Step 3: Flip-Flop Transition Table
 The first row shows that to let the present state 0 remain
a 0 after the next clock pulse then J=0 and K is don’t
care.
 J=K=0 relates to no change input condition and when
J=0, K=1 relates to the reset input condition. Both of
these cases results on the next state 0, therefore
transition 0 to 0 is defined by J=0, K=x.
 All other rows can be similarly verified.
Design of Synchronous Counters
Step 3: Flip-Flop Transition Table
 Excitation table can be summarized as follow
Cell Present State Next State Flip flop inputs
# 𝑄 𝑄 𝑄 𝑄 𝑄 𝑄 𝑱𝟐 𝐾 𝑱𝟏 𝐾 𝑱𝟎 𝐾
0 0 0 0 0 0 1 0 X 0 X 1 X
1 0 0 1 0 1 1 0 X 1 X X 0
2 0 1 0 1 1 0 1 X X 0 0 X
3 0 1 1 0 1 0 0 X X 0 X 1
4 1 0 0 0 0 0 X 1 0 X 0 X
5 1 0 1 1 0 0 X 0 0 X X 1
6 1 1 0 1 1 1 X 0 x 0 1 X
7 1 1 1 1 0 1 X 0 X 1 X 0
Design of Synchronous Counters
Step 4: Karnaugh Maps
 Transfer the J and K states from the transition table to the Karnaugh
maps. There is a Karnaugh map for each input of each flip-flop.
Design of Synchronous Counters
 Step 4: Karnaugh Maps
Design of Synchronous Counters
Step 5: Logic Expression for Flip-Flop Inputs
 Group the Karnaugh map cells to generate and derive
the logic expression for each flip-flop.
 Design of Synchronous Counters
Step 6: Counter Implementation
 Implement the expressions with combinational logic and
combine with the flip-flops to create the counter.
Tutorial
 The content of a 4-bit register is initially 1101. The
register is shifted six times to the right with the serial
input being 101101. What is the content of the register
after each shift?
 Design a synchronous counter to sequence 4 3 1 7 5
and repeat.
 Design a 3-bit binary ripple up counter using positive
triggered D flip-flops.
Tutorial
 Design a 3-bit counter which counts in the sequence: 001,
011, 010, 110, 111, 101, 100, (repeat) 001, . . .
a) Use J-K flip-flops
b) Use S-R flip-flops
c) Use D flip-flops
Note: Transition Tables D and SR flip-flops are

Row # Q 𝑄 D Row # Q 𝑄 S R
0 0 0 0 0 0 0 0 X
1 0 1 1 1 0 1 1 0
2 1 0 0 2 1 0 0 1
3 1 1 1 3 1 1 X 0
Homework
 Study on synchronous up down counter