Specialization: Electronic Instrument Maintenance Department: Electronics Engineering

Course: Fundamental Digital

Level: Two Course code: EECIM1203
Electronics and Circuits
Date: 05 / 03 / 2023 - 06 / 03 / 2023 Week: Ten

SEQUENTIAL LOGIC CIRCUIT: SHIFT REGISTER CIRCUITS Worksheet 9

Student Name: ……………………………………………………………………………..

OBJECTIVES:
At the end of this session the student should be able to:
1. Be able to analyze and design shift registers.
2. To examine binary counting circuits
3. To observe shift register operation
4. To implement the shift register using flip flop and verifying the function of the universal shift
register (74194 chip).
Introduction:
A shift register basically consists of several single bit “D-Type Data Latches”, one for each data bit,
either a logic “0” or a “1”, connected together in a serial type daisy-chain arrangement so that the output
from one data latch becomes the input of the next latch and so on.
This sequential device loads the data present on its inputs and then moves or “shifts” it to its output once
every clock cycle.
Shift Registers are used for data storage or for the movement of data and are therefore commonly used
inside calculators or computers to store data such as two binary numbers before they are added together,
or to convert the data from either a serial to parallel or parallel to serial format.
Shift register IC’s are generally provided with a clear or reset connection so that they can be “SET” or
“RESET” as required. Generally, shift registers operate in one of four different modes with the basic
movement of data through a shift register being:

 Serial-in to Parallel-out (SIPO) – the register is loaded with serial data, one bit at a time, with the
stored data being available at the output in parallel form.

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  Serial-in to Serial-out (SISO) – the data is shifted serially “IN” and “OUT” of the register, one bit
at a time in either a left or right direction under clock control.
 Parallel-in to Serial-out (PISO) – the parallel data is loaded into the register simultaneously and is
shifted out of the register serially one bit at a time under clock control.
 Parallel-in to Parallel-out (PIPO) – the parallel data is loaded simultaneously into the register, and
transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented graphically as:

Also, the directional movement of the data through a shift register can be either to the left, (left shifting)
to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting within the same
register thereby making it bidirectional. In this tutorial it is assumed that all the data shifts to the right,
(right shifting).
Apparatus and Materials Required

Quantity Materials .No

2 7474 Dual D Flip-Flop 1
1 IDL-800 Prototyping Board 2
1 LED 3
1 Resistor, 270 Ω, ¼ W 4
16 Wire connectors 5

IC 7474 Pinout diagram

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 PART 1: Serial-in to Serial-out (SISO):
Procedure
1. Connections are made as shown in the SISO circuit diagram.
2. The shift register is loaded with 4 bits of data one by one serially.
3. At the end of the 4th clock pulse, the first data ‘D0’ appears at Q0.
4. Applying another clock pulse will push the second data bit, ‘D1’ to Q0.
5. Applying yet another clock pulse gives the third data bit, ‘D2’ at Q0, and so on

Circuit Diagram

We assume that all the flip-flops ( FFA to FFD ) have just been RESET (CLEAR input) and that all the
outputs Q0 to Q2 are at logic level “0”.
A logical input 11001 is applied at the serial input line connected to FFA.
 Study the operation of this shift register by completing the following table and write the value of the
output of every FF after each clock pulse.

Serial output at Q2 Q2 Q1 Q0 Timing pulse

0 0 0 0 Initial value

Clock Pulse 1

Clock Pulse 2

Clock Pulse 3

Clock Pulse 4

Clock pulse 5

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 How many clock pulse are required to get the entire logical input at Q2? …………….
 Complete the timing diagram of the outputs Q0, Q1 and Q2.

1
0 t
Q0

1
0 t
Q1

1
0 t
Q2

1
0 t

Part 2: Serial-in to Parallel-out (SIPO) Shift Register

1. Connections are made as shown in the SIPO circuit diagram.

2. On applying the first bit of data and then a clock pulse, it can be observed that this data appears at (Q 0).
3. Now, applying the second bit of data and a clock pulse, the bit at Q 0 shifts to Q1 and Q2 will be loaded
with the new data.
4. This repeats until all 4 data bits are loaded.
5. At the end of the 4th clock pulse, all 4 bits are available at the parallel output pins Q 3 through Q0.

Circuit Diagram
Parallel Output

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We assume that all the flip-flops ( FFA to FFD ) have just been RESET (CLEAR input) and that all the
outputs Q0 to Q3 are at logic level “0”.
A logical input 1101 is applied at the serial input line connected to FFA.
 Study the operation of this shift register by completing the following table and write the value of the
output of every FF after each clock pulse.

Parallel output at Q3 Q2 Q1 Q0 Timing pulse

Q0 Q1 Q2 Q3

0000 0 0 0 0 Initial value

Clock Pulse 1

Clock Pulse 2

Clock Pulse 3

Clock Pulse 4

Clock pulse 5

Part 3: Bidirectional Shift Register with Parallel Load

A register capable of shifting in both directions is called bidirectional; 4-bit shift register can be
constructed using D flip-flops as shown below.

Instructor: Mehrez Saafi Head of Department: Mrs Carla Mendoza

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