Emerging Trends in Electronics (MSBTE-Sem 6- Electronics) positioned to operate at twice the performance of the ARMSTDML. * It is intended to deliver 400 Dhrystone 2.1 MIPS at 300 MHz on 0.25 um CMOS technology. In order to achieve this level of performance, starting from the ARMSTDML, two approaches have been combined: 1, The maximum clock rate has been increased, 2. The CPI (average number of Clocks per Instruction) has been reduced. Dy_1.6 MULTIPLE CHOICE QUESITONS @.1.1. Main processor chip in computers is (@)ASIC (ASSP (©)CPU (4) CPLD Ans. : (©) @.1.2 ARM stands for (@) Advanced Rate Machines (©) Advanced RISC Machines (©) Anificial Running Machines (@) Aviary Running Machines Ans. : (0) Q.1.3. The CISC stands for (a) Computer Instruction Set Compliment (b) Complete Instruction Set Compliment (©) Computer Indexed Set Components (@ Complex Instruction set computer Ans. :(@) Q.1.4 The GPIO stand for (a) General Purpose Inner Outer Propeller (b) General Purpose Input Output Pins (©) General Purpose Interested Old People (4) General Purpose Input Output Processor V Ans. : (b) Q.1.5 The IDE stand for (a) In Deep Environment (b) Integrated Development Environment (©)Internal Deep Escape (4) IDE Ans. = (b) @.1.6 A program written with the IDE for Arduino is called (@)IDE source (b) Sketch (©)Cryplography (4) Source code Ans. (b) Q.1.7 Arduino IDE consists of 2 functions. What are they? (@) Build( and loop) Setup() and build) (©) Setup() and loop() (@) Loop() and build and setip() Vans. :(0) (New Syllabus w.es academic year 2019-20) (D6-25) 1.10 ant 1.12 0.1.13 Q144 1.45 1.16 1.17 (Advance Processors) ..Page no. (1-28) ‘ALU of ARM7TOMI is bit (8 32 (©)64 IO ANS.: How many digital pins are there on the UNO board? (14 12 ©1620 Ans. (a) Most of processors designed by ARM are (a) 16 bit (o) 32 bit (c) 64 bit (A)8 bit “ANS. (%) ‘The function of link register in ARM7TOMI is (a) To store return address whenever subroutine is called (b) To store address of VO device (©) Multiplex the address and data lines (@ Perform addition YAns. (0) ‘The function of register 115 in ARM7TDM is as (@) Program Counter —(b) CPSR (©) SPSR (@aLU Ans: (8) In the ARM Nomenclature ARMxTDMI, D and M stand for (2) Debug and Fast Multiplier units are present (b) Division and Multiplier units are present (©) Debugger and Multiplier units are not present (@) Division and Multiplier units are not present Ans: (0) ‘The computer architecture aimed at reducing the time of execution of instructions is (CISC (by RISC (ISA (@ ANNA Ans. (0) In CISC processor the nature of instruction size is. (a) Fixed (b) Variable (©)Both A andB —_(d) None of the above YAns.:(0) If the three stages of execution in pipelining are ‘overlapped, how would be the speed of execution? (a) Higher (b) Moderate (Lower (@) Unpredictable YAns.:( In RISC Processors configuration status of conto: unit is (6) Hardwired (©) Micro programmed (©)Both A and Bd) None of the above ¥ Ans. ‘Tech-Neo Publications ....A SACHIN SHAH VentutEmerging Trends in Electronics (MSBTE-Sem 6- Electronics) 2.1.18 0.1.20 4.21 Q.1.22 0.1.23 0.1.24 0.1.25 ‘A function is a series of programming statements that can be called by name. Which command is called once when the program starts: (a) loopt) —_(b) setup) (© (output) (4) Cinpur) Ans. (0) In ATmegad26p ‘p' refers to? (@) Production (b) Pico-Power (©) Peripheral (4) Programmable on chip Ans. (0) ‘The throughput of a super scalar processor is (a) less than 1 (1 (© More than 1 (4) Not Known YAns.: (0) Each stage in pipelining should be completed within cycle. @1 2 ©3 @4 Ans. (a) The main importance of ARM micro-processors is providing operation with (8) Low cost and low power consumption (©) Higher degree of multi-tasking (©) Lower error or glitches (@ Efficient memory management YAns. : (a) In ARM processor when Interrupt occurs ARM processor goes into following mode (@) FIQ mode (8) Abort mode (Supervisor mode (4) Undefined mode ‘The function of Barrel shifter is (@) Shift Operation in same instruction cycle (b) Shift operation in 2 instruction cycle (©) Shift operation in 4 instruction cycle (@) None of the above YAns. (a) YAns. (a) Evaluate the following statements 1. RIB is traditionally used as the stack pointer and stores the head of the stack in the current processor mode IL R14 is the link register where the core puts the retum address on executing a subroutine TIL RIS is the program counter and contains the address ofthe next instruction to be fetched (@) All the options are tre (b) I and Tare true (@)T and Mare true Vans. : (a) (©) Mand MM are true Q.1.35 MogaAVR has (Advance Processors) ...Page no. (1-29) @.1.28 When the processor Is executing simple data processing instructions, the pipeline enables one instruction to be completed every clock cycle, this is also called as. (@) Throughput (©) Execution (b) Latency (a) None of the above Ans. : (a) @.1.27 Itstarts with a" and continues until a */ what doss this do? (#) Loads asketch —_(b) Makes comments (©) Compiles quicker () Makes stars appear Ans. :(b) @.1.28 The function used to execute one or many statements, multiple time (@ setup0 (6) 0p (© Cinpot) —_@) (outpus) Ans. (b) @. 1.29 Default bootloader for the Arduino UNO is, (2) Optibootioader (© Bare box (b) AIR-boot (GAG @. 1.30 Select proper microcontroller used in Arduino UNO. (@) ATmega328p (© ATmega32114 (b) ATmega2560 (@ ATOISAM3x8E Ans. : (a) @.1.31 Choose from the following that does not include application of RISC. (2) Video processesing (b) Image Processing (©) Amplifiers and Regulators (4) Telecommunication Ans. : (6) @.1.32 Many designs include pipelines as long as (22 (0) 78 (€)55 (a) 20 Ans. : (€) @.1.33 CISC includes. ‘complex instruction, (a) Double Clock (b) Single Clock (©) Multi clock (4) No Clock VAns. (©) @.1.34 ASSPis acronymot___ (8) Application System Specific Processor () Application Security System Procedure (©) Applicable set fpr system Procedure (2) Application Specific System Processor ¥Ans. : (@) program memory (0) 4256 KB. (©) 32-655 KB (6-533 KB vAns. (New Syllabus we.f academic year 2019-20) (D6-25) Tl rech-Neo Publications ..A SACHIN SHAH VentureEmerging Trends in Electronics (MSBTE-Sem 6- Electronics) 2.1.36 @.1.37 Q.1.38 2.1.39 0.1.40 141 1.42 1.44 @.1.45 Tiny AVR has (a) Limited Peripheral Set (b) Extensive Peripheral Set (©) Extended Peripheral Set (4) Set of rules Program memory. (@RAM (®)ROM (©) Non-Volatile flash (4) Volatile lash Instructions are stored Ans. (0) How many types of arduinos do we have? @5 &6 ©8 @7 YAns.: (0) Give the micro-controller used in arduino UNO? (@) ATmega328p ——_(b) Atriega2560 (©) Atmega32114 (4) ATOISAM3X8E YAns. (a) In ATmega326p chip P refer to (@) production (b) pico-power (©)pinmode (4) programable on chip ‘Arduino shields are also called as (@) Extra Peripherals, (©) Add on modules (© Connectivity modules (@) Another Arduino What is default boot loader of the arduino UNO? (@) Optiboot loader (b) AIR boot (© Bare box (4) GAG Which is the software or a prgraming language used for controling of arduino? (a) Assembly language (b) C Tanguage (JAVA (@ Any language Vans. :(@) ‘A program written with the IDE for arduino is called as? (@) IDE source (© cryptography Arduino IDE consists of two functions what are they? (@) build( and Toop (©) setup() and build) (© setup0 and loop (@) buildd) Joop0 and setup YAns. : (0) VAns.: (b) () sketch (@ source code Ans. : (b) Ans. : (6) 2.1.46 a.1.47 @.1.49 2.1.50 a1st @.1.52 1.53 0.1.55 Q.1.56 (Advan How many digits! pins are there on the UNO board? @4 ®2 16 How many analog pins are used in arduino UNO board? @I6 M6 © ‘The first micro-processor was introduced in_. (@) 4004 in 1971(b) 8080 in 1972 (© 8085 in1971 (@) 8086 in1972 MIPS stands for (a) more insrution per second (20 ¥Ans.:(@) @8 Ans. (0) (b) medium instruction per second (6) million instruction per second YAns.:(0) (@) micro instruction per second RISC stands for. (@) reduce instrument set computer (b) reduce instruction set of computer (© computer information set instruction (@ reduce instrcton set complex Vans. : 0) RISC includes number of clock cycles_. (©) dovbe @ tiple performance. higher (@) moderate YAns.: (0) ing attempts to keep every part of processor (@) single (©) multiple RISC has (@ lower (©) medium Pipel Ans: (@) (a) free (©) busy (idle (@) any SIMD stands for. (@) multiple data single instruction (©) single data many instruction (©) multiple instruction single data (@) single instruction multiple data Ans. :(b) Ans. :(@) ‘The optimal power architecture effective data ‘communication uses. (DMA () MAD (ADM (AMD VAns.:(@) The higher end processor operates with to voltage (3105 ©2104 ()2t05 (@)5t02 vAns.:(0) (New Syllabus w.ef academic year 2019-20) (D6-25) Tech-Neo Publications ...A SACHIN SHAH Ventul®1.57 1.58 Emerging Trends in Electronics (MSBTE-Sem 6- Electronics) The RISC instruction set differed ‘rom, computer (a) Mega (b) Micro (©) Micro and mega (4) mini Ans. : (A) RISC allow the architecture to operate efficiently. (@) load () store (©)load-store (4) read-write Ans. : (6) ‘An enhanced multiplier resulting in 2.1.59 @.1.61 2.1.63 Q.1.67 performance (@ higher @ lower (medium —_ (very ow Ans. (0) ‘The processor must take memory access oycle : @1. 3 ©2 @4 VAns. : (c) Which of the folowing s not three stage pipelining (a) decode (b) power © teen (execute Yams: (6) The full version is larges and less power efficient than the hard macrocel (2) 50% -50% _()35%-35% (140% -40% (4) 55% - 55% arduino © ++ program consist of two main function Which of them (2) while Loop0 and loop (©) ifelseQ and while loop YAns. (a) (©) setup0 and loop (@) for and setup YAns.:(@) function is called once when a sketch stars after power up or reset . @) o0p0 setup (©) while @ pinMtodeo. Ans. (0) In Arduino IDE every instruction (line of code ) is terminated by a symbol. @0 @: @™ Wi YAns:@) fare used to write blocks of code in Arduino IDE sketch. (@)colon (©) square brackets Styles of comment used in Arduino IDE. @n ory oF (@) Both a and b (b) semicolon (A) curly brackets Ans. (d) Vans. :(@) Q. 1.68 1.69 1.70 Qt 172 1.74 @.1.75 4.77 (Advance Processors) ...Page no. (1-31 variables are named ereas of the memory (@)processor __(b) micro-processor (©) progress (@) Arduino “vans. :(@) arduino is a very processor (ay hard (6) simple (verersy —(@)bothanadd Ans. (6) character data types that holds a character, (a) single (b) multiple (©)bothaandb —@) many VAns. (a) characters are used to hold value from (2) 128(0129—(b) 12710 128 (©) 12800127. @) 12910 128 VAns. (0) multiple lines is used for (@) text ignore (©) start coniment (b) end comment (@) write a comment in here YAns. :(b) Arduino includes keywords for controlling the sketch (2) arithematic flow (6) algebric flow (©) both aand b (@) logical flow “Ans. : (4) are pre build circuit board that fit on top of arduino, (@) shields () sensor (datatype ——_(@) bread board VAns. : (@) ISP stands for @) in-symbol programming (b)in-system pogramming (©) in-system processor @ in-system progress Ans. :(b) ISP programming method is functionally performed through Protocol. @sPt () SSP. osr (spp Ans. (a) UTAG allows accessing of On chip for debugging. (@) internal memory and register (b) Internet (c) only memory (@ only register Ans. (a) (New Syllabus w.e f academic year 2019-20) (06-25) [Bb reci-veo Publications. .A SACHIN SHAH Venture{8 the Third and latest version of arduino UNO) G@RI ORO RI @)R2_—VAns(@) 1.79 In Arduino, setup () function is used to initialize. (@) constant (b) variable (©)bothaandb _ (A) characters YAns. :(b) @.1.80 Arduino IDE language can be expanded through library ac. OCH (© English (@IAVA Yan Q.1.81 loop() function is executed repeated in the (@) program —_(&) main program @ecode —@abande Ans. (0) @.1.82 In Arduino sketch ( < ) sign is used for what Purpose? (@) not equal to (b) less than (©) greate than - (4) less than equal to “Ans. : (b) @.1.83 Select Appropriate command to read Digital Pin number 2 (©) pinMode(pin, mode) (@ digitaRead(2); “Ans. :(@) (@) digital Wrte(pin); (©) delay (ms); Q. 1.84 WOT stands for (@) watch dog timer (b) write digital timer (©) when data transfer (4) both and Ans. : (a) @.1.85 JTAG stands for. (a) joint test action group (b) joint test attract group (©) joint test action government @ joint tube action group Vans. : (a) @.1.86 Arduino design use a variety of and (a) micro-processor and computer (&) micro-conteoller and processor (©) miero-processor and controller Ans. (0) (4) micto-controller and computer Q. 1.87 identify the following platform on which arduino IDE doesnot run (@) windows (b) linux (©) Android (4) Osx “Ans. (©) 88 Function of boot loader is. (a) installing new firmware (©) transfer the data into register (4) both a and b () Add two registers YAns.: (a) (New Syllabus w.e academic year 2019-20) (06-25) State the function of IDE. (a) to reste a sketch @.1.89 (b) to create a program (©) to create a schematic diagram (4) to create simulation VAns.: (a) Q. 1.90 most micro-controller systems are limited to (@) windows (6) linux * (OSX (4) both bande Yan 1.91 does not manufacture processors by ise (cise (AVR (RISC (ARM YAns. (4) @.1.92” XMEGA includes the pin package of__ (a) 2232-50 (b) 44-64-100 (©)34-55-150 (4) Bothaandb Ans. (b) @.1,93. The program memory of XMEGA is__ (a) 16-64k (6) 8-16kb (©)16-384K (4) O-16Kb Y Ans. :(6) 2.1.94 ‘Are used for. storing complexed instructions. (@) transponders (6) terminator (transformers, (4) Transistor YAns.:(@) 9.1.95 Architecture is a method of parallel ‘computing used in many processors. (@ Von-neumann (6) Super sealer se @asic YAns. (0) @.1.96 FPGA Gates used in FPSLIC are (2) Skto40k ——_() keto 50K © 16t055k (2410 50k @.1.97 AVR core can RUN upto (a) SMhz (©) 50Mhz (© 50H (©) 25Mhe, YAns.:(0) @.1.98 The Atmel Released Microcontrollers based on the S82 bit AVAS2 Architecture in (@)2005_ (b) 2006 (©2007 (a) 2008, WAns. @.1.99 There are types of comments in Aurdino. @3 H2 Ol @S Ans.) Q. 1.100 Emphasis on software. @RISC — @)cIsC (AVR © @) ARM Ans. :(0) [al rech-neo Publications ...A SACHIN SHAH VentureEmerging Trends in Electronics (MSBTE-Sem 6- Electronics) @.1.101 In RISC register to register load and store are, structions. (@)Dependend (0) Independed (Complex (4) Bothaandb Ans. (6) @. 1.102 CISC took many clock cycles to complete instruction. @) Many Two © Single (© Four Vans. (©) . 1.103 RISC processor is used to to decode their instruction. (@) Micro-code RAM __(b) Micro-code ROM (©) Mini-codeRAM (4) Mini-code ROM Ans. (0) Q.1.104 In, transistors are used for storing complexed instruction. @ecisc Q)AVR rIsc (ARM Ans : (a) @.1.105 RISC includes code siz (Smallest) Largest (©Medium ——@) Tiny YAns.: (6) @. 1.106 RISC has development time, (@) Longer (©) medium © Shorter (@) Very Longer Ans. (€) @. 1.107 Today's many of the chips supports many instruction as yesterday's chip (@)CISC and RISC (6) RISC and CISC (©) CISC and CISC ()RISCand RISC Ans. (b) @.1.108 CISC processors allowed overlap between instruction. (@) Consecutive _(b) Complex (©) Random @) Constant Ans. :(@) @.1.109 Arduino is__ (@) Anopen source platform (b) A Govern Software (©) Dedicated software (@ Botha andb YAns.: (8) @.1.110 In the arduino the symbol used to calculate module @! &%- OF GS — Ans.:0) Q. 4.111 operating voltage of arduino is @3v ()230v Sv GOV Ans. (6) (Advance Processors) ..Page no. (1-33) Q.4.412 Is clock speed of arduino UNO. (@)SOMHZ ——_(b) SOKHZ (©) 1OKHZ (a) toMHZ Ans. (@) 1.113 Is not comparison operator . @: @> ©< Me YAns:(0) Q.1.114 ON chip flash in ATmegat6 is (a) 16k (6) 10k (@)4K (AIS As. = (a) Q.1.115 on chip flash in ATmega328 is (@)31k (6)32k (©) 30k (4) 19K Q.1.116 The given program will produce the output as : void setup() { pinMode(LED_BUILTIN, OUTPUT); } void Ans. :(b) toop() { digitalWrite(LED_BUILTIN, HIGH); delay(1000); © Operational Equipment Manufacturer (@ Original Equipment Manufacturer YAns.:(b) Ans. :(@) (Advance Processors) ..Page no. (1-43) 0.1310 does not manufacture processors by itso (@Psoc (AVR (ric (ARM 0.1311 ARM licenses its cores to semi-conductor manufacturers to be integrated into standard . (a) ASIC (b) FPGA (c) APRA (4) SOC. Ans. : (a) @. 1.912 ARM is able to accelerate OEM time-to-market by on its architecture (@) Initiaizing —_(b) Capitalizing (©)Civiizing ——_(@) Controling Ans. :(b) 4, 1.313 By providing the and supporting services, customers can gain a jump on their design cycle ‘and obtain a competitive edge in their targeted market segment (a) Imeltigent Property. (b) Internet Property (6) Internal Processor _(@) Intellectual Property Ans. :(€) @. 4.314 ARM's Global Technology Partner Network Is the in the industries. (@ Smallest (b) Largest (©)Moderate (4) Tiny Vans. (b) @. 1.918 The ARM company is working to establish (@ Solution (6 Sections (© Standard (Slogans Ans. (6) 0.1316 is the industry “standard embedded croprocessor architecture @AVR ARM (ric (rise YAns.: (0) a.1317 is aleador of low-cost high performance (AVR () ARM (ric (Rise Ans. (0) ©. 1.318 Bus A nis connected directly! to ALU anmd B is connected through (@ Program Shifter (6) Barrel connector (© Instruction shifter (Barrel shifter Ans. :(@ 0. 1.319 Barrel Shiter can actually the data, (a) Preprocesses__(b)Posses (© Produce (Passes Ans. :(@) (New Syllabus w.e academic year 2019-20) (D6-25) Fech-Neo Publications ...A SACHIN SHAH VentureEmerging Trends in Electronics (MSBTE-Sem 6- Electr Q, 1,320 Barrel Shifter can shift to 5 (@) ShifttoRigh —_(&) Shift to Left (© Shift to up (®Bothaandb Ans: (@) Q. 1.321 ALU, Barrel Shifter is also circuit. (@) Combinational (6) Single (© Squential (@Bothbande Ans. Q. 1.322 Barrel Shifter carries out can take place in itselt (@ One Cycle (@) Two Cycle (©) Muliple Cycle (4) Halfoycle. Ans. Q, 1,823 Barrel Shifter splits up to operation (@) Scanning Speed _(b) Operating Speed (© Execution Speed (4) Maning Speed “Ans. (€) Q. 1.324 PC is also fand that can generate the address. (@) Resource Bank _(b) Register Bank (©) Procssor Part (4) None of the above Ans. : (b) @. 1.325 Address Bus is of __. (01064 bits () O10 bits (©)0t032 bits) Ot0 16 its Ans. (0) Q. 1.926 buses are of 92 bits. (@) Control (b) Address (© Data (@ Both b and c YAns. :@) @. 1.327 ALUis the aoronym of (@) Arithmatical and Logical Unit (&) Arothogonal and Logical Unit (© Arithmatical and legislation Unit (@ Both b and c Ans. : (a) Q. 1.328 _mode is common operating mode (@) Data mode (b) User mode (© Running Mode (4) Sysytem Mode Ans. :(b) Q. 1.329 Data registors are typically from @RStoRIS —@) R210 RIO (ROtORIS (4) RItORIS YAns. (0) @. 1.390 Is link registor. @R4 ORI (RU @R2 Ans. (b) @.1.331 __is a register where returned address is ut whenever a subroutine is called, (@) Link Registor __(b) General Purpose Registor (c) Stack Pointer (@) Accumulator Ans. (a) (Advance Processors) ...Page no, (1-44) @. 1.332 is program Counter. (RS @)R6 RIS (RI Ans. (¢) 2.1.33 Architecture is not synonymous with the single Organization (PIC (6) ARM (AVR — @cIsC Ans. :() Q. 1.334 ARM consist of (@)Register Bank _(b) Resonator (©)Radio Frequency (4)Repeaters—Ans.:(a) Q. 1.335 CPSR Stands for. (@) Constant Power Speed Ratio (©) Current Program Status Register (© Computer Professionals for Social Responsibility (@) Certified Professional Services Recruiter Ans. (b) . 1.836 T Bit indicates. (2) Whether the programmer is in Running Mode (0) Whether the Programmer is in thumb mode or in not thumb (©) Programmer isin Stop Mode (@ Both aandb YAns.:() Q. 1.837 Processor modes are. (@) InPrivileged Mode () InNon Previeged Mode (© Either in Privileged Mode or Non Privileged Mode (@ Both aandd YAns.:(0) is the Situation When We Reach the maximum value or minimum value because of an arithmetic operation (@) Overflow) Saturation (©) Underfiow (4) Botha and ¢ .1.999 RI4isa___ (2) Stack Pointer (6) Link Register (©) Special Function Register (6) General Purpose Register vans. :(0) Q. 1.340 PC Stores the values or results from, @21032 ©) 01016 (© 161032 (221064 V Ans. . 1.941 Each Byte in ARM Is Associated with, (Bits (0) Unique Address 1.938 YAns.: (c)Memory (4) Codes Vans. :(0) (New Syllabus wef academic year 2019-20) (06-25) Uadrect-neo Publications A SACHIN SHAH venteEmerging Trends in Electronics (MSBTI sem 6- Electronics) Q. 1.342 User Can use __Data Registers, in program and normal Operation. and that is User mode @32 8 ©1664 VANS. (©) 1.943 The Program counter and the current instruction which is being executed will be pointed by. Register (@RO ()RI3 (R14 @)RIS_— WAns.: (@) Q, 1.344 TOMI stands for. (@ Thumb debug management ICE (©) Thumb debug motipler ICE (©) Thumb data muliplier ICE, (@) Thing data multiplier ICE Ans: 0) 0. 1.345 Thumb is @ instruction (@) 32 bit (b) 64 bit (©) 8 bit (d) 16 bit ~Ans. :(d) |.346 The ARM 7 TOMI has core based version of the ARM architecture - (a) first (b) fifth (©) fourth (d) second Ans. : (c) |.347 ARM architecture version 4T has. pipeline (@)fivestage —_(b) three stage (]@rwostage (4) six stage Vans.:) Q. 1.348 Arm7TDMI has __ power consumption (@ Low (b) very tow high @ very Ans. (a) Q,1.349 Applications of ARM7 TOMI family (@) cellular phone. MP3 players (6) for display device (©) data analysis @) In gadgets Ans: (0) 41.350 In ARM processor when interrupt occurs Arm processor goes into following 9 mode (@) FIQ mode (©) abort mode (© supervisor mode (4) undefined mode V Ans. : (a) 0.1.51 ARM7TDMI processor compatible code (a) reverse (inverted (© forward (Bothaande —— YAns.:(6) 1.352 In the ARM Nomenclature ARMXTDMI,D and m stands for (@) division and muhiplier (©) data multiplier (© debugger and multiplication core has (Advance Processors) ..Page no. (1-45) (@) debug and fast moltiplier vans. : (2) Q. 1.953 Arm boot code must the state of the processor (@) constant (b) fixed (©) stable (@) change YAns.:(@) Q. 1.384 Executing 16 bit code the processor change into (a) thumb to ARM (b) Arm to ASIP (©) both aand d (@) Armto thumb “Ans. : (d) Q. 1.355 Embedded ICE has debug (on chip () code (© fetched (@) compile Ans. : (a) . 1.356 The OS is typically expected to be running in _ ‘and user application running in _ (@) privileged mode and nonprivileged mode (b)_non-privileged mode and privileged mode (©) interrupt privileged mode and privilege (@) privileged mode interupt privilege mode "vans. : (a) Q. 1.357 In ARM a particular kind of interrupt occurs ARM processor goes into mode (@ privileged mode (b) interrupt request mode (©) interupt privileged mode and privilege (@) interrupt nonprivileged mode YAns. :(b) 1.358 After reset the processor goes on (a) supervisor mode _(b) superior mode (idle mode (@ stop mode Ans. : (a) @. 1.359 In ARM there are registers divided among seven different processor modes. @30 200 ©3716 Ans. 310) (@. 1.960 In ARM Bank of registers are in each mode (visible (b) not visible (temporary —_(@) volatile 1.361 FIQ stands for (4) Forever Intermediate Que (©) first interact quote (© Fast Message Que (first interrupt request vans. :(@) @. 4.962 __and_are two interrupt modes of CPU (@)SPSR and RIQ (0) FIQand CPSR (©FIQandIRQ___(@) Bothaand b «Ans. (6) (New Syllabus w.e academic year 2019-20) (06-25) Tech-Neo Publications ...A SACHIN SHAH VentureEmerging Trends in Electronics (MSBTE-Sem 6- Electronics) (Advance Processors) ...Page no. (1-46) Q. 1.363 The standard ARM7TDMI processor core is a __ ‘macrocell. (@) soft (b) rough (©) hard @ Plane Ans. (0) Q. 1.364 CPI stands for__. (a) clocks per instrument (©) cell per instruction (b) clocks per instruction (@ clocks por instruction @. 1.373 state the processor used by ARM7? (@)8-bit CISC (0) 8-bit RISC (©)32-bitCISC ——(@)32-bIERISC Ans. :@ @. 1.374 state the instruction set used by ARM7? (@) 16-bit (b) 32-bit (64-bit 8-bit Q. 1.875 how many registers are used there in ARM7? Ans, Ans. (0) (0) 35 register (&) 37 register 2.1.65 The ARM7TOMA It includes support for the __ (32 register (6) 31 register ee . 1.376 The capabilty of ARM7-F instruction for a second (thumb) debug ie © multiple @ ICE Ans. (8) (NOMS — Qy1s0MIPS Q. 1.366 The embedded ICE module for _ debug support (125MIPs — (@) 130 MIPS Ans. (8) Cee tae, Q, 1.377 Which of the following has the same instruction set (off-chip (6) up chip. Ans. (0) as ARM 7 Q. 1.367 __ memory port used by the ARM7TDMI for both (@ARM6 (ARMS instruction and data accesses. (@ARMIed—(@) ARMvST Ans. (0) (@) double ©) four @.1.378 what are t.d.m,! stands for in ARM7TOMI7 (© single @ tree YAns.:(@) (@) timer, debug, multiplex, ICE @. 1.368 The ARM multiply instructions that produce a _ (©) Thumb, debug, moliplie, INCE result (©) Timer, debug, modulation (2) 30-bit 31-bit (©) Thumb, debug, multiplier ICE Ans: (0) (33-bit (32-bit Ans.:(@) | @ 4.379 ARMTTOMI Operates in which mode? Q. 1.389 which two approaches are been combined in the (@bigendian (6) tle endian ‘ARMSTOMI? (©)bothaandb (A) neitheranorb Ans. :(0) (@) maximum clock rate has been increased . 1.380 In which of the following ARM processor virtual (©) the CPI has been reduced memory is present (© minimum clock rate has been increased (@ ARM7DI (®) ARM7TDME-S (@ both a and b Ans. :(d) (©ARMTTDMI = (4) ARM7-S-_— Ans. :(@) @. 1.370 In the ARM7TDMI pipeline during a data access an | @.1.381 How many instruction pipeline is used in instruction fetch __ take place ARMIES? a (by both a and © (a) three stage (6) four stage oe (® camer Ans. :(d) (@)five stage —_() two stage VAns.:(0 @. 1.871 In the ARM7TDMI core the hardware is | @. 4.982 How many bit data bus is used in ARM7EJ-S? axpported (a) 32 bit (16 bit (@) double-stepping _(b)threestepping seit (@ both a and e Vans. (©)single-stepping —_(@) nostepping_Ans.:(© | @, 4,983 The cache memory for ARM710T @. 1.372 The ARMIOTDMI is the current __ ARM (a) 12kb (b) 16kb (c) 8k (4)32kb.- VAns. (0) processor core . 1.984 What are the profiles for ARM architecture? (low-end ——_(b) low. start WAR AM ©highend —_—_(@) high-stat ¥ Ans. (ARM @RM vans. (0 (New Syllabus we.f academic year 2019-20) (D6-25) TB rech-neo Pubications..a SACHIN SHAH VentureQ. 1.985 The address space in ARM is _ (2°24 (b)264 IMG )IN2_—-VAn 4. 1.986 In the ARM , PC is implemented using _ (@) caches (@) heaps (©) general purpose registers (A) stack Ans. (@) Q. 1.987 Define __is a measure of how much work a processor does in a clock cycle @CIP — @)CRL )IPC_ PIC Ans. () . 1.388 ARM Processor involves organization such a (@) Virtual Serial Interface Alliance () Virtual Socket Interface Alliance (©) Visional Socket Internal Alliance (@) Virtual Socket Internal Association @.1.389 OEM stands for_? (2) Operational Extemal Manufacturer (6) Original Extemal Manufacture (© Operational Equipment Manufacturer (@) Operational Equipment Manufacturer :@) @. 1.390 ARM processors where basically designed for Vans. (0) Vans. (a) Main frame systems (b) Distributed systems (©) Mobile systems (4) Super computers Ans. : (0) Q. 1.381 The banked registers are used for (@) Switching between supervisor and interrupt mode (b) Extended storing (©) Saine as general purpose registers (@ None of the mentioned Q. 1.392 Each instruction in ARM machines is encoded into Word (a) 2byte (b) 3 byte @Abyte @abyte Q. 1.393 The processor used by ARM7 for___. (@)BbitCISC —_(b) 8-bit RISC (©)32bit CISC ~ (@) 32-bit RISC Q, 1.394 The instruction set used by ARM7 Is_ (a) 16-bit instruction set (b) 32-bit instruction set. (©) 64-bit instruction set) 8-bit instruction set Ans. Vans. (a) YAns.: (0) YAns.: (d) ) Q. 1.995 Which is the most popular ARM cores of families? (@) ARM710A_(b) ARM7TDML and ARM7TDMI-S (©) ARM720T_(@) ARM710 YAns.: (6) (New Syllabus we,f academic year 2019-20) (06-25) (Advance Processors) ...Page no. (1-47) {Q. 1.396 The Operating Frequency of ARIM7 processor is, (@) 1SOMH () 180MHz (©) 200M (@)120MHz Ans. () . 1.997 Address Rango of ARM processor is (@) 32 bit wide () 8 bitwide () 26bit wide (@) 16bit wide 2) Q,1.998 ARM7TOMI processor doos not Include the ‘application tke (@) Digital stet eamern (b) Pager (©) Broadcasting (4) Wireless Handset YAns. (6) @. 1.399 RAM of ATmoga328 is, @)2KB_() 2KB (©3KB@)44KB Ans. (a) . 1.400 ATmegat6 has WO pins 16 4 OG Ans. (a @.1.401 ATmega328 has VO pins (4) 6pin () M4pin (©) L6pin_()Apin Ans. (b) 1.402 Atmega2560 has VO pins 4S O44 SH SS YAns @. 1.403 Atmogat6 consist pin number (12 ()28 2B Ans. () @. 1.404 Atmegas28 consist __pin number (12 2B O22 WIS — YAns0) . 1.405 ATmega2560 consist ___ pin number (101 (100 (©) 102 @)103._—-Ans. (0) 1 1.406 ARM architecture has_bit architecture, @8 O16 ©R WEF — Vans.r(@) Q. 1.407 ARM has __general purpose register, @6 W8 |G WR — VAmr(6) @. 1.408 ARM stands for () Advanced Rate Machines (b) Advanced RISC Machines (©) Attificial Running Machines (8) Aviary Running Machines YAns. (0) @, 409 Instruction execution cyclos are___ in CISC G1 )2 ]Unique (Different VAns. 1 (@) . 1.410 The main Importance of ARM mlcro-processors Is, providing operation with (@) Low cos and low power consumption (b) Higher degree of multi-taskin Tl reci-seorulations A SACHIN SHAM VentreEmerging Trends in Electronics (MSBTE-Sem 6- Electronics) (©) Lower errr or glitches (4) Efficient memory management YAns. (a) Q. 1.411 The architecture feature used in ARM 9 processor is (a) Harvard cise (&) Von Neumann (6) Hardwire Q. 1.412 ARM processors where basically designed for Vans. : (a) (@) Main frame systems (b) Distributed systems (©) Mobile systems 4) Super computers YAns.: (6) Q. 1.413 The ARM processor doesn't support Byte address ability? (@)TRUE (6) FALSE Vans. :(b) Q. 1.414 The address space in ARM is__ (a) 224 (b) 2964 ©2M6 (a)2932 YAns.: (0) @. 1.415 In ARM7 the word may be divided into four bytes, (a) 8-bit (b) 16-bit (]Ibit —_ (4) 64-bit Ans. : (a) Q.1.416 In ARM processor which of the following register act as a program counter G)RIZ ORI ORM RIS YAns.:(@) @. 1.417 ARM instruction consists _address format @2 3 Ol 4A Ans. (0) . 1.418 ARMs addressable. (a Bit (Byte (©) Word (@) Quad Word YAns. :(b) @.1.419 Memory can be accessed in ARM systems by instructions. i) Store ii) MOVE iii) Load iv) arithmetic v) logical @ is © Ans. :(b) @iiv @ @. 1.420 RISC stands for (a) Restricted Instruction Sequencing Computer (b) Restricted Instruction Sequential Compiler (©) Reduced Instruction Set Computer (@) Reduced Induction Set Computer VAns. : (0) (Advance Processors) ...Page no. (1-48) Q. 1.421 In ARM, PC is implemented using (b) Heaps (@) Stack (a) Caches (©) General purpose register Ans. (¢) ©. 1,422 The additional duplicate register used in ARI machines are called as (6) Banked registers (4) Duplicate registers Ans. :() (a) Copied-registers (©) Extra registers Q. 1.423 The banked registers are used for (a) Switching between supervisor and interrupt mode (b) Extended storing () Same as other general purpose registers (@) None of the mentioned VAns. (8) Q. 1.424 Each instruction in ARM machines is encoded into Word. (a) 2 byte (b) 3 byte (4 byte @B bye @. 1.425 Which functional unit of ARM family architecture is responsible for upgrading the address register contents before the core reads or writes the next register value from memory location? (a) Databus —_(b) Barrel Shifter (€)Incrementer (4) Instruction Decoder ¥ Ans. :() @. 1.426 In ARM processor which of the following is Link Register G@)RI2Z ORI ORY @RIS — VAns:(6 . 1.427 In ARM processor which of the following is Stack Pointer @Ri2 RIB (Ris @Ris YAns.:(b) @. 1.428 Von Neumann architecture processor will take fiow many number of clock cycles to execute one instruction @! ®2 ©3 @4 Vans (0) Q, 1.429 Harvard architecture processor will take how many umber of clock cycles to execute one instruction @lse2 ©32 (jae Ans. :(0) @. 1.430 Number of status registers available in ARM processor is @2 ©4 ©6 ws VAn (New Syilabus w.ef academic year 2019-20) (06-25) Tl rech-neo Publications ...A SACHIN SHAH Venturejing Trends in Electronics (MSBTE-Sem Electronics) Q, 1.431 Which type of non-privileged processor mode is entered due to rising of high priority of an interrupt? (@) User mode (b) Fast Intemupt Mode (FIQ) (© Imerrupt Mode (RQ) (@ Supervisor Mode (SVC) Ans. (b) Q. 1.432 Abort mode generally enters when G@) An attempt access memory fails (b) Low priority interrupt is raised (©) ARM processor ison rest (4) Undefined instructions are to be handled Ans. : (a) Q. 1.433 In the process of pipelining, which instructions are fetched from the memory by the ARM processor during the execution of current instruction? @) Previous (b) Present (Next @)Aloftheabove Ans. = (€) Q. 1.434 If the three stages of execution in pipelining are ‘overlapped, how would be the speed of execution? (@) Higher (b) Moderate (©)Lower (4) Unpredictable @. 1.435 ARM was orginally known as (@) Aeron RISC Machine () Advanced RISC Machine (©) Ashton Raggat McDougall (@) Automatic RISC Machine ) @.1.496 What are the values of the | and F bits in the Program Status Register on reset? (@)1=0,F=0* (by II, Pal © 1-0F (4) Tet, Feo YAns.: (6) {@. 1.437 Which of the following register in ARMT is used to point to the location of currently executing instruction in a program? (RIB RIS (RIS @RIZ Ans. (0) @. 1.498 In the ARM Nomenclature ARMXTOMI, D and M stand for - (a) Debug and Fast Multiplier units are present (b) Division and Multiplier units are present (©) Debugger and Multiplier units are not present @ Division and Multiplier units are not present YAns.: (a) YAns. (a) YAns.: 1.439 Which of the following statements are true with respect to pipelining? Pipelining is an implementation technique whereby multiple instructions are overlapped in execution, It is not visible to the programmer Page no. (1-49) (Advance Processors) Each step is called a pipe stage or pipe segment UL. Pipeline machine cycle is the time required to move an instruction one step down the pipeline (a) All are true (b) Land IT are true (and Maree (4) None of them are true Ans. : (a) @.1.440 The ___ instruction is the basic mechanism is [ARM for changing the flow of control (@) Store (b) Branch (©) Controt (@) Direct Flow Ams. :(b) 1.441 An ARM instruction is (@)8bits long (b) 16 bits long (©)32bits long (4) 64 bits long Ans. (©) 1.442 ARMIOTDMIis a (a) 3 - stage pipeline processor (©) 5— stage pi (©) 6 stage pipeline processor (4) 8 ~ stage pipeline processor Vans. (0) @. 1.443 When a procedure call is made in an ARM, the retum address is automatically placed into (@) Programs Counter (15) (©) Link Register (r14) (© Stack Pointer (15) (4) Stack Pointer (13) Ans. :(b) @.1.444 In which of the following modes’ of an ARM processor, CPSR can't be modified? (a) Fast Interrupt Processing (FIQ) mode (b) Normal Interrupt Processing (IRQ) mode (©) Usee mode (@) Supervisor (SVC) mode ¥ Ans. (0) @. 4.445 On a hard reset, ARM enters which ofthe following modes? (a) Fast Interrupt Processing (FIQ) mode (6) Normal interrupt Prstessing (IRQ) mode (©) User mode (@) Supervisor (SVC) mode Ans. (d) Q. 1.446 Pipe-tining is a unique feature of (@Risc cise (ISA @Ise vans. Q, 1.447 The CISC stands for (@) Computer Instruction Set Compliment (©) Complete Instruction Set Compliment (New Syllabus wee academic year 2019-20) (06-25) Ta rech-Neo Publications ..A SACHIN SHAW Venture(©) Computer Indexed Set Components (@) Complex Instruction set computer. Ans. : (4) Q. 1.448 Each stage in pipelining should be completed within cycle @1 ©2 ©3-@4 Ans. (a) Q, 1.449 The ARM processor registers R13, R14, and AIS are architecturally used for special purposes. Which is the correct respective sequence of special purpose registers? (@) PC, LR, SP ()LR, PC, SP (©) SP, LR, PC @LR,SP,PC Ans. : (6) . 1.450 The ARM processor like all RISC processors uses a architecture (@)Datscopy (0) Load (©)Load-store (A) Store Ans. (0) Q. 1.451 What is the size of general purpose registers in ‘ARM processor (a) 8-bit (b) 16-bit Obit (a) 32-bit YAns.:(@) @. 1.452 In ARM processor data processing is carried out in (@) Memory (b) Registers (©) Memory and Registers () Instruction decoder YAns.:(b) Q. 1.453 Which of the following ARM processor mode is not a privileged mode (@) Abort mode _(b) System mode (©) Usermode (4) Undefined mode “Ans. : (€) Q. 1.454 ARM9 has pipelining stages @5 6 ©7 @4 — Ans.:(a) Q.1.455 How many cycles are required to complete the execution of one instruction in 6 stage pipelining processor? @5 6 ©7 @8 @.1.456 When the ARM processor can't decode the instruction it enters into (@) Abort mode _(b) System mode (©)Usermode _(@) Undefined mode @. 1.457 When the ARM processor attempts to access ‘memory without the correct access permission it Ans. : (6) vans. :(d) enters into (@) Abort mode (b) System mode (©)Usermode (4) Undefined mode Ans. : (a) @.1.458 ARM11 is a (@)3- stage pipeline processor (b) 5 ~ stage pipeline processor (©) 6~stage pipeline processor (4) 8 ~stage pipeline processor Ans. :() Q. 1.459 An ARM instruction in thumb mode is (@)Bbits long —_(b) 16 bits long (©) 32bits long (4) 64 bits long Ans. :() 1.480 In ARM7TDMI-S , S stands for (@) System Programming (b) Synthesizable (©) Synchronous (@) Supervisor mode Ans. : (0) @.1.461 In the ARM Nomenclature ARMXTOMI, T and | stand for (@) Thumb and Incrementer (b) Throughput and Incrementer (©) Thumb and In circuit Emulator (@) Throughput and In circuit emulator “Ans. : (@) . 1.462 The architecture feature used in ARMT processor is (@) Harvard (b) Von Neumann, jeaisc (@) Hardwire YAns. (6) {Q. 1.463 Aurdino programs also supports codes (@) Assembly C (JAVA jc (@AVRC YAns.:(@) 1.464 In ARM architecture B bus is connected through (@ ALU (©) Barrel shifter ()Registers (4) None ofthe above Ans. :(b) @Q. 1.465 The ARM core uses @RIsc (b)cIsc (©Bothaandb (4) None of the above Ans: (a) Architecture. 166 ARM Processor specifically designed for to reduce (a) Size (©) Both aand b (b) Power Consumption (@) None of the above v Ans. (©) @.1.467 ARM Processor core is a key component of bit embedded system O16 ©2 wes (8 Vans. (0 (New Syllabus w.e,f academic year 2019-20) (D6-25) [Blrec-neo Publications ...A SACHIN SHAH VentureEmerging Trends in Ele @. 1,468 RISC Philosophy implemented with __ major deign goals. @4 6 ©8 WIE Is the processing of instruction broken Wiuiastnasien vanesoy (@ Resistive switching Random Access Memory 0.27 Mem feabres nave properties We _ a prelates Haney crema (4) Nonvolatile nature, linearity (@) None of the above Ans. : (a) (b) Volatile nature, non-linearity Q. 2.47. Select correct option for above statement (©) Volatile nature, linearity ‘Statement 1: In Li-ion batteries lithium ions move (@) Nonvolatile nature, non-linearity Y Ans. : (d) from the negative electrode to the positive electrode Q.2.38 Memristor is defined by relation during discharge, (@) do=Medq (6) dq=C+dv Statement 2: In Li-ion batteries lithium ions move OwaLed Wavenea Thea Gah {rom the positive electrode to the negative electrode during charging. (New Syllabus wer academic year 2019-20 (06-25) Ua rech-neo Publications A SACHIN SHAH Ventre