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UNIT 7 IO Interfacing

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30 views18 pages

UNIT 7 IO Interfacing

Uploaded by

kinjalbenanilbhaisolanki
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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UNIT:7

I/O Interfacing
Outline:
Interfacing Concepts, Ports,

Interfacing Of I/O Devices,

Interrupts In 8085,

Programmable Interrupt Controller 8259A,

Programmable Peripheral Interface 8255A


Introduction to Interfacing Concepts
Interface is the path for communication between two components.

Interfacing is of two types, memory interfacing and I/O interfacing.


There are various communication devices like the keyboard, mouse,
printer, etc.
So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers.

This type of interfacing is known as I/O interfacing.


8085 Interfacing Pins
Following is the list of 8085 pins used for interfacing with other
devices:

1. A15-A8 (Higher Address Bus)


2. AD7-AD0(Lower Address/Data Bus)
3. ALE
4. RD
5. WR
6. READY
There are two ways of communication in which the microprocessor can
connect with the outside world.

Serial Communication Interface : In this type of communication, the


interface gets a single bit of data from the microprocessor and sends it bit by
bit to the other system serially and vice-a-versa.

Parallel Communication Interface : In this type of communication, the


interface gets a byte of data from the microprocessor and sends it bit by bit to
the other systems in simultaneous (or) parallel fashion and vice-a-versa.

Types of I/O :
Interrupts in 8085
An Interrupt is a process where an external device can get the attention of the
microprocessor.
The process starts from the I/O device
The process is asynchronous.
An interrupt is considered to be an emergency signal that may be serviced.
The Microprocessor may respond to it as soon as possible.
When the Microprocessor receives an interrupt signal, it suspends the currently
executing program and jumps to an Interrupt Service Routine (ISR) to respond to the
incoming interrupt.
Each interrupt will most probably have its own ISR.
Responding to an interrupt may be immediate or delayed depending on whether the
interrupt is maskable or non-maskable.
Interrupts are the signals generated by the external devices to request the
microprocessor to perform a task.

There are 5 interrupt signals as follows:

1. TRAP

2. RST 7.5

3. RST 6.5

4. RST 5.5

5. INTR
Classification of Interrupts
Programmable Peripheral
Interface 8255A
The 8255A is a general purpose programmable, parallel I/O device.

It is designed to transfer the data from simple I/O to interrupt I/O under certain
conditions as required.

It can be used with almost any microprocessor.

It consists of three 8-bit bidirectional I/O ports (24 I/O lines) which can be
configured as per the requirement.

It is flexible, versatile and economical but somewhat complex.

The intent is to provide complete I/O interface in single chip.

This chip directly interfaces to data bus of the processor.


8255A I/O port
8255A I/O port :
Block diagram :8255A
8255A Architecture: Control
Logic
Programmable Interrupt
Controller 8259A
The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for use with the
8085 and 8086 microprocessors.
The 8085 has only five number of hardware interrupts: TRAP,RST 7.5,RST 6.5,RST 5.5 and
INTR.
The 8259 can be used for applications that use more than five numbers of interrupts from
multiple sources.
The main features of 8259 are listed below :
Manage eight levels of interrupts.
Eight interrupts are spaced at the interval of four or eight locations.
Resolve eight levels of priority in fully nested mode, automatic rotation mode or specific
rotation mode.
Mask each interrupt individually.
Read the status of pending interrupt, in-service interrupt, and masked interrupt.
Accept either the level triggered or edge triggered interrupt.
8259 Internal Block
Diagram
Read/Write Logic : When address line A0 is at logic 0, the controller is
selected to write a command word or read status. The Chip Select logic and A0
determine the port address of controller.

Control Logic : It has two pins: INT as output and INTA as input. The

INT is connected to INTR pin of MPU.

Interrupt Registers and Priority Resolver :


1. Interrupt Request Register (IRR)

2. Interrupt In-Service Register (ISR)

3. Priority Resolver

4. Interrupt Mask Register (IMR)


Interrupt Request Register (IRR) and Interrupt In-Service Register (ISR)
Interrupt input lines are handled by two registers in cascade – IRR and ISR

IRR is used to store all interrupt which are requesting service.

ISR is used to store all interrupts which are being serviced.

Priority Resolver : This logic block determines the priorities of the bit set in
IRR. IR0 is having highest priority, IR7 is having lowest priority.

Interrupt Mask Register : It stores bits which mask the interrupt lines to be
masked. IMR operates on the IRR. Masking of high priority input will not affect
the interrupt request lines.
THANK YOU

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