Introduction

 An interrupt is an event which informs the

CPU that its service (action) is needed.
 Sources of interrupts:
 internalfault (e.g.. divide by zero, overflow)
 software
 external hardware :
 maskable
 nonmaskable

 reset
 Basic Procedure for Processing
Interrupts
 When an interrupt is executed, the p:
 finishes executing its current instruction (if any).
 saves (PUSH) the flag register, IP and CS
register in the stack.
 goes to a fixed memory location.
 reads the address of the associated ISR.
 Jumps to that address and executes the ISR.
 gets (PULL) the flag register, CS:IP register from
the stack.
 continues executing the previous job (if any).
 8259 PROGRAMMABLE
INTERRUPT CONTROLLER
 It is a tool for managing the interrupt requests
according to the instructions written into its control
register.
 It can be set up to work with either the 8085 or the
8086/8088 microprocessor mode.
 It can be expanded to 64 priority levels by cascading
additional 8259s.
 It can be set up to accept either the level-triggered or
the edge-triggered interrupt requests
FIGURE 9-4 Block diagram and pin definitions for the 8259A Programmable Interrupt Controller (PIC). (Courtesy of Intel Corporation.)

John Uffenbeck
The 80x86 Family: Design, Programming, Copyright ©2002 by Pearson Education, Inc.
and Interfacing, 3e Upper Saddle River, New Jersey 07458
All rights reserved.
 Pin description
 8-bit bi-directional data bus, one address line is needed,
PIC has two control registers to be programmed, you can
think of them as two output ports or two memory location.
 The direction of data flow is controlled by RD and WR.
 CS is as usual connected to the output of the address decoder.
 Interrupt requests are output on INT which is connected to the
INTR of the processor. Int. acknowledgment is received by
INTA.
 IR0-IR7 allow 8 separate interrupt requests to be inputted to
the PIC.
 sp/en=1 for master , sp/en=0 for slave.
 CAS0-3 inputs/outputs are used when more than one PIC to
cascaded.
 BLOCK DIAGRAM OF 8259
 READ/WRITE LOGIC- When the address line Ao is at
logic 0,the controller is selected to write a command or
read a status.
 CONTROL LOGIC-This block has two pins: INT
(Interrupt) as an output and INTA (Interrupt
Acknowledge) as an input.
 CASCADE BUFFER/COMPARATOR-This block is used to
expand the number of interrupt levels by cascading two
or more 8259s

-
Example of two cascaded PICs
 Continued…
 INTERRUPT REGISTER AND PRIORITY
RESOLVER-
 The Interrupt Request Register (IRR) has eight
input lines (IRo-IR7) for interrupts.
 The In-Service register (ISR) stores all the levels
that are currently being serviced.
 The Interrupts Mask Register (IMR) stores the
masking bits of the interrupt lines to be masked.
 The Priority Resolver (PR) examines these three
registers and determines whether INT should be
sent to the MPU.
 FIGURE 9-7 All interrupt requests must pass through the PIC’s interrupt request register (IRR) and interrupt mask register (IMR). If
put in service, the appropriate bit of the in-service (IS) register is set.

John Uffenbeck
The 80x86 Family: Design, Programming, Copyright ©2002 by Pearson Education, Inc.
and Interfacing, 3e Upper Saddle River, New Jersey 07458
All rights reserved.
 OPERATION
 PIC is to be initialized and programmed to control its
operation.
 The operation in simple words:
when an interrupt occurs , the PIC determines the highest
priority, activates the processor via its INTR input, and
sends the type number onto the data bus when the
processor acknowledges the interrupt.
 Priority:
What is used in PC is fully nested mode. That is the lowest
numbered IRQ input has highest priority. Lower priority
interrupts will not be forwarded to the processor until the
higher priority interrupts have been serviced.
 Continued…
 The 8259 requires two types of control words:
Initialization Command Words (ICW) and
Operational Command Words (OCW).
 The ICW are used to set up the proper
conditions and specify RST vector addresses.
 The OCW are used to perform functions such as
masking interrupts, setting up status-read
operations, etc.
 Commonly used priority modes
 FULLY NESTED MODE-This is a general- purpose
mode in which all IRs (Interrupt requests) are
arranged from highest to lowest, with IRo as the
highest and IR7 as the lowest.
 AUTOMATIC ROTATION MODE-In this mode, a
device after being serviced receives the lowest
priority.
 SPECIFIC ROTATION MODE-In this the user can
select any IR for the lowest priority, thus fixing
all other priorities.
 END OF INTERRUPT
 After the completion of an interrupt service, the
corresponding ISR bit needs to be reset to
update the information in the ISR.This is called
End-of-Interrupt (EOI) command.
 It can be issued in three formats:
:-Non specific EOI command
:-Specific EOI command
:-Automatic EOI