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8259A Interrupt Controller 220210107078

The 8259A is a programmable interrupt controller that manages multiple interrupt requests for Intel microprocessors, allowing for efficient multitasking and real-time processing. It supports up to 8 interrupt requests, programmable priority levels, and can be cascaded to handle up to 64 interrupts. The controller features various modes and can mask individual interrupts, making it suitable for applications in embedded systems and industrial automation.

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4 views18 pages

8259A Interrupt Controller 220210107078

The 8259A is a programmable interrupt controller that manages multiple interrupt requests for Intel microprocessors, allowing for efficient multitasking and real-time processing. It supports up to 8 interrupt requests, programmable priority levels, and can be cascaded to handle up to 64 interrupts. The controller features various modes and can mask individual interrupts, making it suitable for applications in embedded systems and industrial automation.

Uploaded by

vegadkushal9
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Microprocessor and

Interfacing (3160712)
8259A Interrupt
Controller

Present by : Vinit Roshiya


(220210107078)
Introduction to
Interrupts
• An interrupt is a signal to the processor
for attention.
• It halts the current execution to perform
a higher-priority task.
• Essential for multitasking and real-time
processing environments.
What is an Interrupt
Controller?
• Manages multiple interrupt requests
from devices.
• Sends interrupts to the CPU in an
organized way.
• 8259A handles and prioritizes hardware
interrupts efficiently.
Features of 8259A

• Supports 8 interrupt requests (IR0-


IR7).
• Cascade up to 64 interrupt levels.
• Programmable priority levels.
• Maskable & non-maskable interrupts.
• Edge & level-triggered modes.
• Compatible with 8085, 8086
microprocessors.
Pin Configuration of
8259A
• D0-D7: Data Bus (bidirectional).
• INT: Interrupt output to CPU.
• INTA: Interrupt Acknowledge.
• RD/WR: Read/Write Control.
• CS: Chip Select.
• IR0-IR7: Interrupt Request Inputs.
• SP/EN: Slave Program/Enable.
3 Unique Pins to understand
Chip Select (CS) :
The Chip Select pin acts as an enable signal that must be active
(low) for the
microprocessor to interact with the 8259A for programming or
status monitoring.
Slave Program (SP) / Enable Buffer (EN) :
When the 8259A is not operating in buffered mode, the SP/EN pin acts as an inp
used to configure the 8259A as either a master or a slave in a cascaded
errupt system.
The choice between buffered and non-buffered mode is made during the
tialization of the 8259A using Initialization Command Words (ICWs).

Cascading Lines (CAS0,CAS1,CAS2) :


e 8259A Programmable Interrupt Controller (PIC), the CAS0 and CAS1
along with CAS2, are cascade lines used when you need to expand the number
terrupt inputs beyond the 8 provided by a signal 8259A.
Functional Blocks of
8259A
• Interrupt Request Register (IRR): Holds
incoming interrupts.
• In-Service Register (ISR): Tracks active
interrupts.
• Priority Resolver: Determines interrupt priority.
• Interrupt Mask Register (IMR): Masks/enables
interrupts.
• Control Logic: Manages CPU-PIC
communication.
Above figure shows the internal block diagram of the 8259A.
It includes eight blocks : control logic, Read/Write logic, data
bus buffer, three registers (IRR, ISR, and IMR), priority
resolver, and cascade buffer.
This diagram shows all the elements of a programmable
device, plus additional blocks. The functions of some of these
blocks need explanation, which is given below.

READ/WRITE LOGIC
This is a typical Read/Write control logic. When the address
line A0 is at logic 0, the controller is selected to write a
command or read a status. The Chip Select logic and A0
determine the port address of the controller.

CONTROL LOGIC
This block has two pins: INT (Interrupt) as an output, and
INTA (Interrupt Acknowledge) as an input. The INT is
connected to the interrupt pin of the MPU. Whenever a valid
interrupt is asserted, this signal goes high. The INTA is the
Interrupt Acknowledge signal from the MPU.
INTERRUPT REGISTERS AND PRIORITY
RESOLVER
The Interrupt Request Register (IRR) has eight input
lines (IR0-IR7) for interrupts.
When these lines go high, the requests are stored in
the register. The Interrupt Service Register (ISR)
stores all the levels that are currently being serviced,
and the Interrupt Mask Register (IMR) stores the
masking bits of the interrupt lines to be masked. The
Priority Resolver (PR) examines these three registers
and determines whether INT should be sent to the
MPU.

CASCADE BUFFER/COMPRATOR
This block is used to expand the number of interrupt
levels by cascading two or more
8259As. To simplify the discussion, this block will not
be mentioned again.
Working of 8259A

• Interrupt Request from device.


• CPU sends Interrupt Acknowledge.
• Priority Resolver selects highest
priority.
• Interrupt Vector sent to CPU.
• CPU executes Interrupt Service Routine.
• End of Interrupt command sent to reset
ISR.
Types of Interrupts

• Maskable Interrupts: Can be


enabled/disabled by software.
• Non-Maskable Interrupts (NMI): Cannot
be disabled, high priority.
Cascading Multiple
8259A Controllers
• Up to 8 slave 8259A chips connected to
a master.
• Supports up to 64 interrupt lines.
Advantages of 8259A

• Efficient multi-interrupt handling.


• Programmable priority levels.
• Reduces CPU overhead.
Applications of 8259A

• Embedded Systems.
• Real-Time Operating Systems.
• Industrial Automation.
• Computer Peripherals.
Summary
The 8259A is a programmable interrupt controller designed to work with Intel microprocessors 8085, 8086, and 8088.
The 8259A interrupt controller can

• Manage eight interrupts according to the instructions written into its control registers.
This is equivalent to providing eight interrupt pins on the processor in place of one
INTR (8085) pin.
• Vector an interrupt request anywhere in the memory map. However, all eight interrupts
are spaced at the interval of either four or eight locations. This eliminates the major
drawback of the 8085 interrupts in which all interrupts are vectored to memory locations on page 00H.
• Resolve eight levels of interrupt priorities in a variety of modes, such as fully nested
mode, automatic rotation mode, and specific rotation mode.
• Mask each interrupt request individually.
• Read the status of pending interrupts, in-service interrupts, and masked interrupts.
• Be set up to accept either the level-triggered or the edge-triggered interrupt request.
• Be expanded to 64 priority levels by cascading additional 8259A.
• Be set up to work with either the 8085-microprocessor mode or the 8086/8088 microprocessor mode.
Thank You

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