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Compression

compression in dft

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ctulasi1411
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24 views2 pages

Compression

compression in dft

Uploaded by

ctulasi1411
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Need of scan flop:

The goal of scan design is to make a difficult-to-test sequential circuit behave (during the testing process)
like an easier-to-test combinational circuit. Achieving this goal involves replacing sequential elements with
scannable sequential elements (scan cells/scan flops) and then stitching the scan cells together into scan
registers, or scan chains. You can then use these serially connected scan cells to shift data in and out
when the design is in scan mode.

“Before Scan” design is difficult to initialize to a known state, making it difficult to both control the internal
circuitry and observe its behavior using the primary inputs and outputs of the design. In a "Scan design"
scan memory elements (scan flops) replace the original memory elements (normal flops) imparting
controllability and observability to the design (prime requirement for the design being testable), when
shifting is enabled.

1) Transition-delay is related to slow-to-rise or slow-to-fall faults at a particular node. Whereas path-


delay is related to slow-to-rise or slow-to-fall faults of a particular path.

2) The reason for transition-delay at a node is some manufacturing defect at that node (more
resistive node). The reason for path-delay is some manufacturing defect that is distributed
through out the path (more resistive path). Let me explain this in detail with an example.

Transition delay is similar to stuck-at atpg, except that it attempts to detect slow-to-rise and slow-
to-fall nodes, rather than stuck-at-0 and stuck-at-1 nodes. A slow-to-rise fault at a node means
that a transition from 0 to 1 on the node doesn’t produce the correct results at the maximum
operating speed of the design. Similarly a slow-to-fall fault means that a transition form 1 to 0 on
a node doesn’t produce the correct results at the maximum speed of the design. Transition delay
fault targets single point defects.

Burnin test is the technique of estimating the life time of the chip by providing stress in the form
temperature , voltage and current.

COMPRESSION:
WHAT IS COMPRESSION?
Compression is a technique of adding some additional on-chip hardware before
the scan chains to decompress the stimuli coming from the ATE and to compress
the response going to ATE.
It also controls large number of internal scan chains by using external channels.
2. why compression?
Compression is used to reduce test time, test data volume and test cost.
3.Blocks in EDT
Decompressor: LFSR, PHASE SHIFTER
Compactor: Mask logic. xor logic
LFSR: linear feedback shift register: To generate random patterns and these
patterns fed to phase shifter.
Phase shifter: It is a xor logic, used to block the repeated patterns , if any
generated by the lfsr.
Output of phase shifter is fed to inputs of internal scan chains.

Compactor: It consists of mask logic, xor logic.


Mask logic: it consists of mask shift register, mask hold register, mask decoder.
Mask logic is used to mask the x value and to avoid aliasing effect.
Xor logic: xor logic is used to compress the response coming from the masking
logic.

X-masking techniques:
1hot masking: only one internal scan chain response is propagated trough each
external channel at a time by blocking all other chains. It not allows x values
Flexible masking: It allows multiple internal chain responses, it blocks only the
internal chains that generate x values.

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